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535.171.04

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This commit is contained in:
Bernhard Stoeckner
2024-03-21 14:22:31 +01:00
parent 044f70bbb8
commit c042c7903d
36 changed files with 691 additions and 265 deletions
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20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r538_27
#define NV_BUILD_BRANCH r538_49
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r538_27
#define NV_PUBLIC_BRANCH r538_49
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r538_27-451"
#define NV_BUILD_CHANGELIST_NUM (33992350)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r538_49-495"
#define NV_BUILD_CHANGELIST_NUM (34058561)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r538_27-451"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33992350)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r538_49-495"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34058561)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r538_27-6"
#define NV_BUILD_CHANGELIST_NUM (33992350)
#define NV_BUILD_BRANCH_VERSION "r538_49-2"
#define NV_BUILD_CHANGELIST_NUM (34058561)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "538.46"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33992350)
#define NV_BUILD_NAME "538.52"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34058561)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.161.08"
#define NV_VERSION_STRING "535.171.04"
#else

1
src/nvidia-modeset/Makefile
View File

@@ -95,6 +95,7 @@ endif
ifeq ($(TARGET_ARCH),aarch64)
CFLAGS += -mgeneral-regs-only
CFLAGS += -march=armv8-a
CFLAGS += -ffixed-x18
CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics)
endif

2
src/nvidia-modeset/include/nvkms-hdmi.h
View File

@@ -38,7 +38,7 @@ void nvUpdateHdmiInfoFrames(const NVDispEvoRec *pDispEvo,
void nvDpyUpdateHdmiPreModesetEvo(NVDpyEvoPtr pDpyEvo);
void nvDpyUpdateHdmiVRRCaps(NVDpyEvoPtr pDpyEvo);
void nvUpdateHdmiCaps(NVDpyEvoPtr pDpyEvo);
void nvSendHdmiCapsToRm(NVDpyEvoPtr pDpyEvo);
void nvLogEdidCea861InfoEvo(NVDpyEvoPtr pDpyEvo,
NVEvoInfoStringPtr pInfoString);

23
src/nvidia-modeset/src/nvkms-dpy.c
View File

@@ -71,7 +71,7 @@ static NvBool ValidateEdid (const NVDpyEvoRec *pDpyEvo,
const NvBool ignoreEdidChecksum);
static void LogEdid (NVDpyEvoPtr pDpyEvo,
NVEvoInfoStringPtr pInfoString);
static void ClearEdid (NVDpyEvoPtr pDpyEvo);
static void ClearEdid (NVDpyEvoPtr pDpyEvo, const NvBool bSendHdmiCapsToRm);
static void ClearCustomEdid (const NVDpyEvoRec *pDpyEvo);
static void WriteEdidToResman (const NVDpyEvoRec *pDpyEvo,
const NVEdidRec *pEdid);
@@ -90,14 +90,14 @@ static void AssignDpyEvoName (NVDpyEvoPtr pDpyEvo);
static NvBool IsConnectorTMDS (NVConnectorEvoPtr);
static void DpyDisconnectEvo(NVDpyEvoPtr pDpyEvo)
static void DpyDisconnectEvo(NVDpyEvoPtr pDpyEvo, const NvBool bSendHdmiCapsToRm)
{
NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo;
pDispEvo->connectedDisplays =
nvDpyIdListMinusDpyId(pDispEvo->connectedDisplays, pDpyEvo->id);
ClearEdid(pDpyEvo);
ClearEdid(pDpyEvo, bSendHdmiCapsToRm);
}
static NvBool DpyConnectEvo(
@@ -351,6 +351,7 @@ static void ApplyNewEdid(
NVDpyEvoPtr pDpyEvo,
const NVEdidRec *pEdid,
const NVParsedEdidEvoRec *pParsedEdid,
const NvBool bSendHdmiCapsToRm,
NVEvoInfoStringPtr pInfoString)
{
if (pDpyEvo->edid.buffer != NULL) {
@@ -392,7 +393,9 @@ static void ApplyNewEdid(
DpyAssignColorSpaceCaps(pDpyEvo, pInfoString);
}
nvUpdateHdmiCaps(pDpyEvo);
if (bSendHdmiCapsToRm) {
nvSendHdmiCapsToRm(pDpyEvo);
}
nvDpyProbeMaxPixelClock(pDpyEvo);
@@ -574,7 +577,8 @@ static void ReadAndApplyEdidEvo(
* worrying that this request has different parameters (like CustomEdid
* or mode validation overrides).
*/
ApplyNewEdid(pDpyEvo, &edid, pParsedEdid, &infoString);
ApplyNewEdid(pDpyEvo, &edid, pParsedEdid, TRUE /* bSendHdmiCapsToRm */,
&infoString);
} else {
nvFree(edid.buffer);
}
@@ -1844,14 +1848,15 @@ static void LogEdid(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString)
* structure.
*/
static void ClearEdid(NVDpyEvoPtr pDpyEvo)
static void ClearEdid(NVDpyEvoPtr pDpyEvo, const NvBool bSendHdmiCapsToRm)
{
NVEdidRec edid = { };
NVEvoInfoStringRec infoString;
nvInitInfoString(&infoString, NULL, 0);
if (EdidHasChanged(pDpyEvo, &edid, NULL)) {
ApplyNewEdid(pDpyEvo, &edid, NULL, &infoString);
ApplyNewEdid(pDpyEvo, &edid, NULL,
bSendHdmiCapsToRm, &infoString);
}
}
@@ -2283,7 +2288,7 @@ NVDpyEvoPtr nvAllocDpyEvo(NVDispEvoPtr pDispEvo,
void nvFreeDpyEvo(NVDispEvoPtr pDispEvo, NVDpyEvoPtr pDpyEvo)
{
DpyDisconnectEvo(pDpyEvo);
DpyDisconnectEvo(pDpyEvo, FALSE /* bSendHdmiCapsToRm */);
// Let the DP library host implementation handle deleting a pDpy as if the
// library had notified it of a lost device.
@@ -2826,7 +2831,7 @@ NvBool nvDpyGetDynamicData(
return FALSE;
}
} else {
DpyDisconnectEvo(pDpyEvo);
DpyDisconnectEvo(pDpyEvo, TRUE /* bSendHdmiCapsToRm */);
}
if (nvConnectorUsesDPLib(pConnectorEvo)) {

6
src/nvidia-modeset/src/nvkms-evo.c
View File

@@ -8602,6 +8602,7 @@ void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo,
pHC->serverLock = NV_EVO_RASTER_LOCK;
pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead);
pHC->setLockOffsetX = TRUE;
pHC->crashLockUnstallMode = FALSE;
} else {
pHC->clientLock = NV_EVO_RASTER_LOCK;
pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead);
@@ -8612,11 +8613,10 @@ void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo,
} else {
pHC->clientLockoutWindow = 2;
}
pHC->crashLockUnstallMode =
(pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE);
}
if (pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE) {
pHC->crashLockUnstallMode = TRUE;
}
pHC->stereoLocked = FALSE;
EvoUpdateHeadParams(pDispEvo, head, pUpdateState);

27
src/nvidia-modeset/src/nvkms-evo3.c
View File

@@ -6639,12 +6639,19 @@ static void EvoSetStallLockC3(NVDispEvoPtr pDispEvo, const int head,
NVEvoChannelPtr pChannel = pDevEvo->core;
NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner];
NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head];
NvU32 data = 0x0;
nvUpdateUpdateState(pDevEvo, updateState, pChannel);
if (pHC->crashLockUnstallMode) {
data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _CRASH_LOCK);
} else {
data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK);
}
if (enable) {
NvU32 data = DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) |
DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT);
data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) |
DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT);
if (!pHC->useStallLockPin) {
data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, _LOCK_PIN_NONE);
@@ -6657,20 +6664,12 @@ static void EvoSetStallLockC3(NVDispEvoPtr pDispEvo, const int head,
data |= DRF_NUM(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN,
NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(pin));
}
if (pHC->crashLockUnstallMode) {
data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _CRASH_LOCK);
} else {
data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK);
}
nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1);
nvDmaSetEvoMethodData(pChannel, data);
} else {
nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1);
nvDmaSetEvoMethodData(pChannel,
DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _FALSE));
data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _FALSE);
}
nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1);
nvDmaSetEvoMethodData(pChannel, data);
}
static NvBool GetChannelState(NVDevEvoPtr pDevEvo,

4
src/nvidia-modeset/src/nvkms-hdmi.c
View File

@@ -203,7 +203,7 @@ NvBool nvDpyIsHdmiEvo(const NVDpyEvoRec *pDpyEvo)
/*!
* Updates the display's HDMI 2.0 capabilities to the RM.
*/
void nvUpdateHdmiCaps(NVDpyEvoPtr pDpyEvo)
void nvSendHdmiCapsToRm(NVDpyEvoPtr pDpyEvo)
{
NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS params = { 0 };
NVParsedEdidEvoPtr pParsedEdid = &pDpyEvo->parsedEdid;
@@ -221,7 +221,7 @@ void nvUpdateHdmiCaps(NVDpyEvoPtr pDpyEvo)
params.caps = 0;
/*
* nvUpdateHdmiCaps() gets called on dpy's connect/disconnect events
* nvSendHdmiCapsToRm() gets called on dpy's connect/disconnect events
* to set/clear capabilities, clear capabilities if parsed edid
* is not valid.
*/

1
src/nvidia/Makefile
View File

@@ -91,6 +91,7 @@ ifeq ($(TARGET_ARCH),aarch64)
CFLAGS += -mgeneral-regs-only
CFLAGS += -march=armv8-a
CFLAGS += -mstrict-align
CFLAGS += -ffixed-x18
CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics)
endif

5
src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -77,6 +77,9 @@
#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) \
((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2)
// First index of doorbell which is controlled by VF
#define NV_CTRL_INTR_GPU_DOORBELL_INDEX_VF_START 2048
// The max number of leaf registers we expect
#define NV_MAX_INTR_LEAVES 16

2
src/nvidia/generated/g_nv_name_released.h
View File

@@ -1042,6 +1042,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x28A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
{ 0x28A1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
{ 0x28B8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Laptop GPU" },
{ 0x28B9, 0x0000, 0x0000, "NVIDIA RTX 1000 Ada Generation Laptop GPU" },
{ 0x28BB, 0x0000, 0x0000, "NVIDIA RTX 500 Ada Generation Laptop GPU" },
{ 0x28E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
{ 0x28E1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
{ 0x28F8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Embedded GPU" },

2
src/nvidia/generated/g_vgpuconfigapi_nvoc.h
View File

@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

20
src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h
View File

@@ -103,4 +103,24 @@ typedef struct MESSAGE_QUEUE_COLLECTION
#define GSP_MSG_QUEUE_HEADER_SIZE RM_PAGE_SIZE
#define GSP_MSG_QUEUE_HEADER_ALIGN 4 // 2 ^ 4 = 16
/*!
* Calculate 32-bit checksum
*
* This routine assumes that the data is padded out with zeros to the next
* 8-byte alignment, and it is OK to read past the end to the 8-byte alignment.
*/
static NV_INLINE NvU32 _checkSum32(void *pData, NvU32 uLen)
{
NvU64 *p = (NvU64 *)pData;
NvU64 *pEnd = (NvU64 *)((NvUPtr)pData + uLen);
NvU64 checkSum = 0;
NV_ASSERT_CHECKED(uLen > 0);
while (p < pEnd)
checkSum ^= *p++;
return NvU64_HI32(checkSum) ^ NvU64_LO32(checkSum);
}
#endif // _MESSAGE_QUEUE_PRIV_H_

40
src/nvidia/src/kernel/gpu/fsp/kern_fsp.c
View File

@@ -244,32 +244,50 @@ kfspPollForQueueEmpty_IMPL
KernelFsp *pKernelFsp
)
{
NV_STATUS status = NV_OK;
RMTIMEOUT timeout;
gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE);
gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout,
GPU_TIMEOUT_FLAGS_OSTIMER |
GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE);
while (!kfspIsQueueEmpty(pGpu, pKernelFsp))
{
//
// For now we assume that any response from FSP before RM message send is complete
// indicates an error and we should abort.
// For now we assume that any response from FSP before RM message
// send is complete indicates an error and we should abort.
//
// Ongoing dicussion on usefullness of this check. Bug to be filed.
//
if (!kfspIsMsgQueueEmpty(pGpu, pKernelFsp))
{
kfspReadMessage(pGpu, pKernelFsp, NULL, 0);
NV_PRINTF(LEVEL_ERROR, "Received error message from FSP while waiting for CMDQ to be empty.\n");
return NV_ERR_GENERIC;
NV_PRINTF(LEVEL_ERROR,
"Received error message from FSP while waiting for CMDQ to be empty.\n");
status = NV_ERR_GENERIC;
break;
}
if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT)
{
NV_PRINTF(LEVEL_ERROR, "Timed out waiting for FSP command queue to be empty.\n");
return NV_ERR_TIMEOUT;
}
osSpinLoop();
status = gpuCheckTimeout(pGpu, &timeout);
if (status != NV_OK)
{
if ((status == NV_ERR_TIMEOUT) &&
kfspIsQueueEmpty(pGpu, pKernelFsp))
{
status = NV_OK;
}
else
{
NV_PRINTF(LEVEL_ERROR,
"Timed out waiting for FSP command queue to be empty.\n");
}
break;
}
}
return NV_OK;
return status;
}
/*!

47
src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c
View File

@@ -476,24 +476,6 @@ void GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection)
*ppMQCollection = NULL;
}
/*!
* Calculate 32-bit checksum
*
* This routine assumes that the data is padded out with zeros to the next
* 8-byte alignment, and it is OK to read past the end to the 8-byte alignment.
*/
static NV_INLINE NvU32 _checkSum32(void *pData, NvU32 uLen)
{
NvU64 *p = (NvU64 *)pData;
NvU64 *pEnd = (NvU64 *)((NvUPtr)pData + uLen);
NvU64 checkSum = 0;
while (p < pEnd)
checkSum ^= *p++;
return NvU64_HI32(checkSum) ^ NvU64_LO32(checkSum);
}
/*!
* GspMsgQueueSendCommand
*
@@ -533,7 +515,7 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
pCQE->seqNum = pMQI->txSeqNum;
pCQE->elemCount = GSP_MSG_QUEUE_BYTES_TO_ELEMENTS(uElementSize);
pCQE->checkSum = 0;
pCQE->checkSum = 0; // The checkSum field is included in the checksum calculation, so zero it.
ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu);
if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED))
@@ -660,7 +642,8 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
NvU32 nRetries;
NvU32 nMaxRetries = 3;
NvU32 nElements = 1; // Assume record fits in one queue element for now.
NvU32 uElementSize = 0;
NvU32 uElementSize;
NvU32 checkSum;
NvU32 seqMismatchDiff = NV_U32_MAX;
NV_STATUS nvStatus = NV_OK;
ConfidentialCompute *pCC = NULL;
@@ -713,15 +696,23 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
pCC = GPU_GET_CONF_COMPUTE(pGpu);
if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY))
{
// In Confidential Compute scenario, checksum includes complete element range.
if (_checkSum32(pMQI->pCmdQueueElement, (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN)) != 0)
{
NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n");
nvStatus = NV_ERR_INVALID_DATA;
continue;
}
//
// In the Confidential Compute scenario, the actual message length
// is inside the encrypted payload, and we can't access it before
// decryption, therefore the checksum encompasses the whole element
// range. This makes checksum verification significantly slower
// because messages are typically much smaller than element size.
//
checkSum = _checkSum32(pMQI->pCmdQueueElement,
(nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN));
} else
if (_checkSum32(pMQI->pCmdQueueElement, uElementSize) != 0)
{
checkSum = _checkSum32(pMQI->pCmdQueueElement,
(GSP_MSG_QUEUE_ELEMENT_HDR_SIZE +
pMQI->pCmdQueueElement->rpc.length));
}
if (checkSum != 0)
{
NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n");
nvStatus = NV_ERR_INVALID_DATA;

2
src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
View File

@@ -1587,6 +1587,7 @@ memdescFree
}
if (pMemDesc->_addressSpace != ADDR_FBMEM &&
pMemDesc->_addressSpace != ADDR_EGM &&
pMemDesc->_addressSpace != ADDR_SYSMEM)
{
return;
@@ -1991,6 +1992,7 @@ memdescUnmap
switch (pMemDesc->_addressSpace)
{
case ADDR_SYSMEM:
case ADDR_EGM:
{
osUnmapSystemMemory(pMemDesc, Kernel, ProcessId, Address, Priv);
break;

5
src/nvidia/src/kernel/rmapi/mapping_cpu.c
View File

@@ -733,8 +733,9 @@ memUnmap_IMPL
//
}
// System Memory case
else if ((pGpu == NULL) || ((memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) &&
FLD_TEST_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, pCpuMapping->flags)))
else if ((pGpu == NULL) || (((memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM)
|| (memdescGetAddressSpace(pMemDesc) == ADDR_EGM)
) && FLD_TEST_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, pCpuMapping->flags)))
{
if (FLD_TEST_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, pCpuMapping->flags))
{