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570.133.07

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This commit is contained in:
Bernhard Stoeckner
2025-03-19 14:13:05 +01:00
parent 25bef4626e
commit c5e439fea4
146 changed files with 53971 additions and 54755 deletions
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8
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -315,6 +315,12 @@ namespace DisplayPort
//
bool bNoFallbackInPostLQA;
//
// Set to true when we do not want DSC to be limited
// to 16 BPP for multitile on Blackwell++
//
bool bDisableDscMaxBppLimit;
bool bReportDeviceLostBeforeNew;
bool bDisableSSC;
bool bEnableFastLT;
@@ -335,6 +341,8 @@ namespace DisplayPort
bool bForceHeadShutdownPerMonitor;
bool bEnableLowerBppCheckForDsc;
//
// Dual SST Partner connector object pointer
ConnectorImpl *pCoupledConnector;

1
src/common/displayport/inc/dp_edid.h
View File

@@ -168,6 +168,7 @@ namespace DisplayPort
bool bIgnoreDscCap; // Ignore DSC even if sink reports DSC capability
bool bDisableDownspread;
bool bForceHeadShutdown;
bool bDisableDscMaxBppLimit;
bool bSkipCableIdCheck;
bool bAllocateManualTimeslots;
}_WARFlags;

6
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -101,7 +101,10 @@
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
//
// Bug 5041041 : Enable Lower BPP check for DSC
#define NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC "DP_ENABLE_LOWER_BPP_CHECK"
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
// All entries set to 0 before initialized by the first EvoMainLink constructor.
@@ -141,6 +144,7 @@ struct DP_REGKEY_DATABASE
bool bSkipZeroOuiCache;
bool bDisable5019537Fix;
bool bForceHeadShutdown;
bool bEnableLowerBppCheckForDsc;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

38
src/common/displayport/src/dp_configcaps2x.cpp
View File

@@ -158,7 +158,8 @@ void DPCDHALImpl2x::parseAndReadCaps()
_ANSI_128B_132B, _YES,
buffer[0]);
if (caps2x.bDP2xChannelCodingSupported == true)
// Read this unconditionally when the connection is tunneled
if (caps2x.bDP2xChannelCodingSupported == true || caps.dpInTunnelingCaps.bIsSupported)
{
// 0x2215
if (AuxRetry::ack == bus.read(NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES, &buffer[0], 1))
@@ -264,7 +265,7 @@ void DPCDHALImpl2x::parseAndReadCaps()
if (caps2x.dpInTunnelingCaps.bDP2xChannelCodingSupported)
{
if (AuxRetry::ack ==
bus.read(NV_DPCD20_DP_TUNNELING_MAIN_LINK_CHANNEL_CODING, &byte, sizeof byte))
bus.read(NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES, &byte, sizeof byte))
{
caps2x.dpInTunnelingCaps.bUHBR_10GSupported =
FLD_TEST_DRF(_DPCD20, _DP_TUNNELING_128B132B_LINK_RATES, _10_0_GPBS_SUPPORTED, _YES, byte);
@@ -342,12 +343,18 @@ AuxRetry::status DPCDHALImpl2x::notifySDPErrDetectionCapability()
bool DPCDHALImpl2x::isDp2xChannelCodingCapable()
{
// return false if the device does not support 128b/132b.
if (!caps2x.bDP2xChannelCodingSupported)
return false;
// return false if DP-IN Tunneling is supported but not support 128b/132b.
if (caps.dpInTunnelingCaps.bIsSupported && !caps2x.dpInTunnelingCaps.bDP2xChannelCodingSupported)
return false;
// However when dpTunneling is enabled, read the tunneling cap instead
if (caps.dpInTunnelingCaps.bIsSupported)
{
// return false if DP-IN Tunneling is supported but not support 128b/132b.
if (!caps2x.dpInTunnelingCaps.bDP2xChannelCodingSupported)
return false;
}
else
{
if (!caps2x.bDP2xChannelCodingSupported)
return false;
}
// return true if there is no LTTPR.
if (!bLttprSupported || (caps.phyRepeaterCount == 0))
@@ -410,6 +417,14 @@ NvU32 DPCDHALImpl2x::getUHBRSupported()
bool bUHBR_13_5GSupported = caps2x.bUHBR_13_5GSupported;
bool bUHBR_20GSupported = caps2x.bUHBR_20GSupported;
// When tunneling is supported and bw allocation is enabled, override the caps from tunneling caps
if (caps.dpInTunnelingCaps.bIsSupported && bIsDpTunnelBwAllocationEnabled)
{
bUHBR_10GSupported = caps2x.dpInTunnelingCaps.bUHBR_10GSupported;
bUHBR_13_5GSupported = caps2x.dpInTunnelingCaps.bUHBR_13_5GSupported;
bUHBR_20GSupported = caps2x.dpInTunnelingCaps.bUHBR_20GSupported;
}
if (!bIgnoreCableIdCaps)
{
bUHBR_10GSupported = bUHBR_10GSupported && caps2x.cableCaps.bUHBR_10GSupported;
@@ -424,13 +439,6 @@ NvU32 DPCDHALImpl2x::getUHBRSupported()
bUHBR_20GSupported = bUHBR_20GSupported && caps2x.repeaterCaps.bUHBR_20GSupported;
}
if (caps.dpInTunnelingCaps.bIsSupported && bIsDpTunnelBwAllocationEnabled)
{
bUHBR_10GSupported = bUHBR_10GSupported && caps2x.dpInTunnelingCaps.bUHBR_10GSupported;
bUHBR_13_5GSupported = bUHBR_13_5GSupported && caps2x.dpInTunnelingCaps.bUHBR_13_5GSupported;
bUHBR_20GSupported = bUHBR_20GSupported && caps2x.dpInTunnelingCaps.bUHBR_20GSupported;
}
if (bUHBR_10GSupported)
{
uhbrCaps = FLD_SET_DRF(0073_CTRL_CMD_DP, _GET_CAPS_UHBR_SUPPORTED, _UHBR10_0, _YES, uhbrCaps);

100
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -185,6 +185,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bDisable5019537Fix = dpRegkeyDatabase.bDisable5019537Fix;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableLowerBppCheckForDsc = dpRegkeyDatabase.bEnableLowerBppCheckForDsc;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -1367,12 +1368,38 @@ bool ConnectorImpl::compoundQueryAttachMST(Group * target,
if (compoundQueryAttachMSTIsDscPossible(target, modesetParams, pDscParams))
{
unsigned int forceDscBitsPerPixelX16 = pDscParams->bitsPerPixelX16;
result = compoundQueryAttachMSTDsc(target, modesetParams, &localInfo,
pDscParams, pErrorCode);
if (!result)
{
return false;
}
compoundQueryResult = compoundQueryAttachMSTGeneric(target, modesetParams, &localInfo,
pDscParams, pErrorCode);
//
// compoundQueryAttachMST Generic might fail due to the insufficient bandwidth ,
// We only check whether bpp can be fit in the available bandwidth based on the tranied link config in compoundQueryAttachMSTDsc function.
// There might be cases where the default 10 bpp might fit in the available bandwidth based on the trained link config,
// however, the bandwidth might be insufficient at the actual bottleneck link between source and sink to drive the mode, causing CompoundQueryAttachMSTGeneric to fail.
// Incase of CompoundQueryAttachMSTGeneric failure, instead of returning false, check whether the mode can be supported with the max dsc compression bpp
// and return true if it can be supported.
if (!compoundQueryResult && forceDscBitsPerPixelX16 == 0U && this->bEnableLowerBppCheckForDsc)
{
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
result = compoundQueryAttachMSTDsc(target, modesetParams, &localInfo,
pDscParams, pErrorCode);
if (!result)
{
return false;
}
return compoundQueryAttachMSTGeneric(target, modesetParams, &localInfo,
pDscParams, pErrorCode);
}
return compoundQueryResult;
}
return compoundQueryAttachMSTGeneric(target, modesetParams, &localInfo,
@@ -1564,6 +1591,7 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
warData.dpData.dpMode = DSC_DP_MST;
warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth;
warData.connectorType = DSC_DP;
warData.dpData.bDisableDscMaxBppLimit = bDisableDscMaxBppLimit;
//
// Dplib needs to pass sliceCountMask to clients
@@ -1636,7 +1664,9 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
localInfo->localModesetInfo.bEnableDsc = true;
localInfo->localModesetInfo.depth = bitsPerPixelX16;
if (modesetParams.colorFormat == dpColorFormat_YCbCr422 &&
dev->dscCaps.dscDecoderColorFormatCaps.bYCbCrNative422)
dev->dscCaps.dscDecoderColorFormatCaps.bYCbCrNative422 &&
(dscInfo.gpuCaps.encoderColorFormatMask & DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422) &&
(dscInfo.sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422))
{
localInfo->localModesetInfo.colorFormat = dpColorFormat_YCbCr422_Native;
}
@@ -1790,12 +1820,24 @@ bool ConnectorImpl::compoundQueryAttachMSTGeneric(Group * target,
if ( tail->bandwidth.compound_query_state.timeslots_used_by_query > tail->bandwidth.compound_query_state.totalTimeSlots)
{
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH)
if(this->bEnableLowerBppCheckForDsc)
{
tail->bandwidth.compound_query_state.timeslots_used_by_query -= linkConfig->slotsForPBN(base_pbn);
tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex &= ~(1 << compoundQueryCount);
}
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH);
}
}
tail = (DeviceImpl*)tail->getParent();
}
}
// If the compoundQueryResult is false, we need to reset the compoundQueryLocalLinkPBN
if (!compoundQueryResult && this->bEnableLowerBppCheckForDsc)
{
compoundQueryLocalLinkPBN -= slots_pbn;
}
return compoundQueryResult;
}
bool ConnectorImpl::compoundQueryAttachSST(Group * target,
@@ -1938,6 +1980,8 @@ bool ConnectorImpl::compoundQueryAttachSST(Group * target,
warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth;
warData.dpData.dpMode = DSC_DP_SST;
warData.connectorType = DSC_DP;
warData.dpData.bDisableDscMaxBppLimit = bDisableDscMaxBppLimit;
if (main->isEDP())
{
warData.dpData.bIsEdp = true;
@@ -6067,7 +6111,6 @@ void ConnectorImpl::flushTimeslotsToHardware()
void ConnectorImpl::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
{
//
// During flush entry, if the link is not trained, retrain
// the link so that ACT can be ack'd by the sink.
@@ -6079,11 +6122,18 @@ void ConnectorImpl::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
// head is not actively driving pixels and this needs to be handled
// differently .
//
if(forFlushMode && linkUseMultistream())
if (forFlushMode && linkUseMultistream())
{
if(isLinkLost())
{
train(activeLinkConfig, false);
if(!this->bDisable5019537Fix)
{
train(highestAssessedLC, false);
}
else
{
train(activeLinkConfig, false);
}
}
}
@@ -7307,8 +7357,11 @@ void ConnectorImpl::notifyShortPulse()
{
return;
}
//save the previous highest assessed LC
// Save the previous highest assessed LC
LinkConfiguration previousAssessedLC = highestAssessedLC;
// Save original active link configuration.
LinkConfiguration originalActiveLinkConfig = activeLinkConfig;
if (main->isConnectorUSBTypeC() &&
activeLinkConfig.bIs128b132bChannelCoding &&
@@ -7316,11 +7369,27 @@ void ConnectorImpl::notifyShortPulse()
{
if (activeLinkConfig.isValid() && enableFlush())
{
train(activeLinkConfig, true);
if (!this->bDisable5019537Fix)
{
train(originalActiveLinkConfig, true);
}
else
{
train(activeLinkConfig, true);
}
disableFlush();
}
main->invalidateLinkRatesInFallbackTable(activeLinkConfig.peakRate);
hal->overrideCableIdCap(activeLinkConfig.peakRate, false);
if (!this->bDisable5019537Fix)
{
main->invalidateLinkRatesInFallbackTable(originalActiveLinkConfig.peakRate);
hal->overrideCableIdCap(originalActiveLinkConfig.peakRate, false);
}
else
{
main->invalidateLinkRatesInFallbackTable(activeLinkConfig.peakRate);
hal->overrideCableIdCap(activeLinkConfig.peakRate, false);
}
highestAssessedLC = getMaxLinkConfig();
@@ -7334,8 +7403,16 @@ void ConnectorImpl::notifyShortPulse()
if (activeLinkConfig.isValid() && enableFlush())
{
LinkConfiguration originalActiveLinkConfig = activeLinkConfig;
if (!train(activeLinkConfig, false))
bool bTrainSuccess = false;
if (!this->bDisable5019537Fix)
{
bTrainSuccess = train(originalActiveLinkConfig, false);
}
else
{
bTrainSuccess = train(activeLinkConfig, false);
}
if (!bTrainSuccess)
{
//
// If original link config could not be restored force
@@ -8210,6 +8287,7 @@ void ConnectorImpl::configInit()
allocatedDpTunnelBwShadow = 0;
bDP2XPreferNonDSCForLowPClk = false;
bForceHeadShutdownPerMonitor = false;
bDisableDscMaxBppLimit = false;
}
bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp)

5
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -1713,5 +1713,10 @@ void ConnectorImpl2x::handleEdidWARs(Edid & edid, DiscoveryManager::Device & dev
bForceHeadShutdownPerMonitor = true;
}
}
if (edid.WARFlags.bDisableDscMaxBppLimit)
{
bDisableDscMaxBppLimit = true;
}
}

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -104,7 +104,8 @@ const struct
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_FIX_FOR_5019537, &dpRegkeyDatabase.bDisable5019537Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC, &dpRegkeyDatabase.bEnableLowerBppCheckForDsc, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

5
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -596,6 +596,11 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel incorrectly exposing DSC capability. Ignoring it.");
DP_PRINTF(DP_NOTICE, "DP-WAR> Bug 3543158");
}
else if (ProductID == 0x5B9A)
{
this->WARFlags.bDisableDscMaxBppLimit = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Disable DSC max BPP limit of 16 for DSC.");
}
break;
case 0xB306:
if (ProductID == 0x3228)

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r572_46
#define NV_BUILD_BRANCH r572_77
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r572_46
#define NV_PUBLIC_BRANCH r572_77
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r572_46-344"
#define NV_BUILD_CHANGELIST_NUM (35599303)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r572_77-376"
#define NV_BUILD_CHANGELIST_NUM (35688848)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/r572_46-344"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35599303)
#define NV_BUILD_NAME "rel/gpu_drv/r570/r572_77-376"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35688848)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r572_46-7"
#define NV_BUILD_CHANGELIST_NUM (35597621)
#define NV_BUILD_BRANCH_VERSION "r572_77-2"
#define NV_BUILD_CHANGELIST_NUM (35681611)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "572.61"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35597621)
#define NV_BUILD_NAME "572.80"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35681611)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.124.06"
#define NV_VERSION_STRING "570.133.07"
#else

12
src/common/modeset/timing/nvt_dsc_pps.c
View File

@@ -2347,6 +2347,7 @@ DSC_GeneratePPS
in->bits_per_component = pModesetInfo->bitsPerComponent;
in->linebuf_depth = MIN((pDscInfo->sinkCaps.lineBufferBitDepth), (pDscInfo->gpuCaps.lineBufferBitDepth));
in->block_pred_enable = pDscInfo->sinkCaps.bBlockPrediction;
in->multi_tile = (pDscInfo->gpuCaps.maxNumHztSlices > 4U) ? 1 : 0;
switch (pModesetInfo->colorFormat)
{
@@ -2526,8 +2527,9 @@ DSC_GeneratePPS
// because of architectural limitation we can't use bits_per_pixel
// more than 16.
//
if ((pModesetInfo->bDualMode || (pDscInfo->gpuCaps.maxNumHztSlices > 4U)) &&
(in->bits_per_pixel > 256 /*bits_per_pixel = 16*/))
if ((pModesetInfo->bDualMode ||
(in->multi_tile && (!pWARData || (pWARData && !pWARData->dpData.bDisableDscMaxBppLimit))))
&& (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/))
{
ret = NVT_STATUS_INVALID_BPP;
goto done;
@@ -2547,8 +2549,9 @@ DSC_GeneratePPS
// because of architectural limitation we can't use bits_per_pixel more
// than 16. So forcing it to 16.
//
if ((pModesetInfo->bDualMode || (pDscInfo->gpuCaps.maxNumHztSlices > 4U)) &&
(in->bits_per_pixel > 256 /*bits_per_pixel = 16*/))
if ((pModesetInfo->bDualMode ||
(in->multi_tile && (!pWARData || (pWARData && !pWARData->dpData.bDisableDscMaxBppLimit))))
&& (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/))
{
// ERROR - DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16.
// ERROR - Forcing it to 16.
@@ -2590,7 +2593,6 @@ DSC_GeneratePPS
in->pixel_clkMHz = (NvU32)(pModesetInfo->pixelClockHz / 1000000L);
in->dual_mode = pModesetInfo->bDualMode;
in->drop_mode = pModesetInfo->bDropMode;
in->multi_tile = (pDscInfo->gpuCaps.maxNumHztSlices > 4U) ? 1 : 0;
in->slice_count_mask = pDscInfo->sinkCaps.sliceCountSupportedMask;
in->peak_throughput_mode0 = pDscInfo->sinkCaps.peakThroughputMode0;
in->peak_throughput_mode1 = pDscInfo->sinkCaps.peakThroughputMode1;

1
src/common/modeset/timing/nvt_dsc_pps.h
View File

@@ -254,6 +254,7 @@ typedef struct
DSC_DP_MODE dpMode;
NvU32 hBlank;
NvBool bIsEdp;
NvBool bDisableDscMaxBppLimit;
NvBool bIs128b132bChannelCoding;
}dpData;
} WAR_DATA;

6
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -8230,6 +8230,12 @@ nvswitch_initialize_interrupt_tree_ls10
// NVLIPT
_nvswitch_initialize_nvlipt_interrupts_ls10(device);
// Disable non-fatal and legacy interrupts in TNVL mode
if (nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_tnvl_disable_interrupts(device);
}
}
//

8
src/common/nvswitch/kernel/ls10/tnvl_ls10.c
View File

@@ -1250,6 +1250,14 @@ nvswitch_tnvl_disable_interrupts_ls10
nvswitch_device *device
)
{
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"Failed to disable non-fatal/legacy interrupts. TNVL mode is not enabled\n");
return;
}
//
// In TNVL locked disable non-fatal NVLW, NPG, and legacy interrupt,
// disable additional non-fatals on those partitions.

16
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -3437,6 +3437,18 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
NvU32 maxCeSecureChannels;
} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK
*
* This command checks if all the dependant modules to PRH have been initialized.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK (0x20800a18) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x18" */
/*
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
*
@@ -3454,7 +3466,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)

7
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -149,8 +149,11 @@
#define RESERVED8_ERROR (153)
#define GPU_RECOVERY_ACTION_CHANGED (154)
#define NVLINK_SW_DEFINED_ERROR (155)
#define ROBUST_CHANNEL_LAST_ERROR (157)
#define RESOURCE_RETIREMENT_EVENT (156)
#define RESOURCE_RETIREMENT_FAILURE (157)
#define CHANNEL_RETIREMENT_EVENT (160)
#define CHANNEL_RETIREMENT_FAILURE (161)
#define ROBUST_CHANNEL_LAST_ERROR (161)
// Indexed CE reference
#define ROBUST_CHANNEL_CE_ERROR(x) \

1
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -159,6 +159,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_NOT_READY, 0x00000081, "Nvlink Fabri
NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_FAILURE, 0x00000082, "Nvlink Fabric Probe failed")
NV_STATUS_CODE(NV_ERR_GPU_MEMORY_ONLINING_FAILURE, 0x00000083, "GPU Memory Onlining failed")
NV_STATUS_CODE(NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE, 0x00000084, "Reduction Manager is not available")
NV_STATUS_CODE(NV_ERR_RESOURCE_RETIREMENT_ERROR, 0x00000086, "An error occurred while trying to retire a resource")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

19
src/common/shared/inc/g_vgpu_chip_flags.h
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@@ -615,6 +615,25 @@ ENTRY(0x2238, 0x16B7, 0x10de, "NVIDIA A10M-5C"),
ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),

8
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -17,6 +17,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B7, 0x1804, 0x20B7, 0x1532 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x230E, 0x20DF, 0x230E, 0x20DF },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -119,6 +120,13 @@ static const struct {
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1461}, // NVIDIA H20L-1-15CME
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1462}, // NVIDIA H20L-1-15C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1463}, // NVIDIA H20L-1-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1464}, // NVIDIA H20L-2-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1465}, // NVIDIA H20L-3-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1466}, // NVIDIA H20L-4-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1467}, // NVIDIA H20L-7-120C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C