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This commit is contained in:
Bernhard Stoeckner
2025-03-19 14:13:05 +01:00
parent 25bef4626e
commit c5e439fea4
146 changed files with 53971 additions and 54755 deletions
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3
src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,7 @@
// management partition and CPU-RM/other uprocs.
//
#define NVDM_TYPE_RESET 0x4
#define NVDM_TYPE_HULK 0x11
#define NVDM_TYPE_FIRMWARE_UPDATE 0x12
#define NVDM_TYPE_PRC 0x13

27
src/nvidia/arch/nvalloc/common/inc/nvpcie.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2000-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2000-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -211,21 +211,18 @@
// to any specific hardware.
//
//
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING 23:23
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DEFAULT 0x00000000
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DISABLE 0x00000001
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:24
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:23
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
// Chipset-specific definitions.
// Intel SantaRosa definitions

9
src/nvidia/arch/nvalloc/unix/include/nv.h
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@@ -498,6 +498,9 @@ typedef struct nv_state_t
NvU32 dispIsoStreamId;
NvU32 dispNisoStreamId;
} iommus;
/* Console is managed by drm drivers or NVKMS */
NvBool client_managed_console;
} nv_state_t;
#define NVFP_TYPE_NONE 0x0
@@ -542,9 +545,9 @@ typedef struct UvmGpuNvlinkInfo_tag *nvgpuNvlinkInfo_t;
typedef struct UvmGpuEccInfo_tag *nvgpuEccInfo_t;
typedef struct UvmGpuFaultInfo_tag *nvgpuFaultInfo_t;
typedef struct UvmGpuAccessCntrInfo_tag *nvgpuAccessCntrInfo_t;
typedef struct UvmGpuAccessCntrConfig_tag *nvgpuAccessCntrConfig_t;
typedef struct UvmGpuInfo_tag nvgpuInfo_t;
typedef struct UvmGpuClientInfo_tag nvgpuClientInfo_t;
typedef struct UvmGpuAccessCntrConfig_tag nvgpuAccessCntrConfig_t;
typedef struct UvmGpuInfo_tag nvgpuInfo_t;
typedef struct UvmGpuClientInfo_tag nvgpuClientInfo_t;
typedef struct UvmPmaAllocationOptions_tag *nvgpuPmaAllocationOptions_t;
typedef struct UvmPmaStatistics_tag *nvgpuPmaStatistics_t;
typedef struct UvmGpuMemoryInfo_tag *nvgpuMemoryInfo_t;

2
src/nvidia/arch/nvalloc/unix/src/dynamic-power.c
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@@ -2398,7 +2398,7 @@ NV_STATUS NV_API_CALL rm_power_management(
// For GPU driving console, disable console access here, to ensure no console
// writes through BAR1 can interfere with physical RM's setup of BAR1
//
if (rm_get_uefi_console_status(pNv))
if (pNv->client_managed_console)
{
os_disable_console_access();
bConsoleDisabled = NV_TRUE;

18
src/nvidia/arch/nvalloc/unix/src/os.c
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@@ -5555,3 +5555,21 @@ void osAllocatedRmClient(void *pOsInfo)
if (nvfp != NULL)
nvfp->bCleanupRmapi = NV_TRUE;
}
/*!
* @brief Update variable to indicate console managed by drm driver.
*
* @param[in] OBJGPU GPU object pointer
*
* @returns void
*/
void
osDisableConsoleManagement
(
OBJGPU *pGpu
)
{
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
nv->client_managed_console = NV_TRUE;
}

11
src/nvidia/arch/nvalloc/unix/src/osinit.c
View File

@@ -913,7 +913,6 @@ static void
RmDeterminePrimaryDevice(OBJGPU *pGpu)
{
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
NvBool bFrameBufferConsoleDevice = NV_FALSE;
// Skip updating nv->primary_vga while RM is recovering after GPU reset
if (nv->flags & NV_FLAG_IN_RECOVERY)
@@ -946,15 +945,15 @@ RmDeterminePrimaryDevice(OBJGPU *pGpu)
//
// If GPU is driving any frame buffer console(vesafb, efifb etc)
// mark the GPU as Primary.
// mark the console as client driven and GPU as Primary.
//
bFrameBufferConsoleDevice = rm_get_uefi_console_status(nv);
nv->client_managed_console = rm_get_uefi_console_status(nv);
NV_DEV_PRINTF(NV_DBG_SETUP, nv, " is %s UEFI console device\n",
bFrameBufferConsoleDevice ? "primary" : "not primary");
nv->client_managed_console ? "primary" : "not primary");
pGpu->setProperty(pGpu, PDB_PROP_GPU_PRIMARY_DEVICE,
(bFrameBufferConsoleDevice || !!nv->primary_vga));
(nv->client_managed_console || !!nv->primary_vga));
}
static void
@@ -1839,7 +1838,7 @@ NvBool RmInitAdapter(
// For GPU driving console, disable console access here, to ensure no console
// writes through BAR1 can interfere with physical RM's setup of BAR1
//
if (rm_get_uefi_console_status(nv))
if (nv->client_managed_console)
{
os_disable_console_access();
consoleDisabled = NV_TRUE;

16
src/nvidia/arch/nvalloc/unix/src/unix_console.c
View File

@@ -87,7 +87,7 @@ RmSaveDisplayState
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS preUnixConsoleParams = {0};
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS postUnixConsoleParams = {0};
if (IS_VIRTUAL(pGpu) || pKernelDisplay == NULL)
if (IS_VIRTUAL(pGpu) || (pKernelDisplay == NULL) || nv->client_managed_console)
{
return;
}
@@ -157,20 +157,12 @@ static void RmRestoreDisplayState
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS preUnixConsoleParams = {0};
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS postUnixConsoleParams = {0};
NV_ASSERT_OR_RETURN_VOID(pKernelDisplay != NULL);
//
// vGPU:
// Since vGPU does all real hardware management in the host,
// there is nothing to do at this point in the guest OS.
//
// Since vGPU does all real hardware management in the
// host, there is nothing to do at this point in the
// guest OS (where IS_VIRTUAL(pGpu) is true).
//
if (IS_VIRTUAL(pGpu))
if (IS_VIRTUAL(pGpu) || (pKernelDisplay == NULL) || nv->client_managed_console)
{
// we don't have VGA state that's needing to be restored.
NV_PRINTF(LEVEL_INFO, "skipping RestoreDisplayState on VGPU (0x%x)\n",
pGpu->gpuId);
return;
}