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This commit is contained in:
Bernhard Stoeckner
2025-03-19 14:13:05 +01:00
parent 25bef4626e
commit c5e439fea4
146 changed files with 53971 additions and 54755 deletions
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2
src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h
View File

@@ -217,7 +217,7 @@ NV_STATUS nvGpuOpsOwnAccessCntrIntr(struct gpuSession *session,
NV_STATUS nvGpuOpsEnableAccessCntr(struct gpuDevice *device,
gpuAccessCntrInfo *pAccessCntrInfo,
gpuAccessCntrConfig *pAccessCntrConfig);
const gpuAccessCntrConfig *pAccessCntrConfig);
NV_STATUS nvGpuOpsDisableAccessCntr(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo);

92
src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -2638,6 +2638,42 @@ return_t deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(NVC637_CTRL_E
return SUCCESS_T;
}
return_t deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT_v29_0C(NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS_v29_0C *src = (void *) buffer;
NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *dest = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->id = src->id;
dest->bCreateCap = src->bCreateCap;
#endif
#ifdef COPY_OUTPUT_PARAMETERS
for (int i = 0; i < NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE; i++) {
dest->info.enginesMask[i] = src->info.enginesMask[i];
}
dest->info.sharedEngFlags = src->info.sharedEngFlags;
dest->info.gpcMask = src->info.gpcMask;
dest->info.gfxGpcCount = src->info.gfxGpcCount;
dest->info.veidOffset = src->info.veidOffset;
dest->info.veidCount = src->info.veidCount;
dest->info.smCount = src->info.smCount;
dest->info.spanStart = src->info.spanStart;
dest->info.computeSize = src->info.computeSize;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
return_t deserialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
@@ -3527,7 +3563,7 @@ return_t serialize_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(N
#ifndef UMED_BUILD
static
return_t serialize_GET_BRAND_CAPS_v25_12(NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *pParams,
NvU8 *buffer,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
@@ -5487,6 +5523,44 @@ return_t serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(NVC637_CTRL_EXE
return SUCCESS_T;
}
return_t serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT_v29_0C(NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS_v29_0C *dest = (void *) buffer;
NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *src = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->id = src->id;
dest->bCreateCap = src->bCreateCap;
#endif
#ifdef COPY_OUTPUT_PARAMETERS
for (int i = 0; i < NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE; i++) {
dest->info.enginesMask[i] = src->info.enginesMask[i];
}
dest->info.sharedEngFlags = src->info.sharedEngFlags;
dest->info.gpcMask = src->info.gpcMask;
dest->info.gfxGpcCount = src->info.gfxGpcCount;
dest->info.veidOffset = src->info.veidOffset;
dest->info.veidCount = src->info.veidCount;
dest->info.smCount = src->info.smCount;
dest->info.spanStart = src->info.spanStart;
dest->info.computeSize = src->info.computeSize;
// UUID will not be copied as Guest will choose uuid by itself.
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
return_t serialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
@@ -6983,37 +7057,37 @@ NvU32 serialize_notifier(NvU32 inNotifier)
if (vgx_internal_version_curr.major_number > 0x21) {
return inNotifier;
}
if (vgx_internal_version_curr.major_number == 0x21 &&
(REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R525)) {
return NV2080_NOTIFIERS_MAXCOUNT_R525;
}
if (vgx_internal_version_curr.major_number == 0x1C &&
(REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R470)) {
return NV2080_NOTIFIERS_MAXCOUNT_R470;
}
return inNotifier;
}
// Convert a guest notifier index to a host notifier index.
NvU32 deserialize_notifier(NvU32 inNotifier)
{
if (vgx_internal_version_curr.major_number > 0x21) {
return inNotifier;
}
if (vgx_internal_version_curr.major_number == 0x21 &&
(REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R525)) {
return NV2080_NOTIFIERS_MAXCOUNT;
}
if (vgx_internal_version_curr.major_number == 0x1C &&
(REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R470)) {
return NV2080_NOTIFIERS_MAXCOUNT;
}
return inNotifier;
}

3
src/nvidia/inc/kernel/vgpu/rpc_global_enums.h
View File

@@ -233,7 +233,8 @@ enum {
X(RM, RESERVED, 223)
X(RM, CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL, 224)
X(RM, CTRL_CMD_GET_HS_CREDITS_MAPPING, 225)
X(RM, NUM_FUNCTIONS, 226)
X(RM, CTRL_EXEC_PARTITIONS_EXPORT, 226)
X(RM, NUM_FUNCTIONS, 227)
#ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
};
# undef X

8
src/nvidia/inc/kernel/vgpu/vgpu_version.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,7 +31,7 @@
#define RPC_VERSION_FROM_VGX_VERSION(major, minor) (DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \
DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor))
#define VGX_MAJOR_VERSION_NUMBER 0x29
#define VGX_MINOR_VERSION_NUMBER 0x0B
#define VGX_MINOR_VERSION_NUMBER 0x0C
#define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A
#define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18
@@ -40,6 +40,7 @@
#define VGX_MAJOR_VERSION_NUMBER_VGPU_16_0 0x23
#define VGX_MAJOR_VERSION_NUMBER_VGPU_17_0 0x25
#define VGX_MAJOR_VERSION_NUMBER_VGPU_18_0 0x29
#define VGX_MINOR_VERSION_NUMBER_VGPU_18_0 0x0B
#define VGX_MAJOR_VERSION_WITH_FB_COPY_LARGE_BLOCKSZ_SUPPORT 0x28
@@ -55,6 +56,7 @@
*/
#define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \
{{0x29, 0x00}, {0x29, 0x0B}, {0x18, 0x01}}, \
{{0x29, 0x0C}, {0x29, 0x0C}, {0x18, 0x02}}, \
{{0x28, 0x00}, {0x28, 0x09}, {0x17, 0x01}}, \
{{0x27, 0x00}, {0x27, 0x06}, {0x16, 0x01}}, \
{{0x26, 0x00}, {0x26, 0x05}, {0x15, 0x01}}, \
@@ -107,7 +109,7 @@
/* WARNING: Should be updated with each vGPU release, if there is a break in
* migration compatibility during the development of that release. */
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x18
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x2
/* WARNING: Should be updated with each vGPU release, if minimum supported
* version change on the host.