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This commit is contained in:
Bernhard Stoeckner
2024-10-22 17:38:58 +02:00
parent ed4be64962
commit d5a0858f90
1049 changed files with 209491 additions and 167508 deletions
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14
src/common/nvswitch/kernel/cci/cci_nvswitch.c
View File

@@ -325,9 +325,17 @@ cciInit
NvU32 pci_device_id
)
{
nvswitch_task_create(device, _nvswitch_cci_poll_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS / NVSWITCH_CCI_POLLING_RATE_HZ,
0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, _nvswitch_cci_poll_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS / NVSWITCH_CCI_POLLING_RATE_HZ,
0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping CCI background task when TNVL is enabled\n");
}
return NVL_SUCCESS;
}

34
src/common/nvswitch/kernel/fsprpc_nvswitch.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -87,7 +87,7 @@ _nvswitch_fsp_poll_for_queue_empty
do
{
bKeepPolling = nvswitch_timeout_check(&timeout) ? NV_FALSE : NV_TRUE;
bKeepPolling = nvswitch_timeout_check(&timeout) ? NV_FALSE : NV_TRUE;
bMsgqEmpty = _nvswitch_fsp_is_msgq_empty(device);
bCmdqEmpty = _nvswitch_fsp_is_queue_empty(device);
@@ -98,7 +98,7 @@ _nvswitch_fsp_poll_for_queue_empty
//
if (!bCmdqEmpty && !bMsgqEmpty)
{
nvswitch_fsp_read_message(device, NULL, 0);
nvswitch_fsp_read_message(device, NULL, 0, &timeout);
NVSWITCH_PRINT(device, ERROR, "Received error message from FSP while waiting for CMDQ to be empty.\n");
return -NVL_ERR_GENERIC;
}
@@ -125,23 +125,22 @@ _nvswitch_fsp_poll_for_queue_empty
* @brief Poll for response from FSP via RM message queue
*
* @param[in] device nvswitch_device pointer
* @param[in] pTimeout RPC timeout
*
* @return NVL_SUCCESS, or NV_ERR_TIMEOUT
*/
static NvlStatus
_nvswitch_fsp_poll_for_response
(
nvswitch_device *device
nvswitch_device *device,
NVSWITCH_TIMEOUT *pTimeout
)
{
NvBool bKeepPolling;
NVSWITCH_TIMEOUT timeout;
nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout);
do
{
bKeepPolling = nvswitch_timeout_check(&timeout) ? NV_FALSE : NV_TRUE;
bKeepPolling = nvswitch_timeout_check(pTimeout) ? NV_FALSE : NV_TRUE;
//
// Poll for message queue to wait for FSP's reply
@@ -178,6 +177,8 @@ _nvswitch_fsp_poll_for_response
* @param[in] device nvswitch_device pointer
* @param[in/out] pPayloadBuffer Buffer in which to return message payload
* @param[in] payloadBufferSize Payload buffer size
* @param[in] pTimeout RPC timeout
*
*
* @return NVL_SUCCESS, NV_ERR_INVALID_DATA, NV_ERR_INSUFFICIENT_RESOURCES, or errors
* from functions called within
@@ -187,7 +188,8 @@ nvswitch_fsp_read_message
(
nvswitch_device *device,
NvU8 *pPayloadBuffer,
NvU32 payloadBufferSize
NvU32 payloadBufferSize,
NVSWITCH_TIMEOUT *pTimeout
)
{
NvU8 *pPacketBuffer;
@@ -206,7 +208,7 @@ nvswitch_fsp_read_message
if (pPacketBuffer == NULL)
{
NVSWITCH_PRINT(device, ERROR,
"Failed to allocate memory for GLT!!\n");
"%s: Failed to allocate memory!!\n", __FUNCTION__);
return -NVL_NO_MEM;
}
@@ -219,9 +221,10 @@ nvswitch_fsp_read_message
NvU8 tag;
// Wait for next packet
status = _nvswitch_fsp_poll_for_response(device);
status = _nvswitch_fsp_poll_for_response(device, pTimeout);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Timed out waiting for response from FSP!\n", __FUNCTION__);
goto done;
}
@@ -353,6 +356,7 @@ nvswitch_fsp_send_packet
* @param[in] nvdmType NVDM type of message being sent
* @param[in] pResponsePayload Buffer in which to return response payload
* @param[in] responseBufferSize Response payload buffer size
* @param[in] pTimeout RPC timeout
*
* @return NVL_SUCCESS, or NV_ERR_*
*/
@@ -364,7 +368,8 @@ nvswitch_fsp_send_and_read_message
NvU32 size,
NvU32 nvdmType,
NvU8 *pResponsePayload,
NvU32 responseBufferSize
NvU32 responseBufferSize,
NVSWITCH_TIMEOUT *pTimeout
)
{
NvU32 dataSent, dataRemaining;
@@ -443,12 +448,13 @@ nvswitch_fsp_send_and_read_message
}
}
status = _nvswitch_fsp_poll_for_response(device);
status = _nvswitch_fsp_poll_for_response(device, pTimeout);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Timed out waiting for response from FSP!\n", __FUNCTION__);
goto failed;
}
status = nvswitch_fsp_read_message(device, pResponsePayload, responseBufferSize);
status = nvswitch_fsp_read_message(device, pResponsePayload, responseBufferSize, pTimeout);
failed:
nvswitch_os_free(pBuffer);

6
src/common/nvswitch/kernel/inc/fsprpc_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -91,8 +91,8 @@ typedef enum mctp_packet_state
MCTP_PACKET_STATE_SINGLE_PACKET
} MCTP_PACKET_STATE, *PMCTP_PACKET_STATE;
NvlStatus nvswitch_fsp_read_message(nvswitch_device *device, NvU8 *pPayloadBuffer, NvU32 payloadBufferSize);
NvlStatus nvswitch_fsp_read_message(nvswitch_device *device, NvU8 *pPayloadBuffer, NvU32 payloadBufferSize, struct NVSWITCH_TIMEOUT *pTimeout);
NvlStatus nvswitch_fsp_send_packet(nvswitch_device *device, NvU8 *pPacket, NvU32 packetSize);
NvlStatus nvswitch_fsp_send_and_read_message(nvswitch_device *device, NvU8 *pPayload, NvU32 size, NvU32 nvdmType, NvU8 *pResponsePayload, NvU32 responseBufferSize);
NvlStatus nvswitch_fsp_send_and_read_message(nvswitch_device *device, NvU8 *pPayload, NvU32 size, NvU32 nvdmType, NvU8 *pResponsePayload, NvU32 responseBufferSize, struct NVSWITCH_TIMEOUT *pTimeout);
#endif //_FSPRPC_NVSWITCH_H_

2
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -296,6 +296,8 @@
_op(NvlStatus, nvswitch_tnvl_get_attestation_report, (nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_tnvl_send_fsp_lock_config, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_tnvl_get_status, (nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_send_tnvl_prelock_cmd, (nvswitch_device *device), _arch) \
_op(void, nvswitch_tnvl_disable_interrupts, (nvswitch_device *device), _arch) \
NVSWITCH_HAL_FUNCTION_LIST_FEATURE_0(_op, _arch) \
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \

1
src/common/nvswitch/kernel/inc/lr10/lr10.h
View File

@@ -710,4 +710,5 @@ NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_lr10(nvswitch_device *device,
NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params);
NvlStatus nvswitch_tnvl_get_attestation_report_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_get_status_lr10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
void nvswitch_tnvl_disable_interrupts_lr10(nvswitch_device *device);
#endif //_LR10_H_

9
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -29,9 +29,9 @@
#include "export_nvswitch.h"
#include "common_nvswitch.h"
#include "nvswitch/ls10/dev_boot.h"
#include "ctrl_dev_nvswitch.h"
#include "nvswitch/ls10/dev_master.h"
#define NVSWITCH_NUM_LINKS_LS10 64
#define NVSWITCH_NUM_LANES_LS10 2
@@ -189,6 +189,8 @@
#define SOE_VBIOS_VERSION_MASK 0xFF0000
#define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000
#define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x4C0000
#define SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE 0x580000
#define SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND 0x600000
// LS10 Saved LED state
#define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED
@@ -1053,6 +1055,9 @@ NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_ls10(nvswitch_device *
NvlStatus nvswitch_tnvl_get_attestation_report_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_send_fsp_lock_config_ls10(nvswitch_device *device);
NvlStatus nvswitch_tnvl_get_status_ls10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
void nvswitch_tnvl_reg_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
NvlStatus nvswitch_send_tnvl_prelock_cmd_ls10(nvswitch_device *device);
void nvswitch_tnvl_disable_interrupts_ls10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p);
NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable);

3
src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -51,4 +51,5 @@ NvlStatus nvswitch_soe_set_nport_interrupts_ls10(nvswitch_device *device, NvU32
void nvswitch_soe_disable_nport_fatal_interrupts_ls10(nvswitch_device *device, NvU32 nport,
NvU32 nportIntrEnable, NvU8 nportIntrType);
NvlStatus nvswitch_soe_issue_ingress_stop_ls10(nvswitch_device *device, NvU32 nport, NvBool bStop);
NvlStatus nvswitch_soe_reg_wr_32_ls10(nvswitch_device *device, NvU32 offset, NvU32 data);
#endif //_SOE_LS10_H_

14
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@@ -188,9 +188,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa995039a, 0x0190b31f, 0x3d7cb29d, 0x133f3ed4, 0x10c93f00, 0xcc9001dd, 0xff9fc401, 0x23009033,
0x00310080, 0x80e80f7c, 0x3c003118, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708,
0xd008f4d6, 0xe4ffafc4, 0xb6fffff9, 0x49fa0894, 0x01339004, 0x0cf52566, 0x07f8ff0d, 0x81fb3ab2,
0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x42b2c43d, 0x0011037e,
0x14bd043d, 0x0013a73e, 0x00102a3f, 0x01229001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x1abc0012,
0x00a6b010, 0x260a1ef4, 0xdf08f403, 0x51fb1ab2, 0x0000ea7e, 0x4a7e2f0b, 0x00f80018, 0x0000ea7e,
0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x41b2c43d, 0x0011037e,
0x043d24bd, 0x0013a73e, 0x00101a3f, 0x01119001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x2abc0012,
0x00a6b020, 0x260a1ef4, 0xdf08f403, 0x51fb2ab2, 0x0000ea7e, 0x4a7e2f0b, 0x00f80018, 0x0000ea7e,
0x4a7e2f0b, 0x00f80018, 0xa93f22f9, 0xd0b2c1b2, 0x3204c0b4, 0xff94f0ed, 0x08f4b9a6, 0x9402f805,
0xb99402bf, 0x02ae9804, 0x5200c0b3, 0x3cf0f9bc, 0xa998f9ed, 0x18203402, 0x0e1e0dcc, 0x909fbc01,
0x98019235, 0xebbb02a9, 0x909fbc04, 0x980191b5, 0x9fbc02a9, 0x029db590, 0xbc02a998, 0x9cb5909f,
@@ -426,8 +426,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xb9e404a9, 0x1bf50fff, 0x4dfe0224, 0x0c6ab201, 0x44dd9004, 0x0028d77e, 0x0a00a033, 0xb13ea532,
0x90b40032, 0xff94f111, 0x0239750f, 0xe71190b4, 0x75016c99, 0x90b40339, 0x1f95b611, 0xb4083935,
0xf9e411f0, 0x9ab30fff, 0xe7130fff, 0xb3016cf9, 0x0a0fff9a, 0x39350109, 0xb339bf09, 0x00900099,
0x00297cdf, 0x0dfb1800, 0x4a049990, 0x91b00ffc, 0xffb4f009, 0x0016bb7e, 0x743d94bd, 0x090d91b0,
0x94a9fffc, 0x3e0c91b0, 0x3d003277, 0x7e1c0ba4, 0xb200384c, 0x00a4b3a1, 0x0002f80c, 0x32de3e05,
0x00297cdf, 0x0dfb1800, 0xb0049990, 0x94bd0991, 0xb00ffc4a, 0xb4f00d91, 0x16bb7eff, 0x3dfc0900,
0x94a9ff74, 0x3e0c91b0, 0x3d003277, 0x7e1c0ba4, 0xb200384c, 0x00a4b3a1, 0x0002f80c, 0x32de3e05,
0x0cb0b400, 0x7eff7ac4, 0xbd0016fc, 0x061eb5e4, 0x0c09b0b4, 0x014dfe04, 0xbc40dd90, 0x6ab2b0ba,
0x7e011bb5, 0x320028d7, 0x00ad33a0, 0x90b40155, 0xffffdf10, 0x9ffd00ff, 0xa619a004, 0x071bf49f,
0x19a094bd, 0xb3011b98, 0xf80c00b4, 0x3e020002, 0xb40032de, 0x3f180ce0, 0x01b99208, 0xbc04b290,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x34352e3e, 0x16b9514e, 0xb0b75ac2, 0xb2eff27b,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0xaed46664, 0x0e67518e, 0x2e509632, 0x911f4d66,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x7941bd61, 0xa58046fa, 0xea4f2206, 0x1f176aa9,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x71adf495, 0x5294be55, 0x76b98dbd, 0xa2c54edf,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

14
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@@ -188,9 +188,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa995039a, 0x0190b31f, 0x3d7cb29d, 0x133f3ed4, 0x10c93f00, 0xcc9001dd, 0xff9fc401, 0x23009033,
0x00310080, 0x80e80f7c, 0x3c003118, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708,
0xd008f4d6, 0xe4ffafc4, 0xb6fffff9, 0x49fa0894, 0x01339004, 0x0cf52566, 0x07f8ff0d, 0x81fb3ab2,
0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x42b2c43d, 0x0011037e,
0x14bd043d, 0x0013a73e, 0x00102a3f, 0x01229001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x1abc0012,
0x00a6b010, 0x260a1ef4, 0xdf08f403, 0x51fb1ab2, 0x0000ea7e, 0x4a7e2f0b, 0x00f80018, 0x0000ea7e,
0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x41b2c43d, 0x0011037e,
0x043d24bd, 0x0013a73e, 0x00101a3f, 0x01119001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x2abc0012,
0x00a6b020, 0x260a1ef4, 0xdf08f403, 0x51fb2ab2, 0x0000ea7e, 0x4a7e2f0b, 0x00f80018, 0x0000ea7e,
0x4a7e2f0b, 0x00f80018, 0xa93f22f9, 0xd0b2c1b2, 0x3204c0b4, 0xff94f0ed, 0x08f4b9a6, 0x9402f805,
0xb99402bf, 0x02ae9804, 0x5200c0b3, 0x3cf0f9bc, 0xa998f9ed, 0x18203402, 0x0e1e0dcc, 0x909fbc01,
0x98019235, 0xebbb02a9, 0x909fbc04, 0x980191b5, 0x9fbc02a9, 0x029db590, 0xbc02a998, 0x9cb5909f,
@@ -426,8 +426,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xb9e404a9, 0x1bf50fff, 0x4dfe0224, 0x0c6ab201, 0x44dd9004, 0x0028d77e, 0x0a00a033, 0xb13ea532,
0x90b40032, 0xff94f111, 0x0239750f, 0xe71190b4, 0x75016c99, 0x90b40339, 0x1f95b611, 0xb4083935,
0xf9e411f0, 0x9ab30fff, 0xe7130fff, 0xb3016cf9, 0x0a0fff9a, 0x39350109, 0xb339bf09, 0x00900099,
0x00297cdf, 0x0dfb1800, 0x4a049990, 0x91b00ffc, 0xffb4f009, 0x0016bb7e, 0x743d94bd, 0x090d91b0,
0x94a9fffc, 0x3e0c91b0, 0x3d003277, 0x7e1c0ba4, 0xb200384c, 0x00a4b3a1, 0x0002f80c, 0x32de3e05,
0x00297cdf, 0x0dfb1800, 0xb0049990, 0x94bd0991, 0xb00ffc4a, 0xb4f00d91, 0x16bb7eff, 0x3dfc0900,
0x94a9ff74, 0x3e0c91b0, 0x3d003277, 0x7e1c0ba4, 0xb200384c, 0x00a4b3a1, 0x0002f80c, 0x32de3e05,
0x0cb0b400, 0x7eff7ac4, 0xbd0016fc, 0x061eb5e4, 0x0c09b0b4, 0x014dfe04, 0xbc40dd90, 0x6ab2b0ba,
0x7e011bb5, 0x320028d7, 0x00ad33a0, 0x90b40155, 0xffffdf10, 0x9ffd00ff, 0xa619a004, 0x071bf49f,
0x19a094bd, 0xb3011b98, 0xf80c00b4, 0x3e020002, 0xb40032de, 0x3f180ce0, 0x01b99208, 0xbc04b290,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x34352e3e, 0x16b9514e, 0xb0b75ac2, 0xb2eff27b,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0xaed46664, 0x0e67518e, 0x2e509632, 0x911f4d66,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x7941bd61, 0xa58046fa, 0xea4f2206, 0x1f176aa9,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x71adf495, 0x5294be55, 0x76b98dbd, 0xa2c54edf,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

11
src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c
View File

@@ -212,8 +212,15 @@ _inforom_nvlink_start_correctable_error_recording
pNvlinkState->bCallbackPending = NV_FALSE;
nvswitch_task_create(device, &_nvswitch_nvlink_1hz_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS, 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &_nvswitch_nvlink_1hz_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS, 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping NVLINK heartbeat task when TNVL is enabled\n");
}
}
NvlStatus

18
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -8301,6 +8301,24 @@ nvswitch_tnvl_get_status_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_send_tnvl_prelock_cmd_lr10
(
nvswitch_device *device
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
void
nvswitch_tnvl_disable_interrupts_lr10
(
nvswitch_device *device
)
{
return;
}
//
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
// macro in haldef_nvswitch.h

7
src/common/nvswitch/kernel/ls10/cci_ls10.c
View File

@@ -386,6 +386,13 @@ nvswitch_is_cci_supported_ls10
nvswitch_device *device
)
{
// Skip CCI on TNVL mode
if (nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, INFO, "CCI is not supported on TNVL mode\n");
return NV_FALSE;
}
if (FLD_TEST_DRF(_SWITCH_REGKEY, _CCI_CONTROL, _ENABLE, _FALSE,
device->regkeys.cci_control))
{

7
src/common/nvswitch/kernel/ls10/fsprpc_ls10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -585,13 +585,16 @@ nvswitch_fsprpc_get_caps_ls10
TNVL_RPC_CAPS_PAYLOAD payload;
TNVL_RPC_CAPS_RSP_PAYLOAD responsePayload;
NvlStatus status;
NVSWITCH_TIMEOUT timeout;
payload.subMessageId = TNVL_CAPS_SUBMESSAGE_ID;
nvswitch_os_memset(&responsePayload, 0, sizeof(TNVL_RPC_CAPS_RSP_PAYLOAD));
nvswitch_timeout_create(5 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
status = nvswitch_fsp_send_and_read_message(device,
(NvU8*) &payload, sizeof(TNVL_RPC_CAPS_PAYLOAD), NVDM_TYPE_CAPS_QUERY,
(NvU8*) &responsePayload, sizeof(TNVL_RPC_CAPS_RSP_PAYLOAD));
(NvU8*) &responsePayload, sizeof(TNVL_RPC_CAPS_RSP_PAYLOAD), &timeout);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "RPC failed for FSP caps query\n");

735
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

File diff suppressed because it is too large Load Diff

25
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -293,7 +293,7 @@ nvswitch_destroy_device_state_ls10
{
ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
if (nvswitch_is_soe_supported(device))
if (NVSWITCH_ENG_VALID_LS10(device, SOE, 0) && nvswitch_is_soe_supported(device))
{
nvswitch_soe_unregister_events(device);
nvswitch_unload_soe_ls10(device);
@@ -3089,13 +3089,6 @@ nvswitch_is_soe_supported_ls10
NVSWITCH_PRINT(device, WARN, "SOE can not be disabled via regkey.\n");
}
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, INFO,
"SOE is not supported when TNVL mode is locked\n");
return NV_FALSE;
}
return NV_TRUE;
}
@@ -3143,13 +3136,6 @@ nvswitch_is_inforom_supported_ls10
return NV_FALSE;
}
if (nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, INFO,
"INFOROM is not supported when TNVL mode is enabled\n");
return NV_FALSE;
}
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO,
@@ -4637,7 +4623,14 @@ nvswitch_eng_wr_ls10
return;
}
nvswitch_reg_write_32(device, base_addr + offset, data);
if (nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_tnvl_reg_wr_32_ls10(device, eng_id, eng_bcast, eng_instance, base_addr, offset, data);
}
else
{
nvswitch_reg_write_32(device, base_addr + offset, data);
}
#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS)
{

158
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -666,6 +666,76 @@ nvswitch_soe_issue_ingress_stop_ls10
return NVL_SUCCESS;
}
/*
* @Brief : Perform register writes in SOE during TNVL
*
* @param[in] device
* @param[in] offset
* @param[in] data
*/
NvlStatus
nvswitch_soe_reg_wr_32_ls10
(
nvswitch_device *device,
NvU32 offset,
NvU32 data
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_TNVL_CMD_REGISTER_WRITE *pRegisterWrite;
NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO,
"%s: SOE is not supported\n",
__FUNCTION__);
return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
}
status = device->hal.nvswitch_ctrl_get_bios_info(device, &params);
if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE))
{
nvswitch_reg_write_32(device, offset, data);
return NVL_SUCCESS;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, REGISTER_WRITE);
pRegisterWrite = &cmd.cmd.tnvl.registerWrite;
pRegisterWrite->cmdType = RM_SOE_TNVL_CMD_ISSUE_REGISTER_WRITE;
pRegisterWrite->offset = offset;
pRegisterWrite->data = data;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to send REGISTER_WRITE command to SOE, offset = 0x%x, data = 0x%x\n",
__FUNCTION__, offset, data);
return -NVL_ERR_GENERIC;
}
return NVL_SUCCESS;
}
/*
* @Brief : Init sequence for SOE FSP RISCV image
*
@@ -716,14 +786,21 @@ nvswitch_init_soe_ls10
}
// Register SOE callbacks
status = nvswitch_soe_register_event_callbacks(device);
if (status != NVL_SUCCESS)
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
"Failed to register SOE events\n");
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
"SOE init failed(2)\n");
return status;
status = nvswitch_soe_register_event_callbacks(device);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
"Failed to register SOE events\n");
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
"SOE init failed(2)\n");
return status;
}
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping registering SOE callbacks since TNVL is enabled\n");
}
// Sanity the command and message queues as a final check
@@ -1470,6 +1547,71 @@ _soeI2CAccess_LS10
return ret;
}
/*
* @Brief : Send TNVL Pre Lock command to SOE
*
* @param[in] device
*/
NvlStatus
nvswitch_send_tnvl_prelock_cmd_ls10
(
nvswitch_device *device
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_TNVL_CMD_PRE_LOCK_SEQUENCE *pTnvlPreLock;
NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported\n",
__FUNCTION__);
return -NVL_ERR_NOT_SUPPORTED;
}
status = device->hal.nvswitch_ctrl_get_bios_info(device, &params);
if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND))
{
NVSWITCH_PRINT(device, INFO,
"%s: Skipping TNVL_CMD_PRE_LOCK_SEQUENCE command to SOE. Update firmware "
"from .%02X to .%02X\n",
__FUNCTION__, (NvU32)((params.version & SOE_VBIOS_VERSION_MASK) >> 16),
SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND);
return -NVL_ERR_NOT_SUPPORTED;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, PRE_LOCK_SEQUENCE);
pTnvlPreLock = &cmd.cmd.tnvl.preLockSequence;
pTnvlPreLock->cmdType = RM_SOE_TNVL_CMD_ISSUE_PRE_LOCK_SEQUENCE;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to send PRE_LOCK_SEQUENCE command to SOE, status 0x%x\n",
__FUNCTION__, status);
return -NVL_ERR_GENERIC;
}
return NVL_SUCCESS;
}
/**
* @brief set hal function pointers for functions defined in LR10 (i.e. this file)
*

124
src/common/nvswitch/kernel/ls10/tnvl_ls10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,9 +26,12 @@
#include "common_nvswitch.h"
#include "haldef_nvswitch.h"
#include "ls10/ls10.h"
#include "ls10/soe_ls10.h"
#include "nvswitch/ls10/dev_nvlsaw_ip.h"
#include "nvswitch/ls10/dev_nvlsaw_ip_addendum.h"
#include "nvswitch/ls10/dev_ctrl_ip.h"
#include "nvswitch/ls10/dev_ctrl_ip_addendum.h"
#include <stddef.h>
@@ -639,6 +642,7 @@ _nvswitch_tnvl_get_cert_chain_from_fsp_ls10
NvlStatus status;
TNVL_GET_ATT_CERTS_CMD_PAYLOAD *pCmdPayload = nvswitch_os_malloc(sizeof(TNVL_GET_ATT_CERTS_CMD_PAYLOAD));
TNVL_GET_ATT_CERTS_RSP_PAYLOAD *pRspPayload = nvswitch_os_malloc(sizeof(TNVL_GET_ATT_CERTS_RSP_PAYLOAD));
NVSWITCH_TIMEOUT timeout;
if (pCmdPayload == NULL || pRspPayload == NULL)
{
@@ -653,9 +657,11 @@ _nvswitch_tnvl_get_cert_chain_from_fsp_ls10
pCmdPayload->minorVersion = 0;
pCmdPayload->majorVersion = 1;
nvswitch_timeout_create(5 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
status = nvswitch_fsp_send_and_read_message(device,
(NvU8*) pCmdPayload, sizeof(TNVL_GET_ATT_CERTS_CMD_PAYLOAD), NVDM_TYPE_TNVL,
(NvU8*) pRspPayload, sizeof(TNVL_GET_ATT_CERTS_RSP_PAYLOAD));
(NvU8*) pRspPayload, sizeof(TNVL_GET_ATT_CERTS_RSP_PAYLOAD), &timeout);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
@@ -762,6 +768,10 @@ nvswitch_tnvl_get_attestation_certificate_chain_ls10
goto ErrorExit;
}
certChainLength = certChainLength -
NVSWITCH_IK_HASH_LENGTH -
NVSWITCH_ATT_CERT_SIZE_FIELD_LENGTH -
NVSWITCH_ATT_RSVD1_FIELD_LENGTH;
//
// pCertChainBufferEnd represents last valid byte for cert buffer.
//
@@ -865,6 +875,7 @@ nvswitch_tnvl_get_attestation_report_ls10
NvlStatus status;
TNVL_GET_ATT_REPORT_CMD_PAYLOAD *pCmdPayload;
TNVL_GET_ATT_REPORT_RSP_PAYLOAD *pRspPayload;
NVSWITCH_TIMEOUT timeout;
if (!nvswitch_is_tnvl_mode_enabled(device))
{
@@ -892,9 +903,11 @@ nvswitch_tnvl_get_attestation_report_ls10
pCmdPayload->majorVersion = 1;
nvswitch_os_memcpy(pCmdPayload->nonce, params->nonce, NVSWITCH_NONCE_SIZE);
nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
status = nvswitch_fsp_send_and_read_message(device,
(NvU8*) pCmdPayload, sizeof(TNVL_GET_ATT_REPORT_CMD_PAYLOAD), NVDM_TYPE_TNVL,
(NvU8*) pRspPayload, sizeof(TNVL_GET_ATT_REPORT_RSP_PAYLOAD));
(NvU8*) pRspPayload, sizeof(TNVL_GET_ATT_REPORT_RSP_PAYLOAD), &timeout);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
@@ -937,6 +950,9 @@ nvswitch_detect_tnvl_mode_ls10
val = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _TNVL_MODE);
if (FLD_TEST_DRF(_NVLSAW, _TNVL_MODE, _STATUS, _ENABLED, val))
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL Mode Detected\n",
__FUNCTION__);
device->tnvl_mode = NVSWITCH_DEVICE_TNVL_MODE_ENABLED;
}
@@ -970,6 +986,7 @@ nvswitch_tnvl_send_fsp_lock_config_ls10
NvlStatus status;
TNVL_LOCK_CONFIG_CMD_PAYLOAD *pCmdPayload;
TNVL_LOCK_CONFIG_RSP_PAYLOAD *pRspPayload;
NVSWITCH_TIMEOUT timeout;
if (!nvswitch_is_tnvl_mode_enabled(device))
{
@@ -995,9 +1012,11 @@ nvswitch_tnvl_send_fsp_lock_config_ls10
pCmdPayload->minorVersion = 0;
pCmdPayload->majorVersion = 1;
nvswitch_timeout_create(5 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
status = nvswitch_fsp_send_and_read_message(device,
(NvU8*) pCmdPayload, sizeof(TNVL_LOCK_CONFIG_CMD_PAYLOAD), NVDM_TYPE_TNVL,
(NvU8*) pRspPayload, sizeof(TNVL_LOCK_CONFIG_RSP_PAYLOAD));
(NvU8*) pRspPayload, sizeof(TNVL_LOCK_CONFIG_RSP_PAYLOAD), &timeout);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
@@ -1035,3 +1054,100 @@ nvswitch_tnvl_get_status_ls10
params->status = device->tnvl_mode;
return NVL_SUCCESS;
}
static NvBool
_nvswitch_reg_cpu_write_allow_list_ls10
(
nvswitch_device *device,
NVSWITCH_ENGINE_ID eng_id,
NvU32 offset
)
{
switch (eng_id)
{
case NVSWITCH_ENGINE_ID_SOE:
case NVSWITCH_ENGINE_ID_GIN:
case NVSWITCH_ENGINE_ID_FSP:
return NV_TRUE;
case NVSWITCH_ENGINE_ID_SAW:
if (offset == NV_NVLSAW_DRIVER_ATTACH_DETACH)
return NV_TRUE;
default :
return NV_FALSE;
}
}
void
nvswitch_tnvl_reg_wr_32_ls10
(
nvswitch_device *device,
NVSWITCH_ENGINE_ID eng_id,
NvU32 eng_bcast,
NvU32 eng_instance,
NvU32 base_addr,
NvU32 offset,
NvU32 data
)
{
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL mode is not enabled\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return;
}
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL mode is locked\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return;
}
if (_nvswitch_reg_cpu_write_allow_list_ls10(device, eng_id, offset))
{
nvswitch_reg_write_32(device, base_addr + offset, data);
}
else
{
if (nvswitch_soe_reg_wr_32_ls10(device, base_addr + offset, data) != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: SOE ENG_WR failed for 0x%x[%d] %s @0x%08x+0x%06x = 0x%08x\n",
__FUNCTION__,
eng_id, eng_instance,
(
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" :
"??"
),
base_addr, offset, data);
NVSWITCH_ASSERT(0);
}
}
}
void
nvswitch_tnvl_disable_interrupts_ls10
(
nvswitch_device *device
)
{
//
// In TNVL locked disable non-fatal NVLW, NPG, and legacy interrupt,
// disable additional non-fatals on those partitions.
//
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX),
0xFFFF);
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
0xFFFF);
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_UNITS_IDX),
0xFFFFFFFF);
}

78
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1032,6 +1032,15 @@ _nvswitch_ctrl_get_tnvl_status
return device->hal.nvswitch_tnvl_get_status(device, params);
}
void
nvswitch_tnvl_disable_interrupts
(
nvswitch_device *device
)
{
device->hal.nvswitch_tnvl_disable_interrupts(device);
}
static NvlStatus
_nvswitch_construct_soe
(
@@ -1879,9 +1888,16 @@ nvswitch_lib_initialize_device
(void)device->hal.nvswitch_read_oob_blacklist_state(device);
(void)device->hal.nvswitch_write_fabric_state(device);
nvswitch_task_create(device, &nvswitch_fabric_state_heartbeat,
NVSWITCH_HEARTBEAT_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_fabric_state_heartbeat,
NVSWITCH_HEARTBEAT_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping Fabric state heartbeat background task when TNVL is enabled\n");
}
//
// Blacklisted devices return successfully in order to preserve the fabric state heartbeat
@@ -1985,12 +2001,26 @@ nvswitch_lib_initialize_device
if (device->regkeys.latency_counter == NV_SWITCH_REGKEY_LATENCY_COUNTER_LOGGING_ENABLE)
{
nvswitch_task_create(device, &nvswitch_internal_latency_bin_log,
nvswitch_get_latency_sample_interval_msec(device) * NVSWITCH_INTERVAL_1MSEC_IN_NS * 9/10, 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_internal_latency_bin_log,
nvswitch_get_latency_sample_interval_msec(device) * NVSWITCH_INTERVAL_1MSEC_IN_NS * 9/10, 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping Internal latency background task when TNVL is enabled\n");
}
}
nvswitch_task_create(device, &nvswitch_ecc_writeback_task,
(60 * NVSWITCH_INTERVAL_1SEC_IN_NS), 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_ecc_writeback_task,
(60 * NVSWITCH_INTERVAL_1SEC_IN_NS), 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping ECC writeback background task when TNVL is enabled\n");
}
if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device))
{
@@ -2000,8 +2030,15 @@ nvswitch_lib_initialize_device
}
else
{
nvswitch_task_create(device, &nvswitch_monitor_thermal_alert,
100*NVSWITCH_INTERVAL_1MSEC_IN_NS, 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_monitor_thermal_alert,
100*NVSWITCH_INTERVAL_1MSEC_IN_NS, 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping Thermal alert background task when TNVL is enabled\n");
}
}
device->nvlink_device->initialized = 1;
@@ -5987,6 +6024,15 @@ nvswitch_tnvl_send_fsp_lock_config
return device->hal.nvswitch_tnvl_send_fsp_lock_config(device);
}
NvlStatus
nvswitch_send_tnvl_prelock_cmd
(
nvswitch_device *device
)
{
return device->hal.nvswitch_send_tnvl_prelock_cmd(device);
}
static NvlStatus
_nvswitch_ctrl_set_device_tnvl_lock
(
@@ -6020,8 +6066,18 @@ _nvswitch_ctrl_set_device_tnvl_lock
//
// Disable non-fatal and legacy interrupts
// Disable commands to SOE
//
nvswitch_tnvl_disable_interrupts(device);
//
//
// Send Pre-Lock sequence command to SOE
//
status = nvswitch_send_tnvl_prelock_cmd(device);
if (status != NVL_SUCCESS)
{
return status;
}
// Send lock-config command to FSP
status = nvswitch_tnvl_send_fsp_lock_config(device);