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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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565.57.01
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -666,6 +666,76 @@ nvswitch_soe_issue_ingress_stop_ls10
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return NVL_SUCCESS;
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}
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/*
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* @Brief : Perform register writes in SOE during TNVL
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*
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* @param[in] device
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* @param[in] offset
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* @param[in] data
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*/
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NvlStatus
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nvswitch_soe_reg_wr_32_ls10
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(
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nvswitch_device *device,
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NvU32 offset,
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NvU32 data
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)
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{
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FLCN *pFlcn;
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NvU32 cmdSeqDesc = 0;
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NV_STATUS status;
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RM_FLCN_CMD_SOE cmd;
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NVSWITCH_TIMEOUT timeout;
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RM_SOE_TNVL_CMD_REGISTER_WRITE *pRegisterWrite;
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NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
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if (!nvswitch_is_soe_supported(device))
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{
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NVSWITCH_PRINT(device, INFO,
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"%s: SOE is not supported\n",
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__FUNCTION__);
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return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
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}
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status = device->hal.nvswitch_ctrl_get_bios_info(device, ¶ms);
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if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
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SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE))
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{
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nvswitch_reg_write_32(device, offset, data);
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return NVL_SUCCESS;
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}
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pFlcn = device->pSoe->pFlcn;
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nvswitch_os_memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
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cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, REGISTER_WRITE);
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pRegisterWrite = &cmd.cmd.tnvl.registerWrite;
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pRegisterWrite->cmdType = RM_SOE_TNVL_CMD_ISSUE_REGISTER_WRITE;
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pRegisterWrite->offset = offset;
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pRegisterWrite->data = data;
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nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
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status = flcnQueueCmdPostBlocking(device, pFlcn,
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(PRM_FLCN_CMD)&cmd,
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NULL, // pMsg
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NULL, // pPayload
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SOE_RM_CMDQ_LOG_ID,
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&cmdSeqDesc,
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&timeout);
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if (status != NV_OK)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: Failed to send REGISTER_WRITE command to SOE, offset = 0x%x, data = 0x%x\n",
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__FUNCTION__, offset, data);
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return -NVL_ERR_GENERIC;
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}
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return NVL_SUCCESS;
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}
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/*
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* @Brief : Init sequence for SOE FSP RISCV image
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*
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@@ -716,14 +786,21 @@ nvswitch_init_soe_ls10
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}
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// Register SOE callbacks
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status = nvswitch_soe_register_event_callbacks(device);
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if (status != NVL_SUCCESS)
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if (!nvswitch_is_tnvl_mode_enabled(device))
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{
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
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"Failed to register SOE events\n");
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
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"SOE init failed(2)\n");
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return status;
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status = nvswitch_soe_register_event_callbacks(device);
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if (status != NVL_SUCCESS)
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{
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
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"Failed to register SOE events\n");
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
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"SOE init failed(2)\n");
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return status;
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}
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}
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else
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{
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NVSWITCH_PRINT(device, INFO, "Skipping registering SOE callbacks since TNVL is enabled\n");
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}
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// Sanity the command and message queues as a final check
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@@ -1470,6 +1547,71 @@ _soeI2CAccess_LS10
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return ret;
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}
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/*
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* @Brief : Send TNVL Pre Lock command to SOE
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*
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* @param[in] device
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*/
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NvlStatus
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nvswitch_send_tnvl_prelock_cmd_ls10
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(
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nvswitch_device *device
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)
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{
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FLCN *pFlcn;
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NvU32 cmdSeqDesc = 0;
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NV_STATUS status;
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RM_FLCN_CMD_SOE cmd;
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NVSWITCH_TIMEOUT timeout;
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RM_SOE_TNVL_CMD_PRE_LOCK_SEQUENCE *pTnvlPreLock;
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NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
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if (!nvswitch_is_soe_supported(device))
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{
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NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported\n",
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__FUNCTION__);
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return -NVL_ERR_NOT_SUPPORTED;
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}
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status = device->hal.nvswitch_ctrl_get_bios_info(device, ¶ms);
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if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
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SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND))
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{
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NVSWITCH_PRINT(device, INFO,
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"%s: Skipping TNVL_CMD_PRE_LOCK_SEQUENCE command to SOE. Update firmware "
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"from .%02X to .%02X\n",
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__FUNCTION__, (NvU32)((params.version & SOE_VBIOS_VERSION_MASK) >> 16),
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SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND);
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return -NVL_ERR_NOT_SUPPORTED;
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}
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pFlcn = device->pSoe->pFlcn;
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nvswitch_os_memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
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cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, PRE_LOCK_SEQUENCE);
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pTnvlPreLock = &cmd.cmd.tnvl.preLockSequence;
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pTnvlPreLock->cmdType = RM_SOE_TNVL_CMD_ISSUE_PRE_LOCK_SEQUENCE;
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nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
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status = flcnQueueCmdPostBlocking(device, pFlcn,
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(PRM_FLCN_CMD)&cmd,
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NULL, // pMsg
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NULL, // pPayload
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SOE_RM_CMDQ_LOG_ID,
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&cmdSeqDesc,
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&timeout);
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if (status != NV_OK)
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{
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NVSWITCH_PRINT(device, ERROR, "%s: Failed to send PRE_LOCK_SEQUENCE command to SOE, status 0x%x\n",
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__FUNCTION__, status);
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return -NVL_ERR_GENERIC;
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}
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return NVL_SUCCESS;
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}
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/**
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* @brief set hal function pointers for functions defined in LR10 (i.e. this file)
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*
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