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This commit is contained in:
Bernhard Stoeckner
2024-10-22 17:38:58 +02:00
parent ed4be64962
commit d5a0858f90
1049 changed files with 209491 additions and 167508 deletions
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58
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -109,12 +109,20 @@ enum {
typedef struct RUSD_BAR1_MEMORY_INFO {
volatile NvU64 lastModifiedTimestamp;
//
// Non-polled data, not tied to any specific RM API
// Total size and available memory in Bar1
//
NvU32 bar1Size;
NvU32 bar1AvailSize;
} RUSD_BAR1_MEMORY_INFO;
typedef struct RUSD_PMA_MEMORY_INFO {
volatile NvU64 lastModifiedTimestamp;
//
// Non-polled data, not tied to any specific RM API
// Total size and available memory in PMA
//
NvU64 totalPmaMemory;
NvU64 freePmaMemory;
} RUSD_PMA_MEMORY_INFO;
@@ -152,12 +160,13 @@ typedef struct RUSD_PERF_DEVICE_UTILIZATION {
typedef struct RUSD_PERF_CURRENT_PSTATE {
volatile NvU64 lastModifiedTimestamp;
// Provided from NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE
NvU32 currentPstate;
} RUSD_PERF_CURRENT_PSTATE;
typedef struct RUSD_CLK_THROTTLE_REASON {
volatile NvU64 lastModifiedTimestamp;
NvU32 reasonMask; // Bitmask of RUSD_CLK_THROTTLE_REASON
NvU32 reasonMask; // Bitmask of RUSD_CLK_THROTTLE_REASON_*
} RUSD_CLK_THROTTLE_REASON;
typedef struct RUSD_MEM_ERROR_COUNTS {
@@ -174,6 +183,7 @@ typedef struct RUSD_MEM_ERROR_COUNTS {
typedef struct RUSD_MEM_ECC {
volatile NvU64 lastModifiedTimestamp;
// Provided from NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS
RUSD_MEM_ERROR_COUNTS count[RUSD_MEMORY_ERROR_TYPE_COUNT];
} RUSD_MEM_ECC;
@@ -198,6 +208,7 @@ typedef struct RUSD_TEMPERATURE {
} RUSD_TEMPERATURE;
typedef struct RUSD_MEM_ROW_REMAP_INFO {
// Provided from NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM
NvU32 histogramMax; // No remapped row is used.
NvU32 histogramHigh; // One remapped row is used.
NvU32 histogramPartial; // More than one remapped rows are used.
@@ -229,6 +240,7 @@ typedef struct RUSD_AVG_POWER_USAGE {
typedef struct RUSD_INST_POWER_INFO {
NvU32 instGpuPower; // mW
NvU32 instModulePower; // mW
NvU32 instCpuPower; // mW
} RUSD_INST_POWER_INFO;
typedef struct RUSD_INST_POWER_USAGE {
@@ -238,22 +250,50 @@ typedef struct RUSD_INST_POWER_USAGE {
typedef struct RUSD_SHADOW_ERR_CONT {
volatile NvU64 lastModifiedTimestamp;
//
// Non-polled data, not tied to any specific RM API
// Shadowed ERR_CONT register value
//
NvU32 shadowErrContVal;
} RUSD_SHADOW_ERR_CONT;
// Each RUSD_BUS_DATA_* define corresponds to the equivalent NV2080_CTRL_BUS_INFO_INDEX_*
#define RUSD_BUS_DATA_PCIE_GEN_INFO 0
#define RUSD_BUS_DATA_PCIE_GPU_LINK_LINECODE_ERRORS 1
#define RUSD_BUS_DATA_PCIE_GPU_LINK_CRC_ERRORS 2
#define RUSD_BUS_DATA_PCIE_GPU_LINK_NAKS_RECEIVED 3
#define RUSD_BUS_DATA_PCIE_GPU_LINK_FAILED_L0S_EXITS 4
#define RUSD_BUS_DATA_PCIE_GPU_LINK_CORRECTABLE_ERRORS 5
#define RUSD_BUS_DATA_PCIE_GPU_LINK_NONFATAL_ERRORS 6
#define RUSD_BUS_DATA_PCIE_GPU_LINK_FATAL_ERRORS 7
#define RUSD_BUS_DATA_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS 8
#define RUSD_BUS_DATA_COUNT 9
typedef struct RUSD_PCIE_DATA_INFO {
// Provided from NV2080_CTRL_CMD_BUS_GET_INFO_V2
NvU32 data[RUSD_BUS_DATA_COUNT];
} RUSD_PCIE_DATA_INFO;
typedef struct RUSD_PCIE_DATA {
volatile NvU64 lastModifiedTimestamp;
RUSD_PCIE_DATA_INFO info;
} RUSD_PCIE_DATA;
typedef struct RUSD_GR_INFO
{
volatile NvU64 lastModifiedTimestamp;
NvBool bCtxswLoggingEnabled;
} RUSD_GR_INFO;
typedef struct NV00DE_SHARED_DATA {
// Temporarily duplicated - to be removed by nested structs below
volatile NvU64 seq;
NvU32 bar1Size;
NvU32 bar1AvailSize;
NV_DECLARE_ALIGNED(RUSD_BAR1_MEMORY_INFO bar1MemoryInfo, 8);
NV_DECLARE_ALIGNED(RUSD_PMA_MEMORY_INFO pmaMemoryInfo, 8);
NV_DECLARE_ALIGNED(RUSD_SHADOW_ERR_CONT shadowErrCont, 8);
NV_DECLARE_ALIGNED(RUSD_GR_INFO grInfo, 8);
// gpuUpdateUserSharedData is sensitive to these two sections being contiguous
//
@@ -295,6 +335,9 @@ typedef struct NV00DE_SHARED_DATA {
// POLL_POWER
NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8);
// POLL_PCI
NV_DECLARE_ALIGNED(RUSD_PCIE_DATA pciBusData, 8);
} NV00DE_SHARED_DATA;
//
@@ -306,6 +349,7 @@ typedef struct NV00DE_SHARED_DATA {
#define NV00DE_RUSD_POLL_MEMORY 0x4
#define NV00DE_RUSD_POLL_POWER 0x8
#define NV00DE_RUSD_POLL_THERMAL 0x10
#define NV00DE_RUSD_POLL_PCI 0x20
typedef struct NV00DE_ALLOC_PARAMETERS {
NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed

5
src/common/sdk/nvidia/inc/class/cl00f8.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -95,11 +95,8 @@
#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000
#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV_MEMORY_FABRIC_PAGE_SIZE_256G 0x4000000000
#define NV00F8_ALLOC_FLAGS_DEFAULT 0
#define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0)
#define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1)

19
src/common/sdk/nvidia/inc/class/cl2080_notification.h
View File

@@ -204,7 +204,6 @@ extern "C" {
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_UNUSED_1 (164) // Unused
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165)
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_CE10 (166)
#define NV2080_NOTIFIERS_CE11 (167)
#define NV2080_NOTIFIERS_CE12 (168)
@@ -219,7 +218,6 @@ extern "C" {
#define NV2080_NOTIFIERS_NVPCF_EVENTS (177)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178)
#define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179)
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_OFA1 (180)
#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182)
@@ -230,7 +228,12 @@ extern "C" {
#define NV2080_NOTIFIERS_ECC_SBE_STORM (187)
#define NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT (188)
#define NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE (189)
#define NV2080_NOTIFIERS_MAXCOUNT (190)
#define NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR (190)
#define NV2080_NOTIFIERS_GPU_UNAVAILABLE (191)
#define NV2080_NOTIFIERS_GPU_RECOVERY_ACTION (192)
#define NV2080_NOTIFIERS_POWER_SUSPEND (193)
#define NV2080_NOTIFIERS_POWER_RESUME (194)
#define NV2080_NOTIFIERS_MAXCOUNT (195)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
@@ -238,7 +241,6 @@ extern "C" {
#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7)))
// Indexed CE notifier reference
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_CE(x) (((x) < 10) ? (NV2080_NOTIFIERS_CE0 + (x)) : (NV2080_NOTIFIERS_CE10 + (x) - 10))
#define NV2080_NOTIFIERS_CE_IDX(x) (((x) <= NV2080_NOTIFIERS_CE9) ? ((x) - NV2080_NOTIFIERS_CE0) : ((x) - NV2080_NOTIFIERS_CE10 + 10))
#define NV2080_NOTIFIER_TYPE_IS_CE(x) ((((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) || \
@@ -258,7 +260,6 @@ extern "C" {
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7))
// Indexed OFA notifier reference
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_OFAn(x) ((x == 0) ? (NV2080_NOTIFIERS_OFA0) : (NV2080_NOTIFIERS_OFA1))
#define NV2080_NOTIFIERS_OFA_IDX(x) ((x == NV2080_NOTIFIERS_OFA0) ? ((x) - NV2080_NOTIFIERS_OFA0) : ((x) - NV2080_NOTIFIERS_OFA1 + 1))
#define NV2080_NOTIFIER_TYPE_IS_OFA(x) (((x) == NV2080_NOTIFIERS_OFA0) || ((x) == NV2080_NOTIFIERS_OFA1))
@@ -331,7 +332,6 @@ extern "C" {
#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_OFA0 NV2080_ENGINE_TYPE_OFA
// removal tracking bug: 3748354
// Update the TYPE_COMP_DECOMP_COPYN defines as well when you update COPYN defines
#define NV2080_ENGINE_TYPE_COPY10 (0x00000034)
#define NV2080_ENGINE_TYPE_COPY11 (0x00000035)
@@ -343,11 +343,9 @@ extern "C" {
#define NV2080_ENGINE_TYPE_COPY17 (0x0000003b)
#define NV2080_ENGINE_TYPE_COPY18 (0x0000003c)
#define NV2080_ENGINE_TYPE_COPY19 (0x0000003d)
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_OFA1 (0x0000003e)
#define NV2080_ENGINE_TYPE_RESERVED3f (0x0000003f)
// See TBD documentation for how these defines work with existing ENGINE_TYPE_COPYN defines
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 (0x00000040)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 (0x00000041)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 (0x00000042)
@@ -390,11 +388,9 @@ extern "C" {
#define NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19))
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0)
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_COPY(i) (((i) < 10) ? (NV2080_ENGINE_TYPE_COPY0 + (i)) : (NV2080_ENGINE_TYPE_COPY10 + (i) - 10))
#define NV2080_ENGINE_TYPE_IS_COPY(i) ((((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9)) || \
(((i) >= NV2080_ENGINE_TYPE_COPY10) && ((i) <= NV2080_ENGINE_TYPE_COPY19)) || \
(NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY(i)))
(((i) >= NV2080_ENGINE_TYPE_COPY10) && ((i) <= NV2080_ENGINE_TYPE_COPY19)))
#define NV2080_ENGINE_TYPE_COPY_IDX(i) (((i) <= NV2080_ENGINE_TYPE_COPY9) ? \
((i) - NV2080_ENGINE_TYPE_COPY0) : ((i) - NV2080_ENGINE_TYPE_COPY10 + 10))
@@ -414,7 +410,6 @@ extern "C" {
#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0)
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_OFAn(i) ((i == 0) ? (NV2080_ENGINE_TYPE_OFA0) : (NV2080_ENGINE_TYPE_OFA1))
#define NV2080_ENGINE_TYPE_IS_OFA(i) (((i) == NV2080_ENGINE_TYPE_OFA0) || ((i) == NV2080_ENGINE_TYPE_OFA1))
#define NV2080_ENGINE_TYPE_OFA_IDX(i) ((i == NV2080_ENGINE_TYPE_OFA0) ? ((i) - NV2080_ENGINE_TYPE_OFA0) : ((i) - NV2080_ENGINE_TYPE_OFA1 + 1))

24
src/common/sdk/nvidia/inc/class/cl90cdtrace.h
View File

@@ -39,4 +39,28 @@ typedef struct NV_RATS_GSP_TRACE_RECORD_V1
typedef NV_RATS_GSP_TRACE_RECORD_V1 NV_RATS_GSP_TRACE_RECORD;
#define VGPU_TRACING_BUFFER_KEEP_OLDEST 0
#define VGPU_TRACING_BUFFER_KEEP_NEWEST 1
typedef struct NV_RATS_VGPU_GSP_TRACING_BUFFER_V1{
NvU8 policy;
NvBool bGuestNotifInProgress;
NvU16 seqNo;
NvU32 bufferSize;
NvU32 bufferWatermark;
NvU32 recordCount;
NvU64 tracepointMask;
NvU32 read;
NvU32 write;
NvU64 lastReadTimestamp;
NV_RATS_GSP_TRACE_RECORD *buffer;
} NV_RATS_VGPU_GSP_TRACING_BUFFER_V1;
typedef NV_RATS_VGPU_GSP_TRACING_BUFFER_V1 NV_RATS_VGPU_GSP_TRACING_BUFFER;
#endif

2
src/common/sdk/nvidia/inc/class/cla084.h
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@@ -58,6 +58,7 @@
* hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient
* hMigRmHeapMemory -> MIG-RM heap memory handle
* bDeviceProfilingEnabled -> If set to true, profiling is allowed
* bGpupLiveMigrationEnabled -> True if GPUP LM is supported
*/
#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U)
@@ -88,4 +89,5 @@ typedef struct NVA084_ALLOC_PARAMETERS {
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
NvBool bDeviceProfilingEnabled;
NvBool bGpupLiveMigrationEnabled;
} NVA084_ALLOC_PARAMETERS;

50
src/common/sdk/nvidia/inc/class/clb1cc.h Normal file
View File

@@ -0,0 +1,50 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clb1cc.finn
//
#include "clb0cc.h"
#define MAXWELL_PROFILER_CONTEXT (0xb1ccU) /* finn: Evaluated from "NVB1CC_ALLOC_PARAMETERS_MESSAGE_ID" */
/*
* Creating the MAXWELL_PROFILER_CONTEXT object:
* - The profiler object is instantiated as a child of either a bc channel
* group or bc channel.
*/
#define NVB1CC_ALLOC_PARAMETERS_MESSAGE_ID (0xb1ccU)
typedef struct NVB1CC_ALLOC_PARAMETERS {
/*
* Handle of a specific subdevice of a broadcast device.
*/
NvHandle hSubDevice;
} NVB1CC_ALLOC_PARAMETERS;

41
src/common/sdk/nvidia/inc/class/clc970.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc970.finn
//
#define NVC970_DISPLAY (0xc970U) /* finn: Evaluated from "NVC970_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NVC970_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc970U)
typedef struct NVC970_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
} NVC970_ALLOCATION_PARAMETERS;

329
src/common/sdk/nvidia/inc/class/clc971.h Normal file
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@@ -0,0 +1,329 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc971_h_
#define _clc971_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC971_DISP_SF_USER (0x000C971)
typedef volatile struct {
NvU32 dispSfUserOffset[0x400];
} _NvC971DispSfUser, NvC971DispSfUserMap;
#define NVC971_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */
#define NVC971_SF_HDMI_INFO_IDX_GCP 0x00000001 /* */
#define NVC971_SF_HDMI_INFO_IDX_ACR 0x00000002 /* */
#define NVC971_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVC971_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */
#define NVC971_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */
#define NVC971_SF_HDMI_INFO_STATUS(i,j) (0x000E0004-0x000E0000+(i)*1024+(j)*64) /* R--4A */
#define NVC971_SF_HDMI_INFO_STATUS__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_STATUS__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */
#define NVC971_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC971_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC971_SF_HDMI_INFO_HEADER(i,j) (0x000E0008-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_HEADER__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_HEADER__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_HEADER_HB0 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_HEADER_HB1 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_HEADER_HB2 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW(i,j) (0x000E000C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH(i,j) (0x000E0010-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW(i,j) (0x000E0014-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH(i,j) (0x000E0018-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW(i,j) (0x000E001C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH(i,j) (0x000E0020-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW(i,j) (0x000E0024-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH(i,j) (0x000E0028-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_1 8 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_2 3 /* */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_GCP_CTRL(i) (0x000E0040-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_GCP_CTRL__SIZE_1 8 /* */
#define NVC971_SF_HDMI_GCP_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_GCP_STATUS(i) (0x000E0044-0x000E0000+(i)*1024) /* R--4A */
#define NVC971_SF_HDMI_GCP_STATUS__SIZE_1 8 /* */
#define NVC971_SF_HDMI_GCP_STATUS_SENT 0:0 /* R-IVF */
#define NVC971_SF_HDMI_GCP_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC971_SF_HDMI_GCP_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC971_SF_HDMI_GCP_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVC971_SF_HDMI_GCP_SUBPACK(i) (0x000E004C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_HDMI_GCP_SUBPACK__SIZE_1 8 /* */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL 24:24 /* RWIVF */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL_INIT 0x00000001 /* RWI-V */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL_SW 0x00000000 /* RW--V */
#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL_HW 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */
#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */
#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */
#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */
#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */
#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */
#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc971_h_

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src/common/sdk/nvidia/inc/class/clc973.h Normal file
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@@ -0,0 +1,379 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc973_h_
#define _clc973_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC973_DISP_CAPABILITIES 0xC973
#define NVC973_SYS_CAP 0x0 /* RW-4R */
#define NVC973_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
#define NVC973_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
#define NVC973_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
#define NVC973_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
#define NVC973_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
#define NVC973_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
#define NVC973_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
#define NVC973_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
#define NVC973_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVC973_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NVC973_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
#define NVC973_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
#define NVC973_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
#define NVC973_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
#define NVC973_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
#define NVC973_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
#define NVC973_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
#define NVC973_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
#define NVC973_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVC973_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
#define NVC973_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */
#define NVC973_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */
#define NVC973_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */
#define NVC973_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */
#define NVC973_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */
#define NVC973_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
#define NVC973_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
#define NVC973_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA 0x10 /* RW-4R */
#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC 0x18 /* RW-4R */
#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
#define NVC973_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVC973_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
#define NVC973_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
#define NVC973_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */
#define NVC973_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */
#define NVC973_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */
#define NVC973_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */
#define NVC973_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */
#define NVC973_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */
#define NVC973_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */
#define NVC973_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */
#define NVC973_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */
#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
#define NVC973_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */
#define NVC973_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */
#define NVC973_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
#define NVC973_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */
#define NVC973_SOR_CAP__SIZE_1 8 /* */
#define NVC973_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
#define NVC973_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
#define NVC973_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
#define NVC973_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
#define NVC973_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
#define NVC973_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
#define NVC973_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
#define NVC973_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
#define NVC973_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_SDI 16:16 /* RWIVF */
#define NVC973_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DP_A 24:24 /* RWIVF */
#define NVC973_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DP_B 25:25 /* RWIVF */
#define NVC973_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
#define NVC973_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
#define NVC973_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
#define NVC973_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
#define NVC973_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
#define NVC973_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#ifdef __cplusplus
};
#endif /* extern C */
#endif //_clc973_h_

168
src/common/sdk/nvidia/inc/class/clc97a.h Normal file
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@@ -0,0 +1,168 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc97a__h_
#define _clc97a__h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC97A_CURSOR_IMM_CHANNEL_PIO (0x0000C97A)
#define NVC97A_FREE (0x00000008)
#define NVC97A_FREE_COUNT 5:0
#define NVC97A_UPDATE (0x00000200)
#define NVC97A_SET_INTERLOCK_FLAGS (0x00000204)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVC97A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVC97A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0
#define NVC97A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc97a_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc97b_h_
#define _clc97b_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC97B_WINDOW_IMM_CHANNEL_DMA (0x0000C97B)
// dma opcode instructions
#define NVC97B_DMA
#define NVC97B_DMA_OPCODE 31:29
#define NVC97B_DMA_OPCODE_METHOD 0x00000000
#define NVC97B_DMA_OPCODE_JUMP 0x00000001
#define NVC97B_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVC97B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVC97B_DMA_METHOD_COUNT 27:18
#define NVC97B_DMA_METHOD_OFFSET 15:2
#define NVC97B_DMA_DATA 31:0
#define NVC97B_DMA_DATA_NOP 0x00000000
#define NVC97B_DMA_JUMP_OFFSET 15:2
#define NVC97B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVC97B_PUT (0x00000000)
#define NVC97B_PUT_PTR 9:0
#define NVC97B_GET (0x00000004)
#define NVC97B_GET_PTR 9:0
#define NVC97B_UPDATE (0x00000200)
#define NVC97B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
#define NVC97B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC97B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVC97B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVC97B_SET_POINT_OUT_X 15:0
#define NVC97B_SET_POINT_OUT_Y 31:16
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc97b_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc97e_h_
#define _clc97e_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC97E_WINDOW_CHANNEL_DMA (0x0000C97E)
// dma opcode instructions
#define NVC97E_DMA
#define NVC97E_DMA_OPCODE 31:29
#define NVC97E_DMA_OPCODE_METHOD 0x00000000
#define NVC97E_DMA_OPCODE_JUMP 0x00000001
#define NVC97E_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVC97E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVC97E_DMA_METHOD_COUNT 27:18
#define NVC97E_DMA_METHOD_OFFSET 15:2
#define NVC97E_DMA_DATA 31:0
#define NVC97E_DMA_DATA_NOP 0x00000000
#define NVC97E_DMA_JUMP_OFFSET 15:2
#define NVC97E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVC97E_PUT (0x00000000)
#define NVC97E_PUT_PTR 9:0
#define NVC97E_GET (0x00000004)
#define NVC97E_GET_PTR 9:0
#define NVC97E_UPDATE (0x00000200)
#define NVC97E_UPDATE_RELEASE_ELV 0:0
#define NVC97E_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVC97E_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVC97E_UPDATE_FLIP_LOCK_PIN 8:4
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVC97E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12
#define NVC97E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
#define NVC97E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
#define NVC97E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204)
#define NVC97E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0
#define NVC97E_GET_LINE (0x00000208)
#define NVC97E_GET_LINE_LINE 15:0
#define NVC97E_SET_SEMAPHORE_CONTROL (0x0000020C)
#define NVC97E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11
#define NVC97E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000)
#define NVC97E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001)
#define NVC97E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVC97E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVC97E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVC97E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14
#define NVC97E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000)
#define NVC97E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001)
#define NVC97E_SET_SEMAPHORE_ACQUIRE (0x00000210)
#define NVC97E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NVC97E_SET_SEMAPHORE_RELEASE (0x00000214)
#define NVC97E_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NVC97E_SET_NOTIFIER_CONTROL (0x00000220)
#define NVC97E_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVC97E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVC97E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVC97E_SET_SIZE (0x00000224)
#define NVC97E_SET_SIZE_WIDTH 15:0
#define NVC97E_SET_SIZE_HEIGHT 31:16
#define NVC97E_SET_STORAGE (0x00000228)
#define NVC97E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVC97E_SET_PARAMS (0x0000022C)
#define NVC97E_SET_PARAMS_FORMAT 7:0
#define NVC97E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVC97E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVC97E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVC97E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVC97E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVC97E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVC97E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVC97E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVC97E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVC97E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVC97E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVC97E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVC97E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVC97E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVC97E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVC97E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVC97E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVC97E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVC97E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVC97E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
#define NVC97E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
#define NVC97E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVC97E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVC97E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVC97E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVC97E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVC97E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVC97E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVC97E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVC97E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVC97E_SET_PARAMS_SWAP_UV 19:19
#define NVC97E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVC97E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVC97E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
#define NVC97E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
#define NVC97E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
#define NVC97E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVC97E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVC97E_SET_SEMAPHORE_RELEASE_HI (0x0000023C)
#define NVC97E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0
#define NVC97E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVC97E_SET_POINT_IN_X 15:0
#define NVC97E_SET_POINT_IN_Y 31:16
#define NVC97E_SET_SIZE_IN (0x00000298)
#define NVC97E_SET_SIZE_IN_WIDTH 15:0
#define NVC97E_SET_SIZE_IN_HEIGHT 31:16
#define NVC97E_SET_SIZE_OUT (0x000002A4)
#define NVC97E_SET_SIZE_OUT_WIDTH 15:0
#define NVC97E_SET_SIZE_OUT_HEIGHT 31:16
#define NVC97E_SET_CONTROL_INPUT_SCALER (0x000002A8)
#define NVC97E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0
#define NVC97E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NVC97E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NVC97E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4
#define NVC97E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NVC97E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004)
#define NVC97E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC)
#define NVC97E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0
#define NVC97E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12
#define NVC97E_SET_COMPOSITION_CONTROL (0x000002EC)
#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0
#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000)
#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001)
#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002)
#define NVC97E_SET_COMPOSITION_CONTROL_DEPTH 11:4
#define NVC97E_SET_COMPOSITION_CONTROL_BYPASS 16:16
#define NVC97E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000)
#define NVC97E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001)
#define NVC97E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0)
#define NVC97E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0
#define NVC97E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC97E_SET_KEY_ALPHA (0x000002F8)
#define NVC97E_SET_KEY_ALPHA_MIN 15:0
#define NVC97E_SET_KEY_ALPHA_MAX 31:16
#define NVC97E_SET_KEY_RED_CR (0x000002FC)
#define NVC97E_SET_KEY_RED_CR_MIN 15:0
#define NVC97E_SET_KEY_RED_CR_MAX 31:16
#define NVC97E_SET_KEY_GREEN_Y (0x00000300)
#define NVC97E_SET_KEY_GREEN_Y_MIN 15:0
#define NVC97E_SET_KEY_GREEN_Y_MAX 31:16
#define NVC97E_SET_KEY_BLUE_CB (0x00000304)
#define NVC97E_SET_KEY_BLUE_CB_MIN 15:0
#define NVC97E_SET_KEY_BLUE_CB_MAX 31:16
#define NVC97E_SET_PRESENT_CONTROL (0x00000308)
#define NVC97E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVC97E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVC97E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVC97E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVC97E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVC97E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVC97E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
#define NVC97E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C)
#define NVC97E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330)
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVC97E_SET_ACQ_SEMAPHORE_VALUE (0x00000334)
#define NVC97E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0
#define NVC97E_SET_SCAN_DIRECTION (0x0000033C)
#define NVC97E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0
#define NVC97E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000)
#define NVC97E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001)
#define NVC97E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1
#define NVC97E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000)
#define NVC97E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001)
#define NVC97E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2
#define NVC97E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000)
#define NVC97E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001)
#define NVC97E_SET_TIMESTAMP_ORIGIN_LO (0x00000340)
#define NVC97E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NVC97E_SET_TIMESTAMP_ORIGIN_HI (0x00000344)
#define NVC97E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NVC97E_SET_UPDATE_TIMESTAMP_LO (0x00000348)
#define NVC97E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NVC97E_SET_UPDATE_TIMESTAMP_HI (0x0000034C)
#define NVC97E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NVC97E_SET_INTERLOCK_FLAGS (0x00000370)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#define NVC97E_SET_EXT_PACKET_CONTROL (0x00000398)
#define NVC97E_SET_EXT_PACKET_CONTROL_ENABLE 0:0
#define NVC97E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_EXT_PACKET_CONTROL_LOCATION 4:4
#define NVC97E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000)
#define NVC97E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001)
#define NVC97E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8
#define NVC97E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000)
#define NVC97E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001)
#define NVC97E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12
#define NVC97E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000)
#define NVC97E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001)
#define NVC97E_SET_EXT_PACKET_CONTROL_SIZE 27:16
#define NVC97E_SET_EXT_PACKET_DATA (0x0000039C)
#define NVC97E_SET_EXT_PACKET_DATA_DB0 7:0
#define NVC97E_SET_EXT_PACKET_DATA_DB1 15:8
#define NVC97E_SET_EXT_PACKET_DATA_DB2 23:16
#define NVC97E_SET_EXT_PACKET_DATA_DB3 31:24
#define NVC97E_SET_FMT_COEFFICIENT_C00 (0x00000400)
#define NVC97E_SET_FMT_COEFFICIENT_C00_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C01 (0x00000404)
#define NVC97E_SET_FMT_COEFFICIENT_C01_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C02 (0x00000408)
#define NVC97E_SET_FMT_COEFFICIENT_C02_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C03 (0x0000040C)
#define NVC97E_SET_FMT_COEFFICIENT_C03_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C10 (0x00000410)
#define NVC97E_SET_FMT_COEFFICIENT_C10_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C11 (0x00000414)
#define NVC97E_SET_FMT_COEFFICIENT_C11_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C12 (0x00000418)
#define NVC97E_SET_FMT_COEFFICIENT_C12_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C13 (0x0000041C)
#define NVC97E_SET_FMT_COEFFICIENT_C13_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C20 (0x00000420)
#define NVC97E_SET_FMT_COEFFICIENT_C20_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C21 (0x00000424)
#define NVC97E_SET_FMT_COEFFICIENT_C21_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C22 (0x00000428)
#define NVC97E_SET_FMT_COEFFICIENT_C22_VALUE 20:0
#define NVC97E_SET_FMT_COEFFICIENT_C23 (0x0000042C)
#define NVC97E_SET_FMT_COEFFICIENT_C23_VALUE 20:0
#define NVC97E_SET_ILUT_CONTROL (0x00000440)
#define NVC97E_SET_ILUT_CONTROL_INTERPOLATE 0:0
#define NVC97E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC97E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC97E_SET_ILUT_CONTROL_MIRROR 1:1
#define NVC97E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC97E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC97E_SET_ILUT_CONTROL_MODE 3:2
#define NVC97E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVC97E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVC97E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVC97E_SET_ILUT_CONTROL_SIZE 18:8
#define NVC97E_SET_CSC00CONTROL (0x0000045C)
#define NVC97E_SET_CSC00CONTROL_ENABLE 0:0
#define NVC97E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_CSC00COEFFICIENT_C00 (0x00000460)
#define NVC97E_SET_CSC00COEFFICIENT_C00_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C01 (0x00000464)
#define NVC97E_SET_CSC00COEFFICIENT_C01_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C02 (0x00000468)
#define NVC97E_SET_CSC00COEFFICIENT_C02_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C03 (0x0000046C)
#define NVC97E_SET_CSC00COEFFICIENT_C03_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C10 (0x00000470)
#define NVC97E_SET_CSC00COEFFICIENT_C10_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C11 (0x00000474)
#define NVC97E_SET_CSC00COEFFICIENT_C11_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C12 (0x00000478)
#define NVC97E_SET_CSC00COEFFICIENT_C12_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C13 (0x0000047C)
#define NVC97E_SET_CSC00COEFFICIENT_C13_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C20 (0x00000480)
#define NVC97E_SET_CSC00COEFFICIENT_C20_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C21 (0x00000484)
#define NVC97E_SET_CSC00COEFFICIENT_C21_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C22 (0x00000488)
#define NVC97E_SET_CSC00COEFFICIENT_C22_VALUE 20:0
#define NVC97E_SET_CSC00COEFFICIENT_C23 (0x0000048C)
#define NVC97E_SET_CSC00COEFFICIENT_C23_VALUE 20:0
#define NVC97E_SET_CSC0LUT_CONTROL (0x000004A0)
#define NVC97E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0
#define NVC97E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC97E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC97E_SET_CSC0LUT_CONTROL_MIRROR 1:1
#define NVC97E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC97E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC97E_SET_CSC0LUT_CONTROL_ENABLE 4:4
#define NVC97E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_CSC01CONTROL (0x000004BC)
#define NVC97E_SET_CSC01CONTROL_ENABLE 0:0
#define NVC97E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_CSC01COEFFICIENT_C00 (0x000004C0)
#define NVC97E_SET_CSC01COEFFICIENT_C00_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C01 (0x000004C4)
#define NVC97E_SET_CSC01COEFFICIENT_C01_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C02 (0x000004C8)
#define NVC97E_SET_CSC01COEFFICIENT_C02_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C03 (0x000004CC)
#define NVC97E_SET_CSC01COEFFICIENT_C03_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C10 (0x000004D0)
#define NVC97E_SET_CSC01COEFFICIENT_C10_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C11 (0x000004D4)
#define NVC97E_SET_CSC01COEFFICIENT_C11_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C12 (0x000004D8)
#define NVC97E_SET_CSC01COEFFICIENT_C12_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C13 (0x000004DC)
#define NVC97E_SET_CSC01COEFFICIENT_C13_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C20 (0x000004E0)
#define NVC97E_SET_CSC01COEFFICIENT_C20_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C21 (0x000004E4)
#define NVC97E_SET_CSC01COEFFICIENT_C21_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C22 (0x000004E8)
#define NVC97E_SET_CSC01COEFFICIENT_C22_VALUE 20:0
#define NVC97E_SET_CSC01COEFFICIENT_C23 (0x000004EC)
#define NVC97E_SET_CSC01COEFFICIENT_C23_VALUE 20:0
#define NVC97E_SET_TMO_CONTROL (0x00000500)
#define NVC97E_SET_TMO_CONTROL_INTERPOLATE 0:0
#define NVC97E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC97E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC97E_SET_TMO_CONTROL_SAT_MODE 3:2
#define NVC97E_SET_TMO_CONTROL_SIZE 18:8
#define NVC97E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508)
#define NVC97E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16
#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C)
#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24
#define NVC97E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510)
#define NVC97E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0
#define NVC97E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16
#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514)
#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24
#define NVC97E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518)
#define NVC97E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0
#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C)
#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24
#define NVC97E_SET_CSC10CONTROL (0x0000053C)
#define NVC97E_SET_CSC10CONTROL_ENABLE 0:0
#define NVC97E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_CSC10COEFFICIENT_C00 (0x00000540)
#define NVC97E_SET_CSC10COEFFICIENT_C00_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C01 (0x00000544)
#define NVC97E_SET_CSC10COEFFICIENT_C01_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C02 (0x00000548)
#define NVC97E_SET_CSC10COEFFICIENT_C02_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C03 (0x0000054C)
#define NVC97E_SET_CSC10COEFFICIENT_C03_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C10 (0x00000550)
#define NVC97E_SET_CSC10COEFFICIENT_C10_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C11 (0x00000554)
#define NVC97E_SET_CSC10COEFFICIENT_C11_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C12 (0x00000558)
#define NVC97E_SET_CSC10COEFFICIENT_C12_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C13 (0x0000055C)
#define NVC97E_SET_CSC10COEFFICIENT_C13_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C20 (0x00000560)
#define NVC97E_SET_CSC10COEFFICIENT_C20_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C21 (0x00000564)
#define NVC97E_SET_CSC10COEFFICIENT_C21_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C22 (0x00000568)
#define NVC97E_SET_CSC10COEFFICIENT_C22_VALUE 20:0
#define NVC97E_SET_CSC10COEFFICIENT_C23 (0x0000056C)
#define NVC97E_SET_CSC10COEFFICIENT_C23_VALUE 20:0
#define NVC97E_SET_CSC1LUT_CONTROL (0x00000580)
#define NVC97E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0
#define NVC97E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC97E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC97E_SET_CSC1LUT_CONTROL_MIRROR 1:1
#define NVC97E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC97E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC97E_SET_CSC1LUT_CONTROL_ENABLE 4:4
#define NVC97E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_CSC11CONTROL (0x0000059C)
#define NVC97E_SET_CSC11CONTROL_ENABLE 0:0
#define NVC97E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_CSC11COEFFICIENT_C00 (0x000005A0)
#define NVC97E_SET_CSC11COEFFICIENT_C00_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C01 (0x000005A4)
#define NVC97E_SET_CSC11COEFFICIENT_C01_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C02 (0x000005A8)
#define NVC97E_SET_CSC11COEFFICIENT_C02_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C03 (0x000005AC)
#define NVC97E_SET_CSC11COEFFICIENT_C03_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C10 (0x000005B0)
#define NVC97E_SET_CSC11COEFFICIENT_C10_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C11 (0x000005B4)
#define NVC97E_SET_CSC11COEFFICIENT_C11_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C12 (0x000005B8)
#define NVC97E_SET_CSC11COEFFICIENT_C12_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C13 (0x000005BC)
#define NVC97E_SET_CSC11COEFFICIENT_C13_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C20 (0x000005C0)
#define NVC97E_SET_CSC11COEFFICIENT_C20_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C21 (0x000005C4)
#define NVC97E_SET_CSC11COEFFICIENT_C21_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C22 (0x000005C8)
#define NVC97E_SET_CSC11COEFFICIENT_C22_VALUE 20:0
#define NVC97E_SET_CSC11COEFFICIENT_C23 (0x000005CC)
#define NVC97E_SET_CSC11COEFFICIENT_C23_VALUE 20:0
#define NVC97E_SET_CLAMP_RANGE (0x000005D0)
#define NVC97E_SET_CLAMP_RANGE_LOW 15:0
#define NVC97E_SET_CLAMP_RANGE_HIGH 31:16
#define NVC97E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004)
#define NVC97E_SW_RESERVED_VALUE 31:0
#define NVC97E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640)
#define NVC97E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644)
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648)
#define NVC97E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650)
#define NVC97E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654)
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004)
#define NVC97E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688)
#define NVC97E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690)
#define NVC97E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694)
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000)
#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc97e_h

46
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -933,6 +933,16 @@ typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
* The setting must be applied before the GPU is attached.
* NVLINK_BW_MODE is an NOP for non-NVLink GPUs.
*
* [in] mode
* BW mode requested defined as a DRF
* Possible Legacy values that can be set in bits 2:0:
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER
* Link count can be requested on Blackwell+ in bits 7:3
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
@@ -942,11 +952,20 @@ typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
* NV_ERR_IN_USE
*/
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL (0x00U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF (0x01U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN (0x02U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF (0x03U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER (0x04U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LEGACY 2:0
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LINK_COUNT 7:3
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL (0x00U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF (0x01U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN (0x02U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF (0x03U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER (0x04U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT (0x05U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET (0x00U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE (0x01U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU (0x02U)
#define NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE (0x286U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x86U)
@@ -960,9 +979,23 @@ typedef struct NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS {
*
* This command is used to get NVLINK bandwidth for power saving
*
* The setting must be applied before the GPU is attached.
* NVLINK_BW_MODE is an NOP for non-NVLink GPUs.
*
* [out] mode
* BW mode currently set for the GPUs on the system.
* Possible values are:
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER
* [out] bwModeScope
* Scope of the bw mode setting on the system.
* Possible values are:
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE
* NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
@@ -977,6 +1010,7 @@ typedef struct NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS {
typedef struct NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS {
NvU8 mode;
NvU8 bwModeScope;
} NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS;
/*

132
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -122,6 +122,12 @@ typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS {
NvU32 officialChangelistNumber;
} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS;
typedef enum NV0000_CTRL_SYSTEM_SH_SOC_TYPE {
NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = 0,
NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = 1,
} NV0000_CTRL_SYSTEM_SH_SOC_TYPE;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO
*
@@ -203,6 +209,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS {
* Silicon stepping
* bCCEnabled
* Confidentail compute enabled/disabled state
* selfHostedSocType
* SoC type NV0000_CTRL_SYSTEM_SH_SOC_TYPE* in case of self hosted systems
*
* Possible status values returned are:
* NV_OK
@@ -213,20 +221,21 @@ typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS {
#define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
NvU32 type; /* processor type */
NvU32 capabilities; /* processor caps */
NvU32 clock; /* processor speed (MHz) */
NvU32 L1DataCacheSize; /* L1 dcache size (KB) */
NvU32 L2DataCacheSize; /* L2 dcache size (KB) */
NvU32 dataCacheLineSize; /* L1 dcache bytes/line */
NvU32 numLogicalCpus; /* logial processor cnt */
NvU32 numPhysicalCpus; /* physical processor cnt*/
NvU8 name[52]; /* embedded cpu name */
NvU32 family; /* Vendor defined Family and Extended Family combined */
NvU32 model; /* Vendor defined Model and Extended Model combined */
NvU8 stepping; /* Silicon stepping */
NvU32 coresOnDie; /* cpu cores per die */
NvBool bCCEnabled; /* CC enabled on cpu */
NvU32 type; /* processor type */
NvU32 capabilities; /* processor caps */
NvU32 clock; /* processor speed (MHz) */
NvU32 L1DataCacheSize; /* L1 dcache size (KB) */
NvU32 L2DataCacheSize; /* L2 dcache size (KB) */
NvU32 dataCacheLineSize; /* L1 dcache bytes/line */
NvU32 numLogicalCpus; /* logial processor cnt */
NvU32 numPhysicalCpus; /* physical processor cnt*/
NvU8 name[52]; /* embedded cpu name */
NvU32 family; /* Vendor defined Family and Extended Family combined */
NvU32 model; /* Vendor defined Model and Extended Model combined */
NvU8 stepping; /* Silicon stepping */
NvU32 coresOnDie; /* cpu cores per die */
NvBool bCCEnabled; /* CC enabled on cpu */
NV0000_CTRL_SYSTEM_SH_SOC_TYPE selfHostedSocType; /* SoC type in case of self hosted systems */
} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS;
// Macros for CPU family information
@@ -2108,6 +2117,31 @@ typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
#define NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE 1U
#define NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE 32U
#define NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID (0x48U)
typedef struct NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT {
/* Battery state of charge threshold (percent 0-100) */
NvU8 batteryStateOfChargePercent;
/* Long Timescale Battery current limit (milliamps) */
NvU32 batteryCurrentLimitmA;
/* Rest of system reserved power (milliwatts) */
NvU32 restOfSytemReservedPowermW;
/* Min CPU TDP (milliwatts) */
NvU32 minCpuTdpmW;
/* Max CPU TDP (milliwatts) */
NvU32 maxCpuTdpmW;
/* Short Timescale Battery current limit (milliamps) */
NvU32 shortTimescaleBatteryCurrentLimitmA;
} NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT;
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
@@ -2200,41 +2234,71 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
} filterParam;
/* Reserved */
NvU16 filterReserved;
NvU16 filterReserved;
/* Controller Type Dynamic Boost Controller */
NvBool bIsBoostController;
NvBool bIsBoostController;
/* Increase power limit ratio */
NvU16 incRatio;
NvU16 incRatio;
/* Decrease power limit ratio */
NvU16 decRatio;
NvU16 decRatio;
/* Dynamic Boost Controller DC Support */
NvBool bSupportBatt;
NvBool bSupportBatt;
/* CPU type(Intel/AMD) */
NvU8 cpuType;
NvU8 cpuType;
/* GPU type(Nvidia) */
NvU8 gpuType;
NvU8 gpuType;
/* System Power Table info index */
NvU32 sysPwrIndex;
/* System Power Table get table limits */
NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT sysPwrGetInfo[NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE];
/*
* Does this version of the system power limits table support TSP -> table
* version 2.0 and later should set this to true
*/
NvBool bIsTspSupported;
/*
* Stores the System Power Limits (Battery State of Charge aka BSOC) table version implemented by the SBIOS
*
*/
NvU8 sysPwrLimitsTableVersion;
/* SYSPWRLIMIT class types */
NvU32 type;
/* CPU TDP Limit to be set (milliwatts) */
NvU32 cpuTdpmw;
} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
/* Define the filter types */
#define CONTROLLER_FILTER_TYPE_EMWA 0U
#define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U
#define CONTROLLER_FILTER_TYPE_EMWA 0U
#define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U
/* Valid NVPCF subfunction case */
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U
/* NVPCF subfunction to get the static data tables */
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U
/* NVPCF subfunction to get the system power limits table */
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE 5U
/* NVPCF subfunction to change the CPU's TDP limit */
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE 6U
/* Valid NVPCF subfunction ids */
#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000)
#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002)
#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000)
#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002)
/*
* Defines for get supported sub functions bit fields
@@ -2246,10 +2310,12 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/*!
* Config DSM 2x version specific defines
*/
#define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE (0x00000008)
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL (0x00000009)
/*!
* Defines the max buffer size for config
@@ -2268,7 +2334,7 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU)

9
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
View File

@@ -37,6 +37,15 @@
#include "class/cl0000.h"
#include "nv_vgpu_types.h"
/* DRF macros for OBJGPU::gpuId */
#define NV0000_BUSDEVICE_DOMAIN 31:16
#define NV0000_BUSDEVICE_BUS 15:8
#define NV0000_BUSDEVICE_DEVICE 7:0
#define GPU_32_BIT_ID_DECODE_DOMAIN(gpuId) (NvU16)DRF_VAL(0000, _BUSDEVICE, _DOMAIN, gpuId);
#define GPU_32_BIT_ID_DECODE_BUS(gpuId) (NvU8) DRF_VAL(0000, _BUSDEVICE, _BUS, gpuId);
#define GPU_32_BIT_ID_DECODE_DEVICE(gpuId) (NvU8) DRF_VAL(0000, _BUSDEVICE, _DEVICE, gpuId);
/*
* NV0000_CTRL_CMD_VGPU_CREATE_DEVICE
*

35
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -1451,4 +1451,39 @@ typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS {
/*
* NV0073_CTRL_CMD_DFP_SET_FORCE_BLACK_PIXELS
*
* This command is used to force black pixels from postcomp.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* displayId
* DisplayId of the connected display.
*
* bForceBlackPixels
* To enable or disable black pixel generation.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV0073_CTRL_CMD_DFP_SET_FORCE_BLACK_PIXELS (0x731179U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS_MESSAGE_ID (0x79U)
typedef struct NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 head;
NvBool bForceBlack;
} NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS;
/* _ctrl0073dfp_h_ */

52
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -804,39 +804,33 @@ typedef struct NV0073_CTRL_DP_CSTM {
#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0
#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM8 7:0
/*
* NV0073_CTRL_DP_TESTPATTERN
*
* This structure specifies the possible test patterns available in display port.
* This structure specifies the possible test patterns available in display port,
* and parameters for Square pattern.
*
*/
typedef struct NV0073_CTRL_DP_TESTPATTERN {
NvU32 testPattern;
} NV0073_CTRL_DP_TESTPATTERN;
#define NV0073_CTRL_DP_TESTPATTERN_DATA 4:0
#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP (0x00000002U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_7 (0x00000003U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM (0x00000004U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3 (0x00000006U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING1 (0x00000007U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING2 (0x00000008U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING3 (0x00000009U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING4 (0x0000000AU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT1 (0x0000000BU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS1 (0x0000000CU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS2 (0x0000000DU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_9 (0x0000000EU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_11 (0x0000000FU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_15 (0x00000010U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_23 (0x00000011U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_31 (0x00000012U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_SQNUM (0x00000013U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM_264 (0x00000014U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA 4:0
#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP (0x00000002U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_7 (0x00000003U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM (0x00000004U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3 (0x00000006U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING1 (0x00000007U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING2 (0x00000008U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING3 (0x00000009U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING4 (0x0000000AU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT1 (0x0000000BU)
/*
* NV0073_CTRL_CMD_DP_SET_TESTPATTERN
@@ -868,10 +862,8 @@ typedef struct NV0073_CTRL_DP_TESTPATTERN {
* laneMask
* This parameter specifies the bit mask of DP lanes on which test
* pattern is to be applied.
* lower
* This parameter specifies the lower 64 bits of the CSTM test pattern
* upper
* This parameter specifies the upper 16 bits of the CSTM test pattern
* cstm
* This parameter specifies the all the bits for CSTM test pattern.
* bIsHBR2
* This Boolean parameter is set to TRUE if HBR2 compliance test is
* being performed.
@@ -2774,8 +2766,8 @@ typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL 0x00000002
/* valid state values */
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_DISABLE 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_ENABLE 0x00000001
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_DISABLE 0x00000001
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_AUTONOMOUS 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS_MESSAGE_ID (0x86U)

9
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -328,10 +328,7 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS {
NvU32 ddcPortId;
} NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS;
#define NV0073_CTRL_SPECIFIC_I2C_PORT_NONE (0x0U)
#define NV0073_CTRL_SPECIFIC_I2C_PORT_NONE (0x0U)
/*
* NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA
@@ -394,10 +391,10 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS {
*
*/
#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */
/* maximum number of connectors */
#define NV0073_CTRL_MAX_CONNECTORS 4U
#define NV0073_CTRL_MAX_CONNECTORS 4U
#define NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID (0x50U)

316
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1603,15 +1603,30 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS {
* NV_ERR_GENERIC
*/
#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730143U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH
*
* This command is identical to
* NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH, except that it routes to
* Physical RM, and is for internal RM use. Clients are advised to use
* NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH instead.
*/
#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x43U)
#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730143U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH (0x730157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */
typedef struct NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS {
typedef struct NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE {
NvU32 subDeviceInstance;
NvU32 averageBandwidthKBPS;
NvU32 floorBandwidthKBPS;
} NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS;
} NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE;
#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x43U)
typedef NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS;
#define NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x57U)
typedef NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS;
/*
* NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS
@@ -2013,5 +2028,298 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS {
NvBool bMap;
} NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO
*
* Fetches the LoadV Counter information from corresponding registers.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayId
* DisplayId of the panel for which we are going to read loadv info
* Possible status values returned are:
* counterValue
* Counts number of frames that have been procesed or synchronized with display
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO (0x730154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS_MESSAGE_ID (0x54U)
typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 counterValue;
} NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS;
/*!
* @brief Defines Display Low Power feature IDs
*
* Following defines specifies unique IDs to identify Display Power saving feature.
*/
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_INVALID 0x0000
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_ALPM 0x0001
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_HUBCLK 0x0002
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_RISCV0CLK 0x0003
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_DISPCLK 0x0004
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_POSTRG_CLKS 0x0005
// Parameter/characteristics of Display ALPM
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_SUPPORTED 0x0001
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_ENABLED 0x0002
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_TYPE_AUX_LESS 0x0003
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_ENGAGE_TIME 0x0004
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_ENTRY_COUNT 0x0005
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_EXIT_COUNT 0x0006
/*!
* @brief Parameter/characteristics of hubclk, dispclk, riscv0clk and Post-RG clock Switching
*
* Following are the Parameter/characteristics for of hubclk, dispclk, riscv0clk and
* Post-RG clock Switching
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_INVALID (0x0000)
/*!
* Property specifies if Clock Switching is supported
* or not. This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk.
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_SUPPORT (0x0001)
/*!
* Property specifies if Clock Switching is enabled or not.
* This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk.
* (This property allows Get and Set operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_ENABLED (0x0002)
/*!
* Property specifies the time(us) for which the specified clock was in Safe mode.
* This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_SAFE_TIME_US (0x0003)
/*!
* Property specifies the time(us) for which the specified clock was in Alternate mode.
* This property is only applicable to riscv0clk.
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_ALTERNATE_TIME_US (0x0004)
/*!
* Property specifies if the specified clock is forced to Function mode or not.
* This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk.
* (This property allows Get and Set operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_FORCE_FUNCTION (0x0005)
/*!
* Property specifies if there was an error when the specified clock is being switched
* to safe mode but switch didn't happen in programmed time.
* This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk.
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_SAFE_ERROR (0x0006)
/*!
* Property specifies if there was an error when the specified clock is being switched
* to function mode but switch didn't happen in programmed time.
* This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk.
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_UNSAFE_ERROR (0x0007)
/*!
* Property specifies if there was an error when Riscv0clk clock is being switched
* to alternate mode but switch didn't happen in programmed time.
* This property is only applicable to riscv0clk.
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_ALTER_ERROR (0x0008)
/*!
* Property specifies if there was an error when the Riscv0clk clock is being switched to
* function mode but switch didn't happen in programmed time.
* This property is only applicable to riscv0clk.
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_UNALTER_ERROR (0x0009)
/*!
* Property specifies current state of the specified clock
* i.e. Safe or Function or Alternate
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_STATUS (0x0010)
/*!
* @brief Structure to identify display low power feature
*
* Structure to get/set feature Id, It has two fields
* FeatureID[In] : Feature Identifier
* SubFeatureID[In] : If Any Subfeature associated to Feature
*
* In general, Power saving feature is identify by featureId and SubFeature.
* Add enum in this structure in case some specific power feature needs
* additional fields. "Union" should follow XAPI standards.
*/
typedef struct NV0073_CTRL_DISP_LPWR_FEATURE {
NvU16 featureId;
NvU16 subfeatureId;
} NV0073_CTRL_DISP_LPWR_FEATURE;
/*!
* @brief Parameter structure
*
* Structure to get/set parameter/characteristic. Each parameter has 3 field
* 1) ID [In] : Parameter Identifier
* 2) Flag [In/Out] : Flags
* 3) Value [In/Out] : Value of parameter
*
* Add enum in this structure in case we need to additional fields for some
* special parameters.
*/
typedef struct NV0073_CTRL_DISP_LPWR_PARAMETER {
NvU16 paramId;
NvU16 flag;
NvU32 val;
} NV0073_CTRL_DISP_LPWR_PARAMETER;
/*!
* @brief Flags for PARAMETER
*
* SUCCEED:
* - Get/Set param call is succeed or not.
* - Get Param call for given parameter succeed means RMCtrl retrieved valid
* value for this parameter.
* - Set Param call for given parameter succeed means RMCtrl set value of this
* parameter.
*
* BLOCKING:
* - Defines whether RM Ctrl call is blocking/non-blocking for given parameter.
*/
#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_FLAG_SUCCEED 0:0
#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_FLAG_SUCCEED_NO 0x0
#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_FLAG_SUCCEED_YES 0x1
/*!
* @brief Defines all information required to get/set the parameter for given
* display low power feature.
*/
typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER {
NV0073_CTRL_DISP_LPWR_FEATURE feature;
NV0073_CTRL_DISP_LPWR_PARAMETER param;
} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER;
// Max size of FEATURE_PARAMETER structure for RMCtrl NV0073_CTRL_DISP_LPWR_GET/SET
#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE 64
/*
* NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_GET
*
* This command retrieves parameters/characteristics of power features. It can
* query NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE number of parameters
* in one call. Command provides facility of collecting information on multiple
* power saving features in one call.
*
* Commands returns SUCCESS only when it successfully retrieves value all
* parameter in the list.
*
* listSize
* Number of valid entries in list.
*
* list
* List of parameters. Refer NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER to get
* details about each entry in the list.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_GET (0x730155) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS_MESSAGE_ID (0x55U)
typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS {
NvU32 subDeviceInstance;
NvU32 listSize;
NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE];
} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS;
/*
* NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_SET
*
* This command sets parameters/characteristics of power features. It can
* set NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE number of parameters
* in one call. Command provides facility of setting parameters for multiple
* power saving features in one call.
*
* Commands returns SUCCESS only when it successfully sets value of all
* parameter in the list.
*
* listSize
* Number of valid entries in list.
*
* list
* List of parameters. Refer NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER to get
* details about each entry in the list.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_SET (0x730156) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS_MESSAGE_ID (0x56U)
typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS {
NvU32 subDeviceInstance;
NvU32 listSize;
NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE];
} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR
*
* This command is used to Notify RM about DRR feature. RM uses this
* notification to account MSCG WARs for Turing and Ampere HW bugs.
*
* subDeviceInstance (in)
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation
* should be directed.
* presentDurationUs (in)
* This parameter inputs the presentDurationUs of the active display.
* bEnableDrr
* If it is true, it means that DRR is enabled from DD side.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR (0x730158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID (0x58U)
typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
NvU32 subDeviceInstance;
NvU32 presentDurationUs;
NvBool bEnableDrr;
} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS;
/* _ctrl0073system_h_ */

17
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h → src/common/sdk/nvidia/inc/ctrl/ctrl0076.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,10 +23,19 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080clk.finn
// Source file: ctrl/ctrl0076.finn
//
/*
* NV0076_CTRL_NOTIFY_CONSOLE_DISABLED
*
* This command signals to the resource manager that the operating system's
* legacy framebuffer console was disabled and that the underlying BAR mapping
* can be freed.
*/
#define NV0076_CTRL_CMD_NOTIFY_CONSOLE_DISABLED (0x760101) /* finn: Evaluated from "(FINN_NV01_FRAMEBUFFER_CONSOLE_INTERFACE_ID << 8) | 1" */

1
src/common/sdk/nvidia/inc/ctrl/ctrl0080.h
View File

@@ -33,7 +33,6 @@
#include "ctrl0080/ctrl0080bif.h"
#include "ctrl0080/ctrl0080gpu.h"
#include "ctrl0080/ctrl0080clk.h"
#include "ctrl0080/ctrl0080dma.h"
#include "ctrl0080/ctrl0080gr.h"
#include "ctrl0080/ctrl0080cipher.h"

24
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -73,28 +73,6 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE 0x8
/*
* NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR
*
* baseDmaSysmemAddr
* This parameter represents the base DMA address for sysmem which will be
* added to all DMA accesses issued by GPU. Currently GPUs do not support 64-bit physical address,
* hence if sysmem is greater than max GPU supported physical address width, this address
* will be non-zero
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 baseDmaSysmemAddr, 8);
} NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS;
/*
* NV0080_CTRL_BIF_SET_ASPM_FEATURE
*
@@ -105,7 +83,7 @@ typedef struct NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS {
* NV_OK
*/
#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID (0x4U)

49
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
View File

@@ -91,54 +91,7 @@ typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS {
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40
/* size in bytes of fifo caps table */
#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2
/*
* NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS
*
* This command allows the caller to request that a set of channels
* be added to the runlist.
*
* fifoStartChannelListSize
* Size of the fifoStartChannelList. The units are in entries, not
* bytes.
* fifoStartChannelList
* This will be a list of NV0080_CTRL_FIFO_CHANNEL data structures,
* one for each channel that is to be started.
* channelHandle
* deprecated
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
/*
* hChannel
* This is the handle to the channel that is scheduled to be started.
*/
typedef struct NV0080_CTRL_FIFO_CHANNEL {
NvHandle hChannel;
} NV0080_CTRL_FIFO_CHANNEL;
#define NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS (0x801705) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS {
NvU32 fifoStartChannelListCount;
NvHandle channelHandle[8];
NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8);
} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS;
#define NV0080_CTRL_FIFO_ENGINE_ID_GRAPHICS (0x00000000)
#define NV0080_CTRL_FIFO_ENGINE_ID_MPEG (0x00000001)
#define NV0080_CTRL_FIFO_ENGINE_ID_MOTION_ESTIMATION (0x00000002)
#define NV0080_CTRL_FIFO_ENGINE_ID_VIDEO (0x00000003)
#define NV0080_CTRL_FIFO_ENGINE_ID_BITSTREAM (0x00000004)
#define NV0080_CTRL_FIFO_ENGINE_ID_ENCRYPTION (0x00000005)
#define NV0080_CTRL_FIFO_ENGINE_ID_FGT (0x00000006)
#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2
/*
* NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -313,8 +313,6 @@ typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS {
NvBool isGridBuild;
} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE
*

50
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
View File

@@ -146,6 +146,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
* NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
*
* This command returns the mapping of PCE's for the given LCE.
* The pceMask is local to the CE shim that ceEngineType belongs to.
*
* ceEngineType
* This parameter specifies the copy engine type
@@ -159,12 +160,6 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
/*
* The pceMask is local to the CE shim that ceEngineType belongs to.
*/
#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U)
@@ -236,18 +231,6 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
/*
* This command updates the PCE-LCE mappings for one CE shim. On
* GPUs with multiple CE shims, this interface must be called for
* each shim.
*
* shimInstance [IN]
* Specify which CE shim instance to operate on.
*/
#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
@@ -270,13 +253,9 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
*
* An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be
* set in stubbedCeMask.
*/
/*
*
* This function operates on all CE shims.
*/
#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)
@@ -360,7 +339,6 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS;
/*
* NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO
*
@@ -439,11 +417,15 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3,
NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4,
NV2080_CTRL_CE_LCE_TYPE_C2C = 5,
NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = 6,
NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = 7,
NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = 8,
NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = 9,
} NV2080_CTRL_CE_LCE_TYPE;
/*
* NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE
*
*
* This command queries the PCE config required for the specified LCE type.
*
* [in] lceType
@@ -497,6 +479,24 @@ typedef struct NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS {
NvU32 shimInstance;
} NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS;
/*
* NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED
*
* This command returns whether a given global LCE index is enabled for decomp workloads.
* It has to be given a global LCE index (cannot support shim local LCE ID)
*
* [in] lceIndex
* [out] bDecompEnabled
* Returns NV_TRUE if LCE is enabled for decompression, else returns NV_FALSE
*/
#define NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED (0x20802a12) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS {
NvU32 lceIndex;
NvBool bDecompEnabled;
} NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS;
/* _ctrl2080ce_h_ */

43
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -39,36 +39,9 @@
/*
* NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
*
* sramLastClearedTimestamp [out]
* dramLastClearedTimestamp [out]
* unix-epoch based timestamp. These fields indicate when the error counters
* were last cleared by the user.
*
* sramErrorCounts [out]
* dramErrorCounts [out]
* Aggregate error counts for SRAM and DRAM
*/
#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
NvU32 sramLastClearedTimestamp;
NvU32 dramLastClearedTimestamp;
NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8);
} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_ECC_GET_ECI_COUNTERS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS
*
* sramParityUncorrectedUnique [out]
* sramSecDedUncorrectedUnique [out]
* sramCorrectedTotal [out]
* sramCorrectedUnique [out]
* dramUncorrectedTotal [out]
* dramCorrectedTotal [out]
* Aggregate error counts for SRAM and DRAM.
@@ -88,12 +61,12 @@ typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
* Boolean flag which is set if SRAM error threshold was exceeded
*/
#define NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID (0x1U)
#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8);
NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8);
NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotal, 8);
NV_DECLARE_ALIGNED(NvU64 sramCorrectedUnique, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8);
@@ -106,7 +79,7 @@ typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8);
NvBool sramErrorThresholdExceeded;
} NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS;
} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
/*
* NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
@@ -124,9 +97,9 @@ typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
* dramUncTot [out]:
* total uncorrectable DRAM error count
*/
#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803402U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x2U)
#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8);

291
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -481,33 +481,6 @@ typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuVirtAddress, 8);
} NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS;
/*
* Note: Returns Zeros if no System carveout address info
*
* NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO
*
* This command returns FB carveout address space information
*
* StartAddr
* Returns the system memory address of the start of carveout space.
* SpaceSize
* Returns the size of carveout space.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO (0x2080130bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO {
NV_DECLARE_ALIGNED(NvU64 StartAddr, 8);
NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8);
} NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO;
/*
* NV2080_CTRL_FB_CMD_GET_CALIBRATION_LOCK_FAILED
*
@@ -680,161 +653,6 @@ typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS {
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO (0x00000000U)
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES (0x00000001U)
/*
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2 instead)
*
* These commands access the cache allocation policy on a specific
* engine, if supported.
*
* engine
* Specifies the target engine. Possible values are defined in
* NV2080_ENGINE_TYPE.
* allocPolicy
* Specifies the read/write allocation policy of the cache on the specified
* engine. Possible values are defined in
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS and
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES.
*
*/
typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS {
NvU32 engine;
NvU32 allocPolicy;
} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS;
/* valid values for allocPolicy */
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY
*
* This command is deprecated.
* Use NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 instead.
*
* This command sets the state of the cache allocation policy on a specific
* engine, if supported.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0xFU)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS;
/*
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM
*
* These commands access the cache allocation policy on a specific
* client, if supported.
*
* count
* Specifies the number of entries in entry.
* entry
* Specifies an array of allocation policy entries.
*
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY
*
* clients
* Specifies the target client. Possible values are defined in
* NV2080_CLIENT_TYPE_*.
* allocPolicy
* Specifies the read/write allocation policy of the cache on the specified
* engine. Possible values are defined in
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS and
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES.
*
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE
*
* Specifies the maximum number of allocation policy entries allowed
*/
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE 11U
typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY {
NvU32 client;
NvU32 allocPolicy;
} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY;
typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
NvU32 count;
NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY entry[NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE];
} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
/* valid values for allocPolicy */
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS 0:0
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_DISABLE (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ENABLE (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW 1:1
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES 2:2
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_DISABLE (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ENABLE (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW 3:3
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2
*
* This command sets the state of the cache allocation policy on a specific
* engine, if supported.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x18U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead)
*
* This command gets the state of the cache allocation policy on a specific
* engine, if supported.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0x12U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2
*
* This command gets the state of the cache allocation policy on a specific
* engine, if supported.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x19U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
/*
* NV2080_CTRL_CMD_FB_IS_KIND
*
@@ -908,7 +726,7 @@ typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_C
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U)
@@ -985,65 +803,6 @@ typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS {
#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED (0x00000002U)
#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE (0x00000003U)
/*
* NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY
*
* These commands access the cache promotion policy on a specific
* engine, if supported by the hardware.
*
* Cache promotion refers to the GPU promoting a memory read to a larger
* size to preemptively fill the cache so future reads to nearby memory
* addresses will hit in the cache.
*
* engine
* Specifies the target engine. Possible values are defined in
* NV2080_ENGINE_TYPE.
* promotionPolicy
* Specifies the promotion policy of the cache on the specified
* engine. Possible values are defined by
* NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_*. These values are in terms
* of the hardware cache line size.
*
*/
typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS {
NvU32 engine;
NvU32 promotionPolicy;
} NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS;
/* valid values for promotionPolicy */
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_NONE (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_QUARTER (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_HALF (0x00000002U)
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_FULL (0x00000003U)
/*
* NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY
*
* This command sets the cache promotion policy on a specific engine, if
* supported by the hardware.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY (0x20801316U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x16" */ // Deprecated, removed form RM
/*
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY
*
* This command gets the cache promotion policy on a specific engine, if
* supported by the hardware.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY (0x20801317U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x17" */ // Deprecated, removed form RM
/*
* NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO
*
@@ -1086,9 +845,9 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U
typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
@@ -2391,6 +2150,21 @@ typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS {
NvU32 sysl2LtcEnMask;
} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK.
*/
typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS {
/*!
* [IN]: physical/local SYS index.
*/
NvU32 sysIdx;
/*!
* [OUT]: physical/local lts mask.
* Note: this lts mask should be flattened out within a sys chiplet
*/
NV_DECLARE_ALIGNED(NvU64 sysl2LtsEnMask, 8);
} NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PAC_MASK.
*/
@@ -2456,6 +2230,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS {
#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU
#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK 0xFU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK 0x11U
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NvU16 queryType;
@@ -2479,6 +2254,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS pac;
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS sysl2Lts, 8);
} queryParams;
} NV2080_CTRL_FB_FS_INFO_QUERY;
@@ -2884,4 +2660,31 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_OWNER_INFO fbBlockInfo[NV2080_CTRL_CMD_FB_STATS_MAX_OWNER], 8);
} NV2080_CTRL_CMD_FB_STATS_GET_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO
*
* This command returns the GPU static BAR1 Info
* This is for general P2P DMA. NV50_P2P is for GPU P2P.
*
* @params [OUT] NvBool bStaticBar1Enabled:
* This field indicates the static BAR1 mode is enabled. All the following fields are valid
* only if static BAR1 mode is enabled.
* @params [OUT] NvU64 staticBar1Size:
* This field indicates the size of the static BAR1.
*
* Possible status values returned are
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO (0x20801354U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID (0x54U)
typedef struct NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS {
NvBool bStaticBar1Enabled;
NV_DECLARE_ALIGNED(NvU64 staticBar1Size, 8);
} NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS;
/* _ctrl2080fb_h_ */

101
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -114,10 +114,7 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
/* valid minor revision extended values */
@@ -1128,7 +1125,10 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001FU)
#define NV2080_CTRL_GPU_ECC_UNIT_GSP (0x0000001DU)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000024U)
@@ -1861,13 +1861,11 @@ typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS {
NvU32 ipVersion;
} NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS;
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U)
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U)
/*
* NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT
@@ -2584,37 +2582,39 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8);
} NV2080_CTRL_GPU_SET_PARTITION_INFO;
#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID
#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU
#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U
#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U
#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU
#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U
#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID
#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU
#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U
#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U
#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU
#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 0x00000006U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 0x00000007U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 8U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 40U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U
// TODO XXX Bug 2657907 Remove these once clients update
#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL))
@@ -4328,11 +4328,11 @@ typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_VF_CAPS
* NV2080_CTRL_CMD_GPU_GET_VF_CAPS
*
* This command will return the MSIX capabilities for virtual function
* Parameters:
*
*
* gfid [IN]
* The GPU function identifier for a given VF BDF
*
@@ -4357,6 +4357,33 @@ typedef struct NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS {
NV2080_VF_MSIX_CAPS vfMsixCap;
} NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION
*
* Gets the recovery action needed for the device after a failure.
*
* action [OUT]
* Returns the recovery action needed.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION (0x208001b2U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_GPU_RECOVERY_ACTION {
NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = 0,
NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = 1,
NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = 2,
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3,
} NV2080_CTRL_GPU_RECOVERY_ACTION;
#define NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID (0xB2U)
typedef struct NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS {
NV2080_CTRL_GPU_RECOVERY_ACTION action;
} NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS;
/*
* NV2080_CTRL_GPU_GET_FIPS_STATUS
*

28
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -309,7 +309,6 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
@@ -330,7 +329,6 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
@@ -834,7 +832,8 @@ typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5,
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6,
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7,
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 8,
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = 8,
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 9,
} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS;
/*
@@ -1909,4 +1908,27 @@ typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS {
NvU32 numGfxTpc;
} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS;
/*
* NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION
*
* This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine
*
* promoType[IN]
* This parameter specifies what kind of sector promotion to perform
*
*/
#define NV2080_CTRL_CMD_GR_SET_LG_SECTOR_PROMOTION (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE {
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_NONE = 0,
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_64B = 1,
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_128B = 2,
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE;
#define NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID (0x3BU)
typedef struct NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS {
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE promoType;
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS;
/* _ctrl2080gr_h_ */

7
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -87,6 +87,10 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
*
* This command reports the current GSP-RM heap usage statistics.
*
* gfid
* The gfid that's under query: When gfid = 0, it will report the stats of PF.
* Otherwise, it will report stats for RM task's memory consumption associated
* with a given gfid.
* managedSize
* The total size in bytes of the underlying heap. Note that not all memory
* will be allocatable, due to fragmentation and memory allocator/tracking
@@ -125,6 +129,7 @@ typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT {
#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS {
NvU32 gfid;
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8);

554
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -750,8 +750,9 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
NvU32 groupId;
NvU32 ginTargetId;
NvU32 deviceBroadcastPriBase;
NvU32 groupLocalInstanceId;
} NV2080_CTRL_INTERNAL_DEVICE_INFO;
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 512
#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
@@ -1351,6 +1352,12 @@ typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS {
* pbTargetAperture [IN]
* Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM)
*
* channelPBSize [IN]
* Indicates the PushBuffer size requested by client
*
* subDeviceId [IN]
* One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel
* in the pushbuffer stream (via SSDM method)
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
@@ -1365,6 +1372,8 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
NvU32 channelInstance;
NvBool valid;
NvU32 pbTargetAperture;
NvU32 channelPBSize;
NvU32 subDeviceId;
} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
/*!
@@ -4024,36 +4033,46 @@ typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
* NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
*
* This structure provides the params for starting GPU Fabric Probe
*
* tracepointMask[IN]
* - tracepoint selection filter
* bufferAddr[IN]
* - physical address of tracing buffer for VGPU
* bufferSize[IN]
* - size of gsp side logging buffer
* bufferWatermark[IN]
* - entry threshold for GSP to issue RPC of logged entries to kernel RM
* bStart[IN]
* - if true, start tracing. if false, stop tracing.
* flag[IN]
* - indicates which operation to perform
*/
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U)
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID (0xE3U)
typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS {
typedef struct NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
NvU32 bufferSize;
NvU32 bufferWatermark;
NvBool bStart;
} NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS;
NV_DECLARE_ALIGNED(NvU64 bufferAddr, 8);
NvU32 bufferSize;
NvU32 bufferWatermark;
NvU8 flag;
} NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS;
/*!
* Macros for INTERNAL_CONTROL_GSP_TRACE flags for specific operation.
*/
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST 0x00U
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST 0x01U
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP 0x02U
/*
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE
* NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE
*
* This command is used to start GSP-RM trace tool.
* This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
* This command accepts NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES
@@ -4143,7 +4162,26 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS {
NvU32 attribute;
NvU32 value;
} NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR
*
* @brief NVIDIA RTX 5000 (GP180 SKU500) Windows-specific war
* to pull gpio19 (stereo pin) low for bug3362661.
*
* [in] bApplyStereoPinAlwaysHiWar
* If need to driver stereo pin(GPIO19) low(_IO_INPUT)
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID (0xEDU)
typedef struct NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS {
NvBool bApplyStereoPinAlwaysHiWar;
} NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR (0x20800aed) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM
*
@@ -4154,7 +4192,7 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS {
*
* @return NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID (0x79U)
@@ -4162,4 +4200,490 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS {
NvU32 maxHshubs;
} NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_MODE
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS {
NvU32 rasterSyncDecodeMode;
} NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE (0x20800a14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS
*
* This is an internal command sent from kernel-RM to physical-RM to retrieve GPU PF BAR1 SPA
* BAR1 SPA is required for BAR1 mapping in Direct NIC case for DMA(Direct Memory Access) of FB.
*
* spaValue[OUT]
* - BAR1 SPA of GPU PF
*/
#define NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID (0xEEU)
typedef struct NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS {
NV_DECLARE_ALIGNED(NvU64 spaValue, 8);
} NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA (0x20800aee) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER
*
* This command is used to enable RM NVLink enabled peer state.
* Note: This just updates the RM state. To reflect the state in the registers,
* use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER
*
* [in] peerMask
* Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled
* [in] bEnable
* Whether the bit needs to be set or unset
*
* Possible status values returned are:
* NV_OK
* If the USE_NVLINK_PEER bit was enabled successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip, or
* If unsetting USE_NVLINK_PEER bit is not supported
*
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER (0x20800a21U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
NvU32 peerMask;
NvBool bEnable;
} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
/*
* NVLINK Link states
* These should ALWAYS match the nvlink core library defines in nvlink.h
*/
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF 0x00U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS 0x01U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE 0x02U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT 0x03U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY 0x04U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL 0x05U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT 0x06U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET 0x07U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT 0x0FU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE 0x10U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN 0x11U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP 0x12U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 0x13U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE 0x14U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE 0x15U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE 0x16U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE 0x17U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL 0x1AU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI 0x1CU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID 0xFFU
/*
* NVLINK TX Sublink states
* These should ALWAYS match the nvlink core library defines in nvlink.h
*/
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE 0x08U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY 0x0AU
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ 0x0BU
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN 0x0CU
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS 0x0DU
/*
* NVLINK RX Sublink states
* These should ALWAYS match the nvlink core library defines in nvlink.h
*/
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL 0x08U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM 0x09U
/*
* Link training seed values
* These should ALWAYS match the values defined in nvlink.h
*/
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM 6U
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE (0x7U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM + 1" */
// NVLINK callback types
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE 0x00U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE 0x01U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE 0x02U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE 0x03U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE 0x04U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE 0x05U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE 0x06U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE 0x07U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN 0x0BU
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE 0x0CU
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD 0x0DU
/*
* Structure to store the GET_DL_MODE callback params.
* mode
* The current Nvlink DL mode
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS {
NvU32 mode;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback OFF params
* seedData
* The output seed data
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS {
NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback PRE_HS params
* remoteDeviceType
* The input remote Device Type
* ipVerDlPl
* The input DLPL version
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS {
NvU32 remoteDeviceType;
NvU32 ipVerDlPl;
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS;
/*
* Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params
* seedData[]
* The input seed data
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS {
NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS;
/*
* Structure to store the Nvlink Remote and Local SID info
* remoteSid
* The output remote SID
* remoteDeviceType
* The output remote Device Type
* remoteLinkId
* The output remote link ID
* localSid
* The output local SID
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO {
NV_DECLARE_ALIGNED(NvU64 remoteSid, 8);
NvU32 remoteDeviceType;
NvU32 remoteLinkId;
NV_DECLARE_ALIGNED(NvU64 localSid, 8);
} NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO;
/*
* Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params
* bInitnegotiateConfigGood
* The output bool if the config is good
* remoteLocalSidInfo
* The output structure containing the Nvlink Remote/Local SID info
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS {
NvBool bInitnegotiateConfigGood;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params
* bPollDone
* The output bool if the polling has finished
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS {
NvBool bPollDone;
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback params
* mode
* The input nvlink state to set
* bSync
* The input sync boolean
* linkMode
* The input link mode to be set for the callback
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
NvU32 linkMode;
union {
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS linkModeOffParams;
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS linkModePreHsParams;
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS linkModeInitPhase1Params;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8);
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams;
} linkModeParams;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS;
/*
* Structure to store the GET_TL_MODE callback params.
* mode
* The current Nvlink TL mode
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS {
NvU32 mode;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS;
/*
* Structure to store the SET_TL_LINK_MODE callback params
* mode
* The input nvlink mode to set
* bSync
* The input sync boolean
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS;
/*
* Structure to store the GET_RX/TX_SUBLINK_MODE callback params
* sublinkMode
* The current Sublink mode
* sublinkSubMode
* The current Sublink sub mode
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS {
NvU32 sublinkMode;
NvU32 sublinkSubMode;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS;
/*
* Structure to store the SET_TL_LINK_MODE callback params
* mode
* The input nvlink mode to set
* bSync
* The input sync boolean
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS;
/*
* Structure to store the SET_RX_SUBLINK_MODE callback params
* mode
* The input nvlink mode to set
* bSync
* The input sync boolean
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS;
/*
* Structure to store the GET_RX_SUBLINK_DETECT callback params
* laneRxdetStatusMask
* The output RXDET per-lane status mask
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS {
NvU32 laneRxdetStatusMask;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS;
/*
* Structure to store the SET_RX_DETECT callback params
* bSync
* The input bSync boolean
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS {
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS;
/*
* Structure to store the RD_WR_DISCOVERY_TOKEN callback params
* ipVerDlPl
* The input DLPL version
* token
* The output token
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS {
NvU32 ipVerDlPl;
NV_DECLARE_ALIGNED(NvU64 token, 8);
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS;
/*
* Structure to store the GET_UPHY_LOAD callback params
* bUnlocked
* The output unlocked boolean
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS {
NvBool bUnlocked;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS;
/*
* Structure to store the Union of Callback params
* type
* The input type of callback to be executed
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE {
NvU8 type;
union {
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8);
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8);
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8);
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8);
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS getRxSublinkDetect;
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS setRxSublinkDetect;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8);
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS getUphyLoad;
} callbackParams;
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK
*
* Generic NvLink callback RPC to route commands to GSP
*
* [In] linkdId
* ID of the link to be used
* [In/Out] callBackType
* Callback params
*/
#define NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS {
NvU32 linkId;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE callbackType, 8);
} NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK (0x20800a24U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID
*
* Update Remote and Local Sid info via GSP
*
* [In] linkId
* ID of the link to be used
* [Out] remoteLocalSidInfo
* The output structure containing the Nvlink Remote/Local SID info
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x25U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS {
NvU32 linkId;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x20800a25U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED
*
* Returns if ALI is enabled
*
* [Out] bEnableAli
* Output boolean for ALI enablement
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS {
NvBool bEnableAli;
} NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED (0x20800a29U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET 0x1U
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX
*
* Generic Hshub Mux Update RPC to route commands to GSP
*
* [In] updateType
* HSHUB Mux update type to program or reset Mux
* [In] bSysMem
* Boolean to differentiate between sysmen and peer mem
* [In] peerMask
* Mask of peer IDs. Only parsed when bSysMem is false
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x42U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
NvBool updateType;
NvBool bSysMem;
NvU32 peerMask;
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX (0x20800a42U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER
*
* Performs all the necessary actions required before setting a peer on NVLink
*
* [In] peerId
* Peer ID which will be set on NVLink
* [In] peerLinkMask
* Mask of links that connects the given peer
* [In] bNvswitchConn
* Is the GPU connected to NVSwitch
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x4EU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerId;
NvU32 peerLinkMask;
NvBool bEgmPeer;
NvBool bNvswitchConn;
} NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER (0x20800a4eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER
*
* Performs all the necessary actions required after setting a peer on NVLink
*
* [In] peerMask
* Mask of Peer IDs which has been set on NVLink
*/
#define NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x50U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerMask;
} NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER (0x20800a50U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
/* ctrl2080internal_h */

71
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -77,6 +77,10 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 (0x00000180)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 (0x00000190)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 (0x000001A0)
/* valid ARCHITECTURE_T23X implementation values */
@@ -109,6 +113,25 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B)
/* valid ARCHITECTURE_GH10x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC (0x00000001)
/* valid ARCHITECTURE_AD10x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 (0x00000001)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 (0x00000001)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 (0x00000007)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B (0x0000000B)
/* valid ARCHITECTURE_GB10x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
@@ -166,52 +189,6 @@ typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
/*
* NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS
*
* This command is used to allow clients to query whether hostclk slowdown is
* disabled.
*
* bDisabled
* This parameter will hold the status of hostclk slowdown
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS (0x20801708) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
NvBool bDisabled;
} NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS
*
* This command is used to allow clients to disable/enable hostclk slowdown.
*
* bDisable
* When this parameter is set to TRUE, RM should disable hostclk slowdown.
* If it is set to FALSE, RM will attempt to enable hostclk slowdown, but
* in this case, slowdown is NOT guaranteed to be enabled since there may
* be other reason (like regkey) preventing slowdown.
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS (0x20801709) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP
*

639
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -104,6 +104,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
* Set if L3 is a supported power state on this subdevice/link, NV_FALSE otherwise.
* VALID
* Set if this link is supported on this subdevice, NV_FALSE otherwise. This field is used for *per-link* caps only and NOT for global caps.
* UNCONTAINED_ERROR_RECOVERY
* Set if this GPU supports resetless recovery from uncontained packet errors.
*
*/
@@ -121,6 +123,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2 1:0x04
#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3 1:0x08
#define NV2080_CTRL_NVLINK_CAPS_VALID 1:0x10
#define NV2080_CTRL_NVLINK_CAPS_UNCONTAINED_ERROR_RECOVERY 1:0x20
/*
* Size in bytes of nvlink caps table. This value should be one greater
@@ -135,10 +138,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 (0x00000008U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U)
@@ -146,10 +146,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 (0x00000008U)
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
*
@@ -377,10 +374,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 (0x00000008U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U)
@@ -389,10 +383,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 (0x00000008U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU)
#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U)
@@ -986,8 +977,6 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
#define NV2080_CTRL_NVLINK_COUNTERS_MAX 107U
#define NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS 2U
#define NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ 28
#define NV2080_CTRL_NVLINK_COUNTER_V2_GROUP(i) ((i) / 64)
@@ -1992,35 +1981,6 @@ typedef struct NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS {
NvBool bLockPowerMode;
} NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER
*
* This command is used to enable RM NVLink enabled peer state.
* Note: This just updates the RM state. To reflect the state in the registers,
* use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER
*
* [in] peerMask
* Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled
* [in] bEnable
* Whether the bit needs to be set or unset
*
* Possible status values returned are:
* NV_OK
* If the USE_NVLINK_PEER bit was enabled successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip, or
* If unsetting USE_NVLINK_PEER bit is not supported
*
*/
#define NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER (0x20803017U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
NvU32 peerMask;
NvBool bEnable;
} NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U
@@ -2068,433 +2028,9 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS];
} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
/*
* NVLINK Link states
* These should ALWAYS match the nvlink core library defines in nvlink.h
*/
#define NV2080_NVLINK_CORE_LINK_STATE_OFF 0x00U
#define NV2080_NVLINK_CORE_LINK_STATE_HS 0x01U
#define NV2080_NVLINK_CORE_LINK_STATE_SAFE 0x02U
#define NV2080_NVLINK_CORE_LINK_STATE_FAULT 0x03U
#define NV2080_NVLINK_CORE_LINK_STATE_RECOVERY 0x04U
#define NV2080_NVLINK_CORE_LINK_STATE_FAIL 0x05U
#define NV2080_NVLINK_CORE_LINK_STATE_DETECT 0x06U
#define NV2080_NVLINK_CORE_LINK_STATE_RESET 0x07U
#define NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U
#define NV2080_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU
#define NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU
#define NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU
#define NV2080_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT 0x0FU
#define NV2080_NVLINK_CORE_LINK_STATE_LANE_DISABLE 0x10U
#define NV2080_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN 0x11U
#define NV2080_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP 0x12U
#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE1 0x13U
#define NV2080_NVLINK_CORE_LINK_STATE_INITNEGOTIATE 0x14U
#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE 0x15U
#define NV2080_NVLINK_CORE_LINK_STATE_INITOPTIMIZE 0x16U
#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE 0x17U
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U
#define NV2080_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U
#define NV2080_NVLINK_CORE_LINK_STATE_INITTL 0x1AU
#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU
#define NV2080_NVLINK_CORE_LINK_STATE_ALI 0x1CU
#define NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU
#define NV2080_NVLINK_CORE_LINK_STATE_INVALID 0xFFU
/*
* NVLINK TX Sublink states
* These should ALWAYS match the nvlink core library defines in nvlink.h
*/
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE 0x08U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY 0x0AU
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ 0x0BU
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN 0x0CU
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS 0x0DU
/*
* NVLINK RX Sublink states
* These should ALWAYS match the nvlink core library defines in nvlink.h
*/
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL 0x08U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM 0x09U
/*
* Link training seed values
* These should ALWAYS match the values defined in nvlink.h
*/
#define NV2080_CTRL_NVLINK_MAX_SEED_NUM 6U
#define NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE (0x7U) /* finn: Evaluated from "NV2080_CTRL_NVLINK_MAX_SEED_NUM + 1" */
// NVLINK callback types
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE 0x00U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE 0x01U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE 0x02U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE 0x03U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE 0x04U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE 0x05U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE 0x06U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE 0x07U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN 0x0BU
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE 0x0CU
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD 0x0DU
/*
* Structure to store the GET_DL_MODE callback params.
* mode
* The current Nvlink DL mode
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS {
NvU32 mode;
} NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback OFF params
* seedData
* The output seed data
*/
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS {
NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE];
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback PRE_HS params
* remoteDeviceType
* The input remote Device Type
* ipVerDlPl
* The input DLPL version
*/
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS {
NvU32 remoteDeviceType;
NvU32 ipVerDlPl;
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS;
/*
* Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params
* seedData[]
* The input seed data
*/
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS {
NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE];
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS;
/*
* Structure to store the Nvlink Remote and Local SID info
* remoteSid
* The output remote SID
* remoteDeviceType
* The output remote Device Type
* remoteLinkId
* The output remote link ID
* localSid
* The output local SID
*/
typedef struct NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO {
NV_DECLARE_ALIGNED(NvU64 remoteSid, 8);
NvU32 remoteDeviceType;
NvU32 remoteLinkId;
NV_DECLARE_ALIGNED(NvU64 localSid, 8);
} NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO;
/*
* Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params
* bInitnegotiateConfigGood
* The output bool if the config is good
* remoteLocalSidInfo
* The output structure containing the Nvlink Remote/Local SID info
*/
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS {
NvBool bInitnegotiateConfigGood;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params
* bPollDone
* The output bool if the polling has finished
*/
typedef struct NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS {
NvBool bPollDone;
} NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS;
/*
* Structure to store the SET_DL_LINK_MODE callback params
* mode
* The input nvlink state to set
* bSync
* The input sync boolean
* linkMode
* The input link mode to be set for the callback
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
NvU32 linkMode;
union {
NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS linkModeOffParams;
NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS linkModePreHsParams;
NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS linkModeInitPhase1Params;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8);
NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams;
} linkModeParams;
} NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS;
/*
* Structure to store the GET_TL_MODE callback params.
* mode
* The current Nvlink TL mode
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS {
NvU32 mode;
} NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS;
/*
* Structure to store the SET_TL_LINK_MODE callback params
* mode
* The input nvlink mode to set
* bSync
* The input sync boolean
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
} NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS;
/*
* Structure to store the GET_RX/TX_SUBLINK_MODE callback params
* sublinkMode
* The current Sublink mode
* sublinkSubMode
* The current Sublink sub mode
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS {
NvU32 sublinkMode;
NvU32 sublinkSubMode;
} NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS;
/*
* Structure to store the SET_TL_LINK_MODE callback params
* mode
* The input nvlink mode to set
* bSync
* The input sync boolean
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
} NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS;
/*
* Structure to store the SET_RX_SUBLINK_MODE callback params
* mode
* The input nvlink mode to set
* bSync
* The input sync boolean
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mode, 8);
NvBool bSync;
} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS;
/*
* Structure to store the GET_RX_SUBLINK_DETECT callback params
* laneRxdetStatusMask
* The output RXDET per-lane status mask
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS {
NvU32 laneRxdetStatusMask;
} NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS;
/*
* Structure to store the SET_RX_DETECT callback params
* bSync
* The input bSync boolean
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS {
NvBool bSync;
} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS;
/*
* Structure to store the RD_WR_DISCOVERY_TOKEN callback params
* ipVerDlPl
* The input DLPL version
* token
* The output token
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS {
NvU32 ipVerDlPl;
NV_DECLARE_ALIGNED(NvU64 token, 8);
} NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS;
/*
* Structure to store the GET_UPHY_LOAD callback params
* bUnlocked
* The output unlocked boolean
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS {
NvBool bUnlocked;
} NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS;
/*
* Structure to store the Union of Callback params
* type
* The input type of callback to be executed
*/
typedef struct NV2080_CTRL_NVLINK_CALLBACK_TYPE {
NvU8 type;
union {
NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8);
NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8);
NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8);
NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8);
NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS getRxSublinkDetect;
NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS setRxSublinkDetect;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8);
NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS getUphyLoad;
} callbackParams;
} NV2080_CTRL_NVLINK_CALLBACK_TYPE;
/*
* NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK
*
* Generic NvLink callback RPC to route commands to GSP
*
* [In] linkdId
* ID of the link to be used
* [In/Out] callBackType
* Callback params
*/
#define NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS {
NvU32 linkId;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_TYPE callbackType, 8);
} NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK (0x20803019U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED
*
* Returns if ALI is enabled
*
* [Out] bEnableAli
* Output boolean for ALI enablement
*/
#define NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x1aU)
typedef struct NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS {
NvBool bEnableAli;
} NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED (0x2080301aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID
*
* Update Remote and Local Sid info via GSP
*
* [In] linkId
* ID of the link to be used
* [Out] remoteLocalSidInfo
* The output structure containing the Nvlink Remote/Local SID info
*/
#define NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x1bU)
typedef struct NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS {
NvU32 linkId;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
} NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x2080301bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U
#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET 0x1U
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX
*
* Generic Hshub Mux Update RPC to route commands to GSP
*
* [In] updateType
* HSHUB Mux update type to program or reset Mux
* [In] bSysMem
* Boolean to differentiate between sysmen and peer mem
* [In] peerMask
* Mask of peer IDs. Only parsed when bSysMem is false
*/
#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x1cU)
typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
NvBool updateType;
NvBool bSysMem;
NvU32 peerMask;
} NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX (0x2080301cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER
*
* Performs all the necessary actions required before setting a peer on NVLink
*
* [In] peerId
* Peer ID which will be set on NVLink
* [In] peerLinkMask
* Mask of links that connects the given peer
* [In] bNvswitchConn
* Is the GPU connected to NVSwitch
*/
#define NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1dU)
typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerId;
NvU32 peerLinkMask;
NvBool bEgmPeer;
NvBool bNvswitchConn;
} NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER
*
* Performs all the necessary actions required after setting a peer on NVLink
*
* [In] peerMask
* Mask of Peer IDs which has been set on NVLink
*/
#define NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1eU)
typedef struct NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerMask;
} NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER (0x2080301eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U
@@ -3333,7 +2869,7 @@ typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS {
*
* [In] linkId
* Id of the link on which error occured
* [In] bIsGpuDegraded
* [Out] bIsGpuDegraded
* Boolean to track corresponding GPU is degraded or not
*/
#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x41U)
@@ -3484,6 +3020,7 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH 496U
typedef struct NV2080_CTRL_NVLINK_PRM_DATA {
@@ -3513,7 +3050,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS {
} NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS;
/*!
*
* NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS
@@ -3609,15 +3145,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS {
NvU8 slot_index;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTWE (0x2080305dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID (0x5dU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE (0x2080305eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID (0x5eU)
@@ -3663,28 +3190,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS {
NvU16 admin_mtu;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCIA (0x20803063U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID (0x63U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 slot_index;
NvU8 module;
NvBool pnv;
NvBool l;
NvU16 device_address;
NvU8 page_number;
NvU8 i2c_device_address;
NvU16 size;
NvU8 bank_number;
NvBool passwd_length;
NvU32 password;
NvU32 dword[32];
NvU32 password_msb;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP (0x20803064U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID (0x64U)
@@ -4109,6 +3614,136 @@ typedef struct NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS {
NvU8 moduleId;
} NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS;
/*
* Structure to store UPHY cmd data.
* laneId
* Lane ID for specified link
* address
* Desired address for read
*/
typedef struct NV2080_CTRL_NVLINK_UPHY_CLN_CMD {
NvU8 pllIndex;
NvU16 address;
} NV2080_CTRL_NVLINK_UPHY_CLN_CMD;
#define NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS 18U
/*
* NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN
*
*
* This command retrieves the land id cln select, lane id, and pll index.
*
* [in] linkMask
* Mask of links whose uphy should be read
* [in] uphyCmd
* Array of input data (pll index and address) for each link,
* where index 0 represents link 0's pll index
* and index 16 represents link 16's pll index.
* [out] data
* Data from uphy cln for each link where index 0 represents link 0's pll index
* and index 16 represents link 16's pll index.
*
* Possible status values returned are:
* NV_OK
* If the minion command completed successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip
* NV_ERR_INVALID_ARGUMENT
* If the link is not enabled on the GPU or the lane is invalid
* NV_ERR_TIMEOUT
* If a timeout occurred waiting for minion response
*/
#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN (0x20803084U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID (0x84U)
typedef struct NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_UPHY_CLN_CMD uphyCmd[NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS];
NvU32 data[NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS];
} NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS;
#define NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT 23U
/*
* NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE
*
* This command gets the supported RBMs of the GPU
*
* [out] rbmModesList
* List of supported RBM modes
* [out] rbmTotalModes
* Total RBM modes supported
* Possible status values returned are: TODO: Update this
* NV_OK
* If the BW mode is retrieved successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip
* NV_ERR_INVALID_ARGUMENT
* If the link is not enabled on the GPU
* NV_ERR_INVALID_STATE
* If the link is in an invalid state
*/
#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE (0x20803085U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS {
NvU8 rbmModesList[NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT];
NvU8 rbmTotalModes;
} NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_SET_BW_MODE
*
* This command sets the requested RBM of the GPU
*
* [in] rbmMode
* Requested RBM mode
*
* Possible status values returned are: TODO: Update this
* NV_OK
* If the BW mode is set successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip
* NV_ERR_INVALID_ARGUMENT
* If the link is not enabled on the GPU
* NV_ERR_INVALID_STATE
* If the link is in an invalid state
*/
#define NV2080_CTRL_CMD_NVLINK_SET_BW_MODE (0x20803086U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID (0x86U)
typedef struct NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS {
NvU8 rbmMode;
} NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_GET_BW_MODE
*
* This command gets the set RBM of the GPU
*
* [out] rbmMode
* RBM mode currently set
*
* Possible status values returned are: TODO: Update this
* NV_OK
* If the BW mode is set successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip
* NV_ERR_INVALID_ARGUMENT
* If the link is not enabled on the GPU
* NV_ERR_INVALID_STATE
* If the link is in an invalid state
*/
#define NV2080_CTRL_CMD_NVLINK_GET_BW_MODE (0x20803087U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS {
NvU8 rbmMode;
} NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS;
/* _ctrl2080nvlink_h_ */

35
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -40,21 +40,23 @@
* @brief SPDM Command Types
*
*/
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE 0x2400
#define RSVD7_SIZE 16
#define RSVD7_SIZE 16
#define RSVD8_SIZE 2
#define RSVD8_SIZE 2
/*!
* Guest RM provides INIT context
@@ -227,5 +229,20 @@ typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS {
RM_GSP_SPDM_MSG msg;
} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS;
/*
* NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT
*
* This command retrieves the transcript of SPDM session establishment messages.
*
*/
#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID (0xDAU)
typedef struct NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS {
NvU8 transcript[SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE];
NvU32 transcriptSize;
} NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS;

20
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -438,4 +438,24 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS {
NvU32 flags;
} NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS
*
* Returns information whether frame rate limiter is disabled.
*
* bFlrDisabled [OUT]
* True, if frame rate limiter is disabled.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS (0x2080400d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
NvBool bFlrDisabled;
} NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */

4
src/common/sdk/nvidia/inc/ctrl/ctrl208f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -48,5 +48,5 @@
#include "ctrl208f/ctrl208fdma.h"
#include "ctrl208f/ctrl208fmmu.h"
#include "ctrl208f/ctrl208fucodecoverage.h"
#include "ctrl208f/ctrl208fpmu.h"

80
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h
View File

@@ -306,8 +306,10 @@ typedef struct NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS {
NvU32 col;
NvU32 extBank;
NvU32 rank;
NvU32 sublocation;
NvU32 partition;
NvU32 physicalSublocation;
NvU32 physicalPartition;
NvU32 logicalSublocation;
NvU32 logicalPartition;
NvU32 writeKillPtr0;
NvU32 injectionAddr;
NvU32 injectionAddrExt;
@@ -462,11 +464,20 @@ typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 address, 8);
} NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS;
typedef struct NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO {
NvU32 bank;
NvU32 stackId;
NvU32 row;
NvU32 partition;
NvU32 sublocation;
} NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO;
#define NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_PHYSICAL 0x0
#define NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_RBC 0x1
/*
* NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO
*
* physicalAddress
* Physical address to be remapped
* source
* The reason for retirement. Valid values for this parameter are
* from NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_*
@@ -482,11 +493,23 @@ typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS {
* Attempting to remap a reserved row
* NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR
* Some other RM failure
* addressType
* Type of address passed. Valid values are:
* NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_PHYSICAL
* The specified address is physical address.
* NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_RBC
* The specified address is DRAM Row Bank Column address.
* address
* Union of physicalAddress and rbcAddress. Set the appropriate one based on the address type.
*/
typedef struct NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO {
NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
NvU8 source;
NvU32 status;
NvU8 addressType;
union {
NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO rbcAddress;
} address;
} NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO;
/* valid values for status */
@@ -654,4 +677,51 @@ typedef struct NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS {
NV208F_CTRL_FB_ERROR_TYPE errorType;
} NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS;
/*
* NV208F_CTRL_CMD_FB_GET_FBPA_PAC_MASKS
*
* This API returns the PAC mask for an FBPA. The format is an array where the
* index is the physical FBPA value and the value at the index is the channel
* mask at the corresponding FBPA. At this time there can only be max 4
* channels per FBPA. A floorswept FBPA will have a value of 0x0, vs a
* non-floorswept FBPA with no floorswept channels will have a value of 0xf
*
*/
#define NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_MAX_FBPAS 64
#define NV208F_CTRL_CMD_FB_GET_FBPA_PAC_MASKS (0x208f0518) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS {
NvU8 fbpas[NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_MAX_FBPAS];
} NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS;
/*
* NV208F_CTRL_CMD_FB_CONVERT_CHANNEL
*
* This API converts either a channel from physical to logical or vice-versa
*
* conversionType:
* See NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE
* fbpa:
* The physical fbpa the channel resides
* input:
* Input channel
* output:
* Output channel
*/
#define NV208F_CTRL_CMD_FB_CONVERT_CHANNEL (0x208f0519) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS {
NvU32 conversionType;
NvU32 fbpa;
NvU32 input;
NvU32 output;
} NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS;
#define NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE_LOGICAL_TO_PHYSICAL (0x00000000U)
#define NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE_PHYSICAL_TO_LOGICAL (0x00000001U)
/* _ctrl208ffb_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

29
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -69,7 +69,6 @@ typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS {
NvU8 unit;
NvU8 errorType;
NvU8 instance;
} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS;
@@ -127,18 +126,18 @@ typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS {
NvU32 numHshubmmus;
} NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS;
/*
* NV208F_CTRL_CMD_MMU_GET_NUM_HUBMMUS
*
* Returns the number of ECC Capable HUBMMUS.
*
* numHubmmus [out]
* Number of Hubmmus
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
/*
* NV208F_CTRL_CMD_MMU_GET_NUM_HUBMMUS
*
* Returns the number of ECC Capable HUBMMUS.
*
* numHubmmus [out]
* Number of Hubmmus
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV208F_CTRL_CMD_MMU_GET_NUM_HUBMMUS (0x208f0b04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS_MESSAGE_ID (0x4U)
@@ -147,6 +146,4 @@ typedef struct NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS {
NvU32 numHubmmus;
} NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS;
/* _ctrl208fmmu_h_ */

95
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmu.h Normal file
View File

@@ -0,0 +1,95 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl208f/ctrl208fpmu.finn
//
#include "ctrl/ctrl208f/ctrl208fbase.h"
/*
* NV208F_CTRL_CMD_PMU_ECC_INJECT_ERROR
*
* This ctrl call injects PMU ECC errors. Please see the confluence
* page "ECC" for more information on ECC and ECC injection.
*
* Parameters:
*
* location
* Specifies the PMU HW unit where the injection will occur.
*
* errorType
* Specifies whether the injected error will be correctable or uncorrectable.
* Correctable errors have no effect on running programs while uncorrectable
* errors will cause all channels to be torn down.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV208F_CTRL_CMD_PMU_ECC_INJECT_ERROR (0x208f0c01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID << 8) | NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS {
NvU8 errorType;
} NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS;
#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_TYPE 0:0
#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_TYPE_CORRECTABLE (0x00000000)
#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_TYPE_UNCORRECTABLE (0x00000001)
/*
* NV208F_CTRL_CMD_PMU_ECC_INJECTION_SUPPORTED
*
* Reports if error injection is supported for the PMU
*
* bCorrectableSupported [out]:
* Boolean value that shows if correcatable errors can be injected.
*
* bUncorrectableSupported [out]:
* Boolean value that shows if uncorrecatable errors can be injected.
*
* Return values:
* NV_OK on success
* NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
* NV_ERR_NOT_SUPPORTED otherwise
*
*
*/
#define NV208F_CTRL_CMD_PMU_ECC_INJECTION_SUPPORTED (0x208f0c02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID << 8) | NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS {
NvBool bCorrectableSupported;
NvBool bUncorrectableSupported;
} NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS;
/* _ctrl208fpmu_h_ */

17
src/common/sdk/nvidia/inc/ctrl/ctrl5080.h
View File

@@ -32,7 +32,6 @@
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl0080/ctrl0080dma.h" /* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS */
#include "ctrl/ctrl2080/ctrl2080dma.h" /* NV2080_CTRL_DMA_* */
#include "ctrl/ctrl2080/ctrl2080fb.h" /* NV2080_CTRL_FB_* */
#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_* */
#include "ctrl/ctrl2080/ctrl2080gpu.h" /* NV2080_CTRL_GPU_* */
#include "ctrl/ctrl2080/ctrl2080gr.h" /* NV2080_CTRL_GR_* */
@@ -101,20 +100,16 @@ typedef struct NV5080_CTRL_DEFERRED_API_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8);
NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx;
NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx;
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb;
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8);
NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS CacheAllocPolicy;
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8);
NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy;
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8);
} api_bundle;
} NV5080_CTRL_DEFERRED_API_PARAMS;
@@ -166,20 +161,16 @@ typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8);
NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx;
NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx;
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb;
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8);
NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS CacheAllocPolicy;
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8);
NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy;
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS DisableChannels, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8);

16
src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1143,5 +1143,19 @@ typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS {
NvU32 count;
} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS;
/*
* NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC
*
* bDropDeferredRc (OUT)
* This indicates whether debugger wants a fault to eventually trigger RC on teardown or be dropped.
*/
#define NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC (0x83de0329) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID" */
#define NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS {
NvBool bDropDeferredRc;
} NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS;
/* _ctrl83dedebug_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrl90e7/ctrl90e7base.h
View File

@@ -39,6 +39,7 @@
#define NV90E7_CTRL_BBX_LEGACY_PRIVILEGED (0xc1) /* finn: Evaluated from "(NV90E7_CTRL_BBX | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV90E7_CTRL_BBX (0x01)
#define NV90E7_CTRL_RPR (0x02)
#define NV90E7_CTRL_PREDICTIVE (0x03)
/*
* NV90E7_CTRL_CMD_NULL

27
src/common/sdk/nvidia/inc/ctrl/ctrl90e7/ctrl90e7bbx.h
View File

@@ -63,3 +63,30 @@ typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS {
/*
* NV90E7_CTRL_CMD_BBX_IS_NVM_FLUSH_ENABLED
*
* This command is used to query whether BBX flushing to non-volatile memory is enabled.
*
* bIsEnabled
* Whether BBX flushing to non-volatile memory is enabled.
* bPeriodicFlush
* Whether BBX periodically flushes to non-volatile memory.
* periodicFlushIntervalSec
* The minimum interval (in seconds) between two consecutive periodic BBX flushes
* if periodic flush is enabled.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV90E7_CTRL_CMD_BBX_IS_NVM_FLUSH_ENABLED (0x90e70119) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS_MESSAGE_ID" */
#define NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS {
NvBool bIsEnabled;
NvBool bPeriodicFlush;
NvU32 periodicFlushIntervalSec;
} NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS;

83
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -242,6 +242,8 @@ typedef struct NVA081_GUEST_VM_INFO {
* placementId [OUT]
* This param specifies the placement ID of heterogeneous timesliced vGPU instance.
* Otherwise it is NVA081_PLACEMENT_ID_INVALID.
* vgpuDevName [OUT]
* This param specifies the VF BDF of the virtual GPU.
*
*/
typedef struct NVA081_HOST_VGPU_DEVICE {
@@ -249,7 +251,7 @@ typedef struct NVA081_HOST_VGPU_DEVICE {
NvU32 vgpuDeviceInstanceId;
NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8);
NvU8 vgpuUuid[VM_UUID_SIZE];
NvU8 mdevUuid[VM_UUID_SIZE];
NvU8 vgpuDevName[VM_UUID_SIZE];
NvU32 encoderCapacity;
NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
NvU32 eccState;
@@ -737,16 +739,25 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS {
* This param specific whether timesliced heterogeneous vGPU is enabled
* for different FB sized profiles.
*
* vgpuTypeId [IN]
* This param specifies the Type ID for VGPU profile
*
* placementId [IN / OUT]
* This param specifies the input placement ID provided by hypervisor
* or output placement ID reserved by RM for vGPU type ID.
*
* TODO : This same RmCtrl will be also be used to provide GSP heap offset
* to CPU plugin when vGPU-GSP is enabled.
* (As guest fb and gsp heap is allocated before A084 object)
* vgpuTypeId [IN]
* This param specifies the Type ID for VGPU profile
*
* guestFbLength [OUT]
* This param specifies the FB size assigned to the VM.
*
* guestFbOffset [OUT]
* This param specifies the starting FB offset assigned to the VM.
*
* gspHeapOffset [OUT]
* This param specifies the heap offset of gsp vgpu task.
*
* guestBar1PFOffset [OUT]
* This param specifies the starting PF BAR1 offset assigned to the VM.
* Only applicable for the legacy GPUs.
*
* Possible status values returned are:
* NV_OK
@@ -765,6 +776,7 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 guestFbLength, 8);
NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8);
NV_DECLARE_ALIGNED(NvU64 gspHeapOffset, 8);
NV_DECLARE_ALIGNED(NvU64 guestBar1PFOffset, 8);
} NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS;
/*
@@ -825,9 +837,15 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
} NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS;
/* vGPU capabilities */
#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0
#define NVA081_CTRL_VGPU_CAPABILITY_COMPUTE_MEDIA_ENGINE_GPU 1
#define NVA081_CTRL_VGPU_CAPABILITY_WARM_UPDATE 2
#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0
#define NVA081_CTRL_VGPU_CAPABILITY_COMPUTE_MEDIA_ENGINE_GPU 1
#define NVA081_CTRL_VGPU_CAPABILITY_WARM_UPDATE 2
#define NVA081_CTRL_VGPU_CAPABILITY_DEVICE_STREAMING 3
#define NVA081_CTRL_VGPU_CAPABILITY_READ_DEVICE_BUFFER_BW 4
#define NVA081_CTRL_VGPU_CAPABILITY_WRITE_DEVICE_BUFFER_BW 5
#define NVA081_CTRL_VGPU_CAPABILITY_HETEROGENEOUS_TIMESLICE_SIZES 6
#define NVA081_CTRL_VGPU_CAPABILITY_HETEROGENEOUS_TIMESLICE_PROFILES 7
#define NVA081_CTRL_VGPU_CAPABILITY_FRACTIONAL_MULTI_VGPU 8
/*
* NVA081_CTRL_CMD_VGPU_SET_CAPABILITY
@@ -846,7 +864,7 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID (0x1eU)
@@ -877,20 +895,24 @@ typedef struct NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS {
#define NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS_MESSAGE_ID (0x1fU)
typedef struct NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS {
NvU32 capability;
NvBool state;
NvU32 capability;
NvU32 state;
} NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_SET_VM_NAME
*
* This command is to set VM name for KVM.
* This command is to set VM name for the host.
*
* vgpuName [IN]
* This param provides the vGPU device name to RM.
* vmIdType [IN]
* This param provides the guest VM ID type based on the host.
*
* guestVmId [IN]
* This param provides the guest VM indentifier to RM based on the host.
*
* vmName [IN]
* This param provides the VM name of the vGPU device attached.
* This param provides the VM name of the vGPU device attached
* to the above mentioned host VM.
*
* Possible status values returned are:
* NV_OK
@@ -903,8 +925,9 @@ typedef struct NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS {
#define NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS_MESSAGE_ID (0x20U)
typedef struct NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS {
NvU8 vgpuName[VM_UUID_SIZE];
NvU8 vmName[NVA081_VM_NAME_SIZE];
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
NvU8 vmName[NVA081_VM_NAME_SIZE];
} NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS;
/*
@@ -957,4 +980,26 @@ typedef struct NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS {
NvBool isBar064bit;
} NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH
*
* This command is to get the migration bandwidth of the physical GPU.
*
* migrationBandwidth [OUT]
* This param specifies the migration bandwidth of GPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_REQUEST
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH (0xa0810122) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID (0x22U)
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS {
NvU32 migrationBandwidth;
} NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS;
/* _ctrlA081vgpuconfig_h_ */

50
src/common/sdk/nvidia/inc/ctrl/ctrla084.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -308,4 +308,52 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS {
NvU32 flags;
} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS;
#define NVA084_MAX_VMMU_SEGMENTS_COUNT 384
/*
* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK
*
* This command will update the bootload vGPU task
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CLIENT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
*
* Parameters:
* numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient
* guestFbHandleList -> handle list to guest memory
* hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient
* ctrlBuffOffset -> offset of control buffer
* initTaskLogBuffOffset -> offset of init task log buffer
* initTaskLogBuffSize -> size of init task log buffer
* vgpuTaskLogBuffOffset -> offset of vgpu task log buffer
* vgpuTaskLogBuffSize -> size of vgpu task log buffer
* kernelLogBuffOffset -> offset of kernel log buffer
* kernelLogBuffSize -> size of kernel log buffer
* hMigRmHeapMemory -> MIG-RM heap memory handle
* bDeviceProfilingEnabled -> If set to true, profiling is allowed
*/
#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK (0xa084010d) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS_MESSAGE_ID" */
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS_MESSAGE_ID (0xDU)
typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS {
NvU32 numGuestFbHandles;
NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS_COUNT];
NvHandle hPluginHeapMemory;
NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
NvHandle hMigRmHeapMemory;
NvBool bDeviceProfilingEnabled;
} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS;
/* _ctrla084_h_ */

9
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
View File

@@ -135,9 +135,14 @@ typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS {
NvBool bDevProfilingPermitted;
/*!
* [in] Is Memory profiling permitted
* [in] Is Video memory profiling permitted
*/
NvBool bMemoryProfilingPermitted;
NvBool bVideoMemoryProfilingPermitted;
/*!
* [in] Is SYS memory profiling permitted
*/
NvBool bSysMemoryProfilingPermitted;
} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS;
#define NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x4U)

26
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -558,7 +558,7 @@ typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
/*!
* Defines the maximum count of output credit pools.
* 30 is estimate based on the # of PMAs (2) and chiplet types(3),
* 30 is estimate based on the # of PMAs (2) and chiplet types(3),
* which should be big enough to accommodate the required number of credit pools
*/
#define NVB0CC_CREDIT_POOL_MAX_COUNT 30
@@ -566,7 +566,7 @@ typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
/*!
* NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL
*
* Gets the total high speed streaming credits available for the client
* Gets the total high speed streaming credits available for the client
* in each chiplet pool.
*
* This command is similar to @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS but
@@ -606,25 +606,25 @@ typedef struct NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL {
} NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL;
typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO {
/*!
* [in] Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE.
/*!
* [in] Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE.
*/
NvU8 chipletType;
/*!
* [in] Specifies the logical index of the chiplet.
/*!
* [in] Specifies the logical index of the chiplet.
*/
NvU8 chipletIndex;
/*!
* [out] Specifies the index of credits pool for the chiplet.
/*!
* [out] Specifies the index of credits pool for the chiplet.
*/
NvU8 poolIndex;
} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO;
/*!
* NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING
*
*
* Query the associated PMA credit pool index for given chiplet.
*
*/
@@ -648,12 +648,10 @@ typedef struct NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS {
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO queries[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
} NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS;
/* End of extension construct */
/*!
* NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST
*
*
* Disable the Dynamic MMA clock boost during profiler lifetime.
*
*/
@@ -669,7 +667,7 @@ typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS {
/*!
* NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS
*
*
* Request the Dynamic MMA clock boost feature enablement status.
*
*/

51
src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h
View File

@@ -45,6 +45,7 @@
#define NVC36F_CTRL_RESERVED (0x00)
#define NVC36F_CTRL_GPFIFO (0x01)
#define NVC36F_CTRL_EVENT (0x02)
#define NVC36F_CTRL_INTERNAL (0x03)
/*
* NVC36F_CTRL_CMD_NULL
@@ -58,22 +59,6 @@
/*
* NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
/*
* NVC36F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
*
@@ -155,5 +140,39 @@ typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS {
NvU32 index;
} NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS;
/*
* NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
/*
* NVC36F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN
*
* This command is an internal command sent from Kernel RM to Physical RM
* to get work submit token
*
* Please see description of NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN for more information.
*
*/
#define NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN (0xc36f0301) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID (0x1U)
typedef NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
/* _ctrlc36f.h_ */

41
src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021,2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -154,9 +154,9 @@
* means the cursor is disabled.
*
* head.tileMask
* This parameter specifies the number of tiles which will be assigned to
* the head. Normally, this parameter is set to zero, allowing IMP to
* calculate the number of tiles, but the number of tiles may be specified
* This parameter contains a bitmask specifying which tiles must be
* assigned to the head. Normally, this parameter is set to zero, allowing
* IMP to calculate the number of tiles, but the tiles may be specified
* explicitly for test or debug. If the mode is not possible with the
* specified number of tiles, IMP will report the result as such; the
* number of tiles will not be adjusted.
@@ -168,29 +168,32 @@
* optionally be used to force the number of DSC slices.
*
* head.bEnableDsc
* bEnableDsc indicates whether or not DSC is enabled
* bEnableDsc indicates whether or not DSC is enabled, by default. If it
* is disabled by default, but head.possibleDscSliceCountMask is non-zero,
* IMP may still present tiling solutions with DSC enabled, but only if the
* mode is not possible otherwise. (This will be indicated by a non-zero
* tileList.headDscSlices output.)
*
* head.dscTargetBppX16
* dscTargetBppX16 is the DSC encoder's target bits per pixel, multiplied
* by 16.
*
* This field is required only on systems that support tiling, and only if
* head.bEnableDsc is true.
* head.possibleDscSliceCountMask is true.
*
* head.possibleDscSliceCountMask
* This is a bit mask indicating how many DSC slices are allowed in a
* scanline. If a bit n is set in the bit mask, it means that one possible
* configuration has n+1 DSC slices per scanline.
*
* This field is required only on systems that support tiling, and only if
* head.bEnableDsc is true.
* This field is required only on systems that support tiling.
*
* head.maxDscSliceWidth
* The maximum allowed DSC slice width is determined by spec restrictions
* and monitor capabilities.
*
* This field is required only on systems that support tiling, and only if
* head.bEnableDsc is true.
* head.possibleDscSliceCountMask is true.
*
* head.bYUV420Format
* This parameter indicates output format is YUV420.
@@ -230,6 +233,12 @@
* This parameter is a bitmask of all possible rotated mode data formats
* (NVC372_CTRL_FORMAT_xxx values).
*
* window.surfaceLayout
* This parameter is the surface layout of the window. It is one of
* NVC372_CTRL_LAYOUT_xxx values.
* The default value of 0U would imply that SW uses legacy equations
* (pre NVD5.0) in its computation for fetch BW.
*
* window.maxPixelsFetchedPerLine
* This parameter defines the maximum number of pixels that may need to be
* fetched in a single line for this window. Often, this can be set to the
@@ -517,6 +526,10 @@
* assigned to head 0, bringing the tile total to three for that head. The
* number of DSC slices required for that head would be increased to three.
*
* Note that the tiling assignments do not specify which tiles to use; they
* only specify how many tiles to assign to each head. The client must
* choose which tiles to assign, based on their capabilities.
*
* tilingAssignments.numTiles
* This is the number of additional tiles required for the indexed tiling
* assignment. The tilingAssignment does not provide any benefit unless
@@ -536,6 +549,10 @@
* head (if a single head requires that more than one additional tile be
* assigned).
*
* tilelist.head indexes heads as they are indexed in the
* NVC372_CTRL_IMP_HEAD array within the IMP input data structure. (These
* do not necessarily correspond to physical head indexes.)
*
* tileList.headDscSlices
* headDscSlices gives the recommended number of DSC slices for each
* scanline for the head specified in tileList.head. If a specific tiling
@@ -637,6 +654,7 @@ typedef struct NVC372_CTRL_IMP_WINDOW {
NvBool bOverfetchEnabled;
NvU8 lut;
NvU8 tmoLut;
NvU8 surfaceLayout;
} NVC372_CTRL_IMP_WINDOW;
typedef struct NVC372_CTRL_IMP_WINDOW *PNVC372_CTRL_IMP_WINDOW;
@@ -722,6 +740,11 @@ typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBL
#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422R (0x00008000)
#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_444 (0x00010000)
/* valid layout values */
#define NVC372_CTRL_LAYOUT_PITCH_BLOCKLINEAR 0
#define NVC372_CTRL_LAYOUT_PITCH 1
#define NVC372_CTRL_LAYOUT_BLOCKLINEAR 2
/* valid impResult values */
#define NVC372_CTRL_IMP_MODE_POSSIBLE 0
#define NVC372_CTRL_IMP_NOT_ENOUGH_MEMPOOL 1

2
src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h
View File

@@ -145,7 +145,7 @@ typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS {
*/
#define SECURITY_POLICY_ATTACKER_ADVANTAGE_DEFAULT (60)
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MIN (50)
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (75)
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (65)
#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY (0xc56f010d) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */

6
src/common/sdk/nvidia/inc/ctrl/ctrlc637.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,6 +30,7 @@
// Source file: ctrl/ctrlc637.finn
//
#include "nvlimits.h"
#include "ctrl/ctrlxxxx.h"
/* AMPERE_SMC_PARTITION_REF commands and parameters */
@@ -257,9 +258,8 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */
#define NVC637_UUID_LEN 16
#define NVC637_UUID_STR_LEN (0x29) /* finn: Evaluated from "((NVC637_UUID_LEN << 1) + 9)" */
#define NVC637_UUID_STR_LEN NV_MIG_DEVICE_UUID_STR_LENGTH
typedef struct NVC637_EXEC_PARTITION_UUID {
// C form: char str[NVC638_UUID_STR_LEN];

2
src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/ctrl/ctrlc96f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h
View File

@@ -108,6 +108,8 @@
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP 3
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM 4
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1

2
src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

8
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -257,6 +257,8 @@ typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_STEREO;
#define FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID (0x7301U)
typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SYSTEM;
#define FINN_NV01_FRAMEBUFFER_CONSOLE_INTERFACE_ID (0x007601U)
typedef FINN_RM_API FINN_NV01_FRAMEBUFFER_CONSOLE;
#define FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID (0x8000U)
typedef FINN_RM_API FINN_NV01_DEVICE_0_RESERVED;
#define FINN_NV01_DEVICE_0_BIF_INTERFACE_ID (0x8001U)
@@ -446,6 +448,9 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR;
#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU;
#define FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID (0x208f0cU)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_PMU;
#define FINN_NV20_SUBDEVICE_DIAG_UCODE_COVERAGE_INTERFACE_ID (0x208f19U)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_UCODE_COVERAGE;
#define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U)
@@ -665,6 +670,8 @@ typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED;
typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO;
#define FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc36f02U)
typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT;
#define FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xc36f03U)
typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL;
#define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U)
typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED;
#define FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID (0xc37001U)
@@ -710,7 +717,6 @@ typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED;
typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER;
#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U)
typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc96f00U)
typedef FINN_RM_API FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED;

3
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -145,7 +145,8 @@
#define ROBUST_CHANNEL_KEY_ROTATION_ERROR (151)
#define RESERVED7_ERROR (152)
#define RESERVED8_ERROR (153)
#define ROBUST_CHANNEL_LAST_ERROR (153)
#define GPU_RECOVERY_ACTION_CHANGED (154)
#define ROBUST_CHANNEL_LAST_ERROR (154)
// Indexed CE reference

14
src/common/sdk/nvidia/inc/nvfixedtypes.h
View File

@@ -315,6 +315,7 @@ typedef NvUFXP64 NvUFXP60_4;
#define NV_TYPES_SINGLE_SIGN_NEGATIVE 0x00000001
#define NV_TYPES_SINGLE_EXPONENT 30:23
#define NV_TYPES_SINGLE_EXPONENT_ZERO 0x00000000
#define NV_TYPES_SINGLE_EXPONENT_MAX 0x000000FE
#define NV_TYPES_SINGLE_EXPONENT_BIAS 0x0000007F
#define NV_TYPES_SINGLE_MANTISSA 22:0
@@ -346,6 +347,19 @@ typedef NvUFXP64 NvUFXP60_4;
((NvS32)(DRF_VAL(_TYPES, _SINGLE, _EXPONENT, single) - \
NV_TYPES_SINGLE_EXPONENT_BIAS))
/*!
* Helper macro to convert an NvS8 unbiased exponent value to an IEEE 754
* single-precision value's exponent, by adding the bias.
* Input exponent can range from -127 to 127 which is stored in the range
* [0, 254]
*
* @param[in] single IEEE 754 single-precision value to manipulate.
*
* @return Biased exponent value for IEEE 754 single-precision.
*/
#define NV_TYPES_NvS32_TO_SINGLE_EXPONENT_BIASED(exponent) \
((NvU32)((exponent) + NV_TYPES_SINGLE_EXPONENT_BIAS))
/*!
* NvTemp - temperature data type introduced to avoid bugs in conversion between
* various existing notations.

16
src/common/sdk/nvidia/inc/nvlimits.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,19 +34,25 @@
/*
* This is the maximum number of GPUs supported in a single system.
*/
#define NV_MAX_DEVICES 32
#define NV_MAX_DEVICES 32
/*
* This is the maximum number of subdevices within a single device.
*/
#define NV_MAX_SUBDEVICES 8
#define NV_MAX_SUBDEVICES 8
/*
* This is the maximum length of the process name string.
*/
#define NV_PROC_NAME_MAX_LENGTH 100U
#define NV_PROC_NAME_MAX_LENGTH 100U
/*
* This is the maximum number of heads per GPU.
*/
#define NV_MAX_HEADS 4
#define NV_MAX_HEADS 4
/*
* Maximum length of a MIG device UUID. It is a 36-byte UUID string plus a
* 4-byte prefix and NUL terminator: 'M' 'I' 'G' '-' UUID '\0x0'
*/
#define NV_MIG_DEVICE_UUID_STR_LENGTH 41U

36
src/common/sdk/nvidia/inc/nvmisc.h
View File

@@ -721,6 +721,42 @@ nvPrevPow2_U64(const NvU64 x )
} \
}
//
// Bug 4851259: Newly added functions must be hidden from certain HS-signed
// ucode compilers to avoid signature mismatch.
//
#ifndef NVDEC_1_0
/*!
* Returns the position of nth set bit in the given mask.
*
* Returns -1 if mask has fewer than n bits set.
*
* n is 0 indexed and has valid values 0..31 inclusive, so "zeroth" set bit is
* the first set LSB.
*
* Example, if mask = 0x000000F0u and n = 1, the return value will be 5.
* Example, if mask = 0x000000F0u and n = 4, the return value will be -1.
*/
static NV_FORCEINLINE NvS32
nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
{
NvU32 seenSetBitsCount = 0;
NvS32 index;
FOR_EACH_INDEX_IN_MASK(32, index, mask)
{
if (seenSetBitsCount == n)
{
return index;
}
++seenSetBitsCount;
}
FOR_EACH_INDEX_IN_MASK_END;
return -1;
}
#endif // NVDEC_1_0
//
// Size to use when declaring variable-sized arrays
//

42
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -191,7 +191,6 @@ typedef struct
#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001)
#define NVOS02_FLAGS_LOCATION 11:8
#define NVOS02_FLAGS_LOCATION_PCI (0x00000000)
#define NVOS02_FLAGS_LOCATION_AGP (0x00000001)
#define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002)
#define NVOS02_FLAGS_COHERENCY 15:12
#define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000)
@@ -1106,7 +1105,6 @@ typedef struct
#define NVOS32_ATTR_LOCATION 26:25
#define NVOS32_ATTR_LOCATION_VIDMEM 0x00000000
#define NVOS32_ATTR_LOCATION_PCI 0x00000001
#define NVOS32_ATTR_LOCATION_AGP 0x00000002
#define NVOS32_ATTR_LOCATION_ANY 0x00000003
//
@@ -1196,11 +1194,16 @@ typedef struct
// SMMU mapping for GPU physical allocation decided internally by RM
// This attribute provide an override to RM policy for verification purposes.
//
#define NVOS32_ATTR2_SMMU_ON_GPU 10:8
#define NVOS32_ATTR2_SMMU_ON_GPU 9:8
#define NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT 0x00000000
#define NVOS32_ATTR2_SMMU_ON_GPU_DISABLE 0x00000001
#define NVOS32_ATTR2_SMMU_ON_GPU_ENABLE 0x00000002
// Used for allocating the memory from scanout carveout.
#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT 10:10
#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE 0x00000000
#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE 0x00000001
//
// Make comptag allocation aligned to compression cacheline size.
// Specifying this attribute will make RM allocate comptags worth an entire
@@ -1749,7 +1752,7 @@ typedef struct
// Mappings can have restricted permissions (read-only, write-only). Some
// RM implementations may choose to ignore these flags, or they may work
// only for certain memory spaces (system, AGP, video memory); in such cases,
// only for certain memory spaces (system, video memory); in such cases,
// you may get a read/write mapping even if you asked for a read-only or
// write-only mapping.
#define NVOS33_FLAGS_ACCESS 1:0
@@ -2305,6 +2308,8 @@ typedef struct
NvU8 bForcePowerStateFail;
NvU32 errorStatus; // [OUT] To tell client if there is bubble up errors
NvU32 fastBootPowerState;
NvU8 reserved;
NvU8 reserved2;
} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS;
/***************************************************************************\
@@ -2463,21 +2468,32 @@ typedef struct {
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE 0x0
typedef enum
{
PB_SIZE_4KB = 0,
PB_SIZE_8KB,
PB_SIZE_16KB,
PB_SIZE_32KB,
PB_SIZE_64KB
} ChannelPBSize;
typedef struct
{
NvV32 channelInstance; // One of the n channel instances of a given channel type.
// Note that core channel has only one instance
// while all others have two (one per head).
NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer
NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications
NvU32 offset; // Initial offset for put/get, usually zero.
NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs
NvV32 channelInstance; // One of the n channel instances of a given channel type.
// Note that core channel has only one instance
// while all others have two (one per head).
NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer
NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications
NvU32 offset; // Initial offset for put/get, usually zero.
NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs
NvU32 flags;
NvU32 flags;
ChannelPBSize channelPBSize; // Size of Push Buffer requested by client (allowed values in enum)
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001
NvU32 subDeviceId; // One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel in the pushbuffer stream (via SSDM method)
} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS;
typedef struct

5
src/common/sdk/nvidia/inc/rs_access.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,7 +59,8 @@
#define RS_ACCESS_DUP_OBJECT 0U
#define RS_ACCESS_NICE 1U
#define RS_ACCESS_DEBUG 2U
#define RS_ACCESS_COUNT 3U
#define RS_ACCESS_PERFMON 3U
#define RS_ACCESS_COUNT 4U
/****************************************************************************/