mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-04-26 17:29:11 +00:00
565.57.01
This commit is contained in:
Bernhard Stoeckner
@@ -146,6 +146,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
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* NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
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*
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* This command returns the mapping of PCE's for the given LCE.
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* The pceMask is local to the CE shim that ceEngineType belongs to.
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*
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* ceEngineType
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* This parameter specifies the copy engine type
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@@ -159,12 +160,6 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
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* NV_ERR_INVALID_ARGUMENT
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*/
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/*
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* The pceMask is local to the CE shim that ceEngineType belongs to.
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*/
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#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U)
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@@ -236,18 +231,6 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_GENERIC
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*/
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/*
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* This command updates the PCE-LCE mappings for one CE shim. On
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* GPUs with multiple CE shims, this interface must be called for
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* each shim.
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*
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* shimInstance [IN]
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* Specify which CE shim instance to operate on.
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*/
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#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
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@@ -270,13 +253,9 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
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*
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* An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be
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* set in stubbedCeMask.
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*/
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/*
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*
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* This function operates on all CE shims.
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*/
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#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)
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@@ -360,7 +339,6 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
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typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS;
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/*
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* NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO
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*
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@@ -439,11 +417,15 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
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NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3,
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NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4,
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NV2080_CTRL_CE_LCE_TYPE_C2C = 5,
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NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = 6,
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NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = 7,
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NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = 8,
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NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = 9,
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} NV2080_CTRL_CE_LCE_TYPE;
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/*
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* NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE
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*
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*
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* This command queries the PCE config required for the specified LCE type.
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*
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* [in] lceType
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@@ -497,6 +479,24 @@ typedef struct NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS {
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NvU32 shimInstance;
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} NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS;
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/*
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* NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED
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*
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* This command returns whether a given global LCE index is enabled for decomp workloads.
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* It has to be given a global LCE index (cannot support shim local LCE ID)
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*
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* [in] lceIndex
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* [out] bDecompEnabled
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* Returns NV_TRUE if LCE is enabled for decompression, else returns NV_FALSE
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*/
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#define NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED (0x20802a12) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID (0x12U)
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typedef struct NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS {
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NvU32 lceIndex;
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NvBool bDecompEnabled;
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} NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS;
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/* _ctrl2080ce_h_ */
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -39,36 +39,9 @@
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/*
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* NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
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*
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* sramLastClearedTimestamp [out]
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* dramLastClearedTimestamp [out]
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* unix-epoch based timestamp. These fields indicate when the error counters
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* were last cleared by the user.
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*
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* sramErrorCounts [out]
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* dramErrorCounts [out]
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* Aggregate error counts for SRAM and DRAM
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*/
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#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
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typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
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NvU32 sramLastClearedTimestamp;
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NvU32 dramLastClearedTimestamp;
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NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8);
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NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8);
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NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8);
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NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8);
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} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
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#define NV2080_CTRL_CMD_ECC_GET_ECI_COUNTERS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID" */
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/*
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* NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS
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*
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* sramParityUncorrectedUnique [out]
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* sramSecDedUncorrectedUnique [out]
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* sramCorrectedTotal [out]
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* sramCorrectedUnique [out]
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* dramUncorrectedTotal [out]
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* dramCorrectedTotal [out]
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* Aggregate error counts for SRAM and DRAM.
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@@ -88,12 +61,12 @@ typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
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* Boolean flag which is set if SRAM error threshold was exceeded
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*/
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#define NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID (0x1U)
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#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
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typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
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typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8);
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NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8);
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NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotal, 8);
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NV_DECLARE_ALIGNED(NvU64 sramCorrectedUnique, 8);
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NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8);
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NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8);
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@@ -106,7 +79,7 @@ typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8);
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NvBool sramErrorThresholdExceeded;
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} NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS;
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} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
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/*
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* NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
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@@ -124,9 +97,9 @@ typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
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* dramUncTot [out]:
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* total uncorrectable DRAM error count
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*/
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#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803402U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x2U)
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#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8);
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@@ -481,33 +481,6 @@ typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 gpuVirtAddress, 8);
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} NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS;
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/*
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* Note: Returns Zeros if no System carveout address info
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*
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* NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO
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*
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* This command returns FB carveout address space information
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*
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* StartAddr
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* Returns the system memory address of the start of carveout space.
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* SpaceSize
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* Returns the size of carveout space.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO (0x2080130bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID" */
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#define NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID (0xBU)
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typedef struct NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO {
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NV_DECLARE_ALIGNED(NvU64 StartAddr, 8);
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NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8);
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} NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO;
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/*
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* NV2080_CTRL_FB_CMD_GET_CALIBRATION_LOCK_FAILED
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*
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@@ -680,161 +653,6 @@ typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS {
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#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO (0x00000000U)
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#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES (0x00000001U)
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/*
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2 instead)
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*
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* These commands access the cache allocation policy on a specific
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* engine, if supported.
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*
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* engine
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* Specifies the target engine. Possible values are defined in
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* NV2080_ENGINE_TYPE.
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* allocPolicy
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* Specifies the read/write allocation policy of the cache on the specified
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* engine. Possible values are defined in
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS and
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES.
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*
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*/
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typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS {
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NvU32 engine;
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NvU32 allocPolicy;
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} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS;
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/* valid values for allocPolicy */
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U)
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/*
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* NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY
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*
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* This command is deprecated.
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* Use NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 instead.
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*
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* This command sets the state of the cache allocation policy on a specific
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* engine, if supported.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0xFU)
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typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS;
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/*
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM
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*
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* These commands access the cache allocation policy on a specific
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* client, if supported.
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*
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* count
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* Specifies the number of entries in entry.
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* entry
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* Specifies an array of allocation policy entries.
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*
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY
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*
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* clients
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* Specifies the target client. Possible values are defined in
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* NV2080_CLIENT_TYPE_*.
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* allocPolicy
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* Specifies the read/write allocation policy of the cache on the specified
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* engine. Possible values are defined in
|
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS and
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES.
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*
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* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE
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*
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* Specifies the maximum number of allocation policy entries allowed
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*/
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE 11U
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typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY {
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NvU32 client;
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NvU32 allocPolicy;
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} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY;
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typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
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NvU32 count;
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NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY entry[NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE];
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} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
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/* valid values for allocPolicy */
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS 0:0
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_DISABLE (0x00000000U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ENABLE (0x00000001U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW 1:1
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_NO (0x00000000U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_YES (0x00000001U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES 2:2
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_DISABLE (0x00000000U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ENABLE (0x00000001U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW 3:3
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_NO (0x00000000U)
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#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_YES (0x00000001U)
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/*
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* NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2
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*
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* This command sets the state of the cache allocation policy on a specific
|
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* engine, if supported.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x18U)
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typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
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/*
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* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead)
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*
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* This command gets the state of the cache allocation policy on a specific
|
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* engine, if supported.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0x12U)
|
||||
|
||||
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2
|
||||
*
|
||||
* This command gets the state of the cache allocation policy on a specific
|
||||
* engine, if supported.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x19U)
|
||||
|
||||
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_IS_KIND
|
||||
*
|
||||
@@ -908,7 +726,7 @@ typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_C
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U)
|
||||
|
||||
@@ -985,65 +803,6 @@ typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS {
|
||||
#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED (0x00000002U)
|
||||
#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE (0x00000003U)
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY
|
||||
*
|
||||
* These commands access the cache promotion policy on a specific
|
||||
* engine, if supported by the hardware.
|
||||
*
|
||||
* Cache promotion refers to the GPU promoting a memory read to a larger
|
||||
* size to preemptively fill the cache so future reads to nearby memory
|
||||
* addresses will hit in the cache.
|
||||
*
|
||||
* engine
|
||||
* Specifies the target engine. Possible values are defined in
|
||||
* NV2080_ENGINE_TYPE.
|
||||
* promotionPolicy
|
||||
* Specifies the promotion policy of the cache on the specified
|
||||
* engine. Possible values are defined by
|
||||
* NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_*. These values are in terms
|
||||
* of the hardware cache line size.
|
||||
*
|
||||
*/
|
||||
typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS {
|
||||
NvU32 engine;
|
||||
NvU32 promotionPolicy;
|
||||
} NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS;
|
||||
|
||||
/* valid values for promotionPolicy */
|
||||
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_NONE (0x00000000U)
|
||||
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_QUARTER (0x00000001U)
|
||||
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_HALF (0x00000002U)
|
||||
#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_FULL (0x00000003U)
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY
|
||||
*
|
||||
* This command sets the cache promotion policy on a specific engine, if
|
||||
* supported by the hardware.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY (0x20801316U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x16" */ // Deprecated, removed form RM
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY
|
||||
*
|
||||
* This command gets the cache promotion policy on a specific engine, if
|
||||
* supported by the hardware.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY (0x20801317U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x17" */ // Deprecated, removed form RM
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO
|
||||
*
|
||||
@@ -1086,9 +845,9 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS {
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U
|
||||
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U
|
||||
|
||||
typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
|
||||
|
||||
@@ -2391,6 +2150,21 @@ typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS {
|
||||
NvU32 sysl2LtcEnMask;
|
||||
} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS;
|
||||
|
||||
/*!
|
||||
* Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK.
|
||||
*/
|
||||
typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS {
|
||||
/*!
|
||||
* [IN]: physical/local SYS index.
|
||||
*/
|
||||
NvU32 sysIdx;
|
||||
/*!
|
||||
* [OUT]: physical/local lts mask.
|
||||
* Note: this lts mask should be flattened out within a sys chiplet
|
||||
*/
|
||||
NV_DECLARE_ALIGNED(NvU64 sysl2LtsEnMask, 8);
|
||||
} NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS;
|
||||
|
||||
/*!
|
||||
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PAC_MASK.
|
||||
*/
|
||||
@@ -2456,6 +2230,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS {
|
||||
#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU
|
||||
#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK 0xFU
|
||||
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U
|
||||
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK 0x11U
|
||||
|
||||
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
|
||||
NvU16 queryType;
|
||||
@@ -2479,6 +2254,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
|
||||
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS pac;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS sysl2Lts, 8);
|
||||
} queryParams;
|
||||
} NV2080_CTRL_FB_FS_INFO_QUERY;
|
||||
|
||||
@@ -2884,4 +2660,31 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_OWNER_INFO fbBlockInfo[NV2080_CTRL_CMD_FB_STATS_MAX_OWNER], 8);
|
||||
} NV2080_CTRL_CMD_FB_STATS_GET_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO
|
||||
*
|
||||
* This command returns the GPU static BAR1 Info
|
||||
* This is for general P2P DMA. NV50_P2P is for GPU P2P.
|
||||
*
|
||||
* @params [OUT] NvBool bStaticBar1Enabled:
|
||||
* This field indicates the static BAR1 mode is enabled. All the following fields are valid
|
||||
* only if static BAR1 mode is enabled.
|
||||
* @params [OUT] NvU64 staticBar1Size:
|
||||
* This field indicates the size of the static BAR1.
|
||||
*
|
||||
* Possible status values returned are
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO (0x20801354U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID (0x54U)
|
||||
|
||||
typedef struct NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS {
|
||||
NvBool bStaticBar1Enabled;
|
||||
NV_DECLARE_ALIGNED(NvU64 staticBar1Size, 8);
|
||||
} NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS;
|
||||
|
||||
/* _ctrl2080fb_h_ */
|
||||
|
||||
@@ -114,10 +114,7 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
|
||||
|
||||
/* valid minor revision extended values */
|
||||
@@ -1128,7 +1125,10 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
|
||||
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001FU)
|
||||
#define NV2080_CTRL_GPU_ECC_UNIT_GSP (0x0000001DU)
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000024U)
|
||||
|
||||
|
||||
|
||||
@@ -1861,13 +1861,11 @@ typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS {
|
||||
NvU32 ipVersion;
|
||||
} NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U)
|
||||
#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U)
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT
|
||||
@@ -2584,37 +2582,39 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8);
|
||||
} NV2080_CTRL_GPU_SET_PARTITION_INFO;
|
||||
|
||||
#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID
|
||||
#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU
|
||||
#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U
|
||||
#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U
|
||||
#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U
|
||||
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU
|
||||
#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U
|
||||
#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID
|
||||
#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU
|
||||
#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U
|
||||
#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U
|
||||
#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U
|
||||
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU
|
||||
#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U
|
||||
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 0x00000006U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 0x00000007U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 8U
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U
|
||||
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 40U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U
|
||||
|
||||
// TODO XXX Bug 2657907 Remove these once clients update
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL))
|
||||
@@ -4328,11 +4328,11 @@ typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
|
||||
} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_GET_VF_CAPS
|
||||
* NV2080_CTRL_CMD_GPU_GET_VF_CAPS
|
||||
*
|
||||
* This command will return the MSIX capabilities for virtual function
|
||||
* Parameters:
|
||||
*
|
||||
*
|
||||
* gfid [IN]
|
||||
* The GPU function identifier for a given VF BDF
|
||||
*
|
||||
@@ -4357,6 +4357,33 @@ typedef struct NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS {
|
||||
NV2080_VF_MSIX_CAPS vfMsixCap;
|
||||
} NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION
|
||||
*
|
||||
* Gets the recovery action needed for the device after a failure.
|
||||
*
|
||||
* action [OUT]
|
||||
* Returns the recovery action needed.
|
||||
*
|
||||
* Possible status return values are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION (0x208001b2U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef enum NV2080_CTRL_GPU_RECOVERY_ACTION {
|
||||
NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = 0,
|
||||
NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = 1,
|
||||
NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = 2,
|
||||
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3,
|
||||
} NV2080_CTRL_GPU_RECOVERY_ACTION;
|
||||
|
||||
#define NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID (0xB2U)
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS {
|
||||
NV2080_CTRL_GPU_RECOVERY_ACTION action;
|
||||
} NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_GPU_GET_FIPS_STATUS
|
||||
*
|
||||
|
||||
@@ -309,7 +309,6 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
|
||||
|
||||
@@ -330,7 +329,6 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
|
||||
|
||||
@@ -834,7 +832,8 @@ typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 8,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = 8,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 9,
|
||||
} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS;
|
||||
|
||||
/*
|
||||
@@ -1909,4 +1908,27 @@ typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS {
|
||||
NvU32 numGfxTpc;
|
||||
} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION
|
||||
*
|
||||
* This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine
|
||||
*
|
||||
* promoType[IN]
|
||||
* This parameter specifies what kind of sector promotion to perform
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_GR_SET_LG_SECTOR_PROMOTION (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef enum NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE {
|
||||
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_NONE = 0,
|
||||
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_64B = 1,
|
||||
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_128B = 2,
|
||||
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE;
|
||||
|
||||
#define NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID (0x3BU)
|
||||
|
||||
typedef struct NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS {
|
||||
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE promoType;
|
||||
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS;
|
||||
|
||||
/* _ctrl2080gr_h_ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -87,6 +87,10 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
|
||||
*
|
||||
* This command reports the current GSP-RM heap usage statistics.
|
||||
*
|
||||
* gfid
|
||||
* The gfid that's under query: When gfid = 0, it will report the stats of PF.
|
||||
* Otherwise, it will report stats for RM task's memory consumption associated
|
||||
* with a given gfid.
|
||||
* managedSize
|
||||
* The total size in bytes of the underlying heap. Note that not all memory
|
||||
* will be allocatable, due to fragmentation and memory allocator/tracking
|
||||
@@ -125,6 +129,7 @@ typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT {
|
||||
#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U)
|
||||
|
||||
typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS {
|
||||
NvU32 gfid;
|
||||
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8);
|
||||
|
||||
@@ -750,8 +750,9 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
|
||||
NvU32 groupId;
|
||||
NvU32 ginTargetId;
|
||||
NvU32 deviceBroadcastPriBase;
|
||||
NvU32 groupLocalInstanceId;
|
||||
} NV2080_CTRL_INTERNAL_DEVICE_INFO;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 512
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
@@ -1351,6 +1352,12 @@ typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS {
|
||||
* pbTargetAperture [IN]
|
||||
* Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM)
|
||||
*
|
||||
* channelPBSize [IN]
|
||||
* Indicates the PushBuffer size requested by client
|
||||
*
|
||||
* subDeviceId [IN]
|
||||
* One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel
|
||||
* in the pushbuffer stream (via SSDM method)
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
@@ -1365,6 +1372,8 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
|
||||
NvU32 channelInstance;
|
||||
NvBool valid;
|
||||
NvU32 pbTargetAperture;
|
||||
NvU32 channelPBSize;
|
||||
NvU32 subDeviceId;
|
||||
} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
|
||||
|
||||
/*!
|
||||
@@ -4024,36 +4033,46 @@ typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
|
||||
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
|
||||
* NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
|
||||
*
|
||||
* This structure provides the params for starting GPU Fabric Probe
|
||||
*
|
||||
* tracepointMask[IN]
|
||||
* - tracepoint selection filter
|
||||
* bufferAddr[IN]
|
||||
* - physical address of tracing buffer for VGPU
|
||||
* bufferSize[IN]
|
||||
* - size of gsp side logging buffer
|
||||
* bufferWatermark[IN]
|
||||
* - entry threshold for GSP to issue RPC of logged entries to kernel RM
|
||||
* bStart[IN]
|
||||
* - if true, start tracing. if false, stop tracing.
|
||||
* flag[IN]
|
||||
* - indicates which operation to perform
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U)
|
||||
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID (0xE3U)
|
||||
|
||||
typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS {
|
||||
typedef struct NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
|
||||
NvU32 bufferSize;
|
||||
NvU32 bufferWatermark;
|
||||
NvBool bStart;
|
||||
} NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS;
|
||||
NV_DECLARE_ALIGNED(NvU64 bufferAddr, 8);
|
||||
NvU32 bufferSize;
|
||||
NvU32 bufferWatermark;
|
||||
NvU8 flag;
|
||||
} NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS;
|
||||
|
||||
/*!
|
||||
* Macros for INTERNAL_CONTROL_GSP_TRACE flags for specific operation.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST 0x00U
|
||||
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST 0x01U
|
||||
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP 0x02U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE
|
||||
* NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE
|
||||
*
|
||||
* This command is used to start GSP-RM trace tool.
|
||||
* This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
|
||||
* This command accepts NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES
|
||||
@@ -4143,7 +4162,26 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS {
|
||||
NvU32 attribute;
|
||||
NvU32 value;
|
||||
} NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR
|
||||
*
|
||||
* @brief NVIDIA RTX 5000 (GP180 SKU500) Windows-specific war
|
||||
* to pull gpio19 (stereo pin) low for bug3362661.
|
||||
*
|
||||
* [in] bApplyStereoPinAlwaysHiWar
|
||||
* If need to driver stereo pin(GPIO19) low(_IO_INPUT)
|
||||
*
|
||||
* @return NV_OK on success
|
||||
* @return NV_ERR_ otherwise
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID (0xEDU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS {
|
||||
NvBool bApplyStereoPinAlwaysHiWar;
|
||||
} NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR (0x20800aed) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM
|
||||
*
|
||||
@@ -4154,7 +4192,7 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS {
|
||||
*
|
||||
* @return NV_OK
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID (0x79U)
|
||||
|
||||
@@ -4162,4 +4200,490 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS {
|
||||
NvU32 maxHshubs;
|
||||
} NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS;
|
||||
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_MODE
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID (0x14U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS {
|
||||
NvU32 rasterSyncDecodeMode;
|
||||
} NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE (0x20800a14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS
|
||||
*
|
||||
* This is an internal command sent from kernel-RM to physical-RM to retrieve GPU PF BAR1 SPA
|
||||
* BAR1 SPA is required for BAR1 mapping in Direct NIC case for DMA(Direct Memory Access) of FB.
|
||||
*
|
||||
* spaValue[OUT]
|
||||
* - BAR1 SPA of GPU PF
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID (0xEEU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 spaValue, 8);
|
||||
} NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA (0x20800aee) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER
|
||||
*
|
||||
* This command is used to enable RM NVLink enabled peer state.
|
||||
* Note: This just updates the RM state. To reflect the state in the registers,
|
||||
* use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER
|
||||
*
|
||||
* [in] peerMask
|
||||
* Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled
|
||||
* [in] bEnable
|
||||
* Whether the bit needs to be set or unset
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* If the USE_NVLINK_PEER bit was enabled successfully
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* If NVLINK is not supported on the chip, or
|
||||
* If unsetting USE_NVLINK_PEER bit is not supported
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER (0x20800a21U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x21U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
|
||||
NvU32 peerMask;
|
||||
NvBool bEnable;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
|
||||
|
||||
/*
|
||||
* NVLINK Link states
|
||||
* These should ALWAYS match the nvlink core library defines in nvlink.h
|
||||
*/
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF 0x00U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS 0x01U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE 0x02U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT 0x03U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY 0x04U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL 0x05U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT 0x06U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET 0x07U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT 0x0FU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE 0x10U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN 0x11U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP 0x12U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 0x13U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE 0x14U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE 0x15U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE 0x16U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE 0x17U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL 0x1AU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI 0x1CU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU
|
||||
#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID 0xFFU
|
||||
|
||||
/*
|
||||
* NVLINK TX Sublink states
|
||||
* These should ALWAYS match the nvlink core library defines in nvlink.h
|
||||
*/
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE 0x08U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY 0x0AU
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ 0x0BU
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN 0x0CU
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS 0x0DU
|
||||
|
||||
/*
|
||||
* NVLINK RX Sublink states
|
||||
* These should ALWAYS match the nvlink core library defines in nvlink.h
|
||||
*/
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL 0x08U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM 0x09U
|
||||
|
||||
/*
|
||||
* Link training seed values
|
||||
* These should ALWAYS match the values defined in nvlink.h
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM 6U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE (0x7U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM + 1" */
|
||||
|
||||
// NVLINK callback types
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE 0x00U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE 0x01U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE 0x02U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE 0x03U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE 0x04U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE 0x05U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE 0x06U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE 0x07U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN 0x0BU
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE 0x0CU
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD 0x0DU
|
||||
|
||||
/*
|
||||
* Structure to store the GET_DL_MODE callback params.
|
||||
* mode
|
||||
* The current Nvlink DL mode
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS {
|
||||
NvU32 mode;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback OFF params
|
||||
* seedData
|
||||
* The output seed data
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS {
|
||||
NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE];
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback PRE_HS params
|
||||
* remoteDeviceType
|
||||
* The input remote Device Type
|
||||
* ipVerDlPl
|
||||
* The input DLPL version
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS {
|
||||
NvU32 remoteDeviceType;
|
||||
NvU32 ipVerDlPl;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params
|
||||
* seedData[]
|
||||
* The input seed data
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS {
|
||||
NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE];
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the Nvlink Remote and Local SID info
|
||||
* remoteSid
|
||||
* The output remote SID
|
||||
* remoteDeviceType
|
||||
* The output remote Device Type
|
||||
* remoteLinkId
|
||||
* The output remote link ID
|
||||
* localSid
|
||||
* The output local SID
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO {
|
||||
NV_DECLARE_ALIGNED(NvU64 remoteSid, 8);
|
||||
NvU32 remoteDeviceType;
|
||||
NvU32 remoteLinkId;
|
||||
NV_DECLARE_ALIGNED(NvU64 localSid, 8);
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params
|
||||
* bInitnegotiateConfigGood
|
||||
* The output bool if the config is good
|
||||
* remoteLocalSidInfo
|
||||
* The output structure containing the Nvlink Remote/Local SID info
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS {
|
||||
NvBool bInitnegotiateConfigGood;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params
|
||||
* bPollDone
|
||||
* The output bool if the polling has finished
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS {
|
||||
NvBool bPollDone;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink state to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
* linkMode
|
||||
* The input link mode to be set for the callback
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
NvU32 linkMode;
|
||||
union {
|
||||
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS linkModeOffParams;
|
||||
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS linkModePreHsParams;
|
||||
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS linkModeInitPhase1Params;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8);
|
||||
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams;
|
||||
} linkModeParams;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_TL_MODE callback params.
|
||||
* mode
|
||||
* The current Nvlink TL mode
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS {
|
||||
NvU32 mode;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_TL_LINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink mode to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_RX/TX_SUBLINK_MODE callback params
|
||||
* sublinkMode
|
||||
* The current Sublink mode
|
||||
* sublinkSubMode
|
||||
* The current Sublink sub mode
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS {
|
||||
NvU32 sublinkMode;
|
||||
NvU32 sublinkSubMode;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_TL_LINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink mode to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_RX_SUBLINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink mode to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_RX_SUBLINK_DETECT callback params
|
||||
* laneRxdetStatusMask
|
||||
* The output RXDET per-lane status mask
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS {
|
||||
NvU32 laneRxdetStatusMask;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_RX_DETECT callback params
|
||||
* bSync
|
||||
* The input bSync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS {
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the RD_WR_DISCOVERY_TOKEN callback params
|
||||
* ipVerDlPl
|
||||
* The input DLPL version
|
||||
* token
|
||||
* The output token
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS {
|
||||
NvU32 ipVerDlPl;
|
||||
NV_DECLARE_ALIGNED(NvU64 token, 8);
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_UPHY_LOAD callback params
|
||||
* bUnlocked
|
||||
* The output unlocked boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS {
|
||||
NvBool bUnlocked;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the Union of Callback params
|
||||
* type
|
||||
* The input type of callback to be executed
|
||||
*/
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE {
|
||||
NvU8 type;
|
||||
union {
|
||||
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8);
|
||||
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8);
|
||||
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8);
|
||||
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8);
|
||||
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS getRxSublinkDetect;
|
||||
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS setRxSublinkDetect;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8);
|
||||
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS getUphyLoad;
|
||||
} callbackParams;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK
|
||||
*
|
||||
* Generic NvLink callback RPC to route commands to GSP
|
||||
*
|
||||
* [In] linkdId
|
||||
* ID of the link to be used
|
||||
* [In/Out] callBackType
|
||||
* Callback params
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x24U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS {
|
||||
NvU32 linkId;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE callbackType, 8);
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK (0x20800a24U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID
|
||||
*
|
||||
* Update Remote and Local Sid info via GSP
|
||||
*
|
||||
* [In] linkId
|
||||
* ID of the link to be used
|
||||
* [Out] remoteLocalSidInfo
|
||||
* The output structure containing the Nvlink Remote/Local SID info
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x25U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS {
|
||||
NvU32 linkId;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x20800a25U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED
|
||||
*
|
||||
* Returns if ALI is enabled
|
||||
*
|
||||
* [Out] bEnableAli
|
||||
* Output boolean for ALI enablement
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x29U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS {
|
||||
NvBool bEnableAli;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED (0x20800a29U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET 0x1U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX
|
||||
*
|
||||
* Generic Hshub Mux Update RPC to route commands to GSP
|
||||
*
|
||||
* [In] updateType
|
||||
* HSHUB Mux update type to program or reset Mux
|
||||
* [In] bSysMem
|
||||
* Boolean to differentiate between sysmen and peer mem
|
||||
* [In] peerMask
|
||||
* Mask of peer IDs. Only parsed when bSysMem is false
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x42U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
|
||||
NvBool updateType;
|
||||
NvBool bSysMem;
|
||||
NvU32 peerMask;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX (0x20800a42U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER
|
||||
*
|
||||
* Performs all the necessary actions required before setting a peer on NVLink
|
||||
*
|
||||
* [In] peerId
|
||||
* Peer ID which will be set on NVLink
|
||||
* [In] peerLinkMask
|
||||
* Mask of links that connects the given peer
|
||||
* [In] bNvswitchConn
|
||||
* Is the GPU connected to NVSwitch
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x4EU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
|
||||
NvU32 peerId;
|
||||
NvU32 peerLinkMask;
|
||||
NvBool bEgmPeer;
|
||||
NvBool bNvswitchConn;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER (0x20800a4eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER
|
||||
*
|
||||
* Performs all the necessary actions required after setting a peer on NVLink
|
||||
*
|
||||
* [In] peerMask
|
||||
* Mask of Peer IDs which has been set on NVLink
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x50U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
|
||||
NvU32 peerMask;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER (0x20800a50U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/* ctrl2080internal_h */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -77,6 +77,10 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
|
||||
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 (0x00000180)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 (0x00000190)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 (0x000001A0)
|
||||
|
||||
|
||||
|
||||
/* valid ARCHITECTURE_T23X implementation values */
|
||||
@@ -109,6 +113,25 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B)
|
||||
|
||||
|
||||
/* valid ARCHITECTURE_GH10x implementation values */
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 (0x00000000)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC (0x00000001)
|
||||
|
||||
/* valid ARCHITECTURE_AD10x implementation values */
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 (0x00000000)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 (0x00000001)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 (0x00000001)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 (0x00000002)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 (0x00000003)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 (0x00000004)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 (0x00000006)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 (0x00000007)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B (0x0000000B)
|
||||
/* valid ARCHITECTURE_GB10x implementation values */
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 (0x00000000)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
|
||||
|
||||
|
||||
|
||||
/* Valid Chip sub revisions */
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
|
||||
@@ -166,52 +189,6 @@ typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS
|
||||
*
|
||||
* This command is used to allow clients to query whether hostclk slowdown is
|
||||
* disabled.
|
||||
*
|
||||
* bDisabled
|
||||
* This parameter will hold the status of hostclk slowdown
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS (0x20801708) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x8U)
|
||||
|
||||
typedef struct NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
|
||||
NvBool bDisabled;
|
||||
} NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS
|
||||
*
|
||||
* This command is used to allow clients to disable/enable hostclk slowdown.
|
||||
*
|
||||
* bDisable
|
||||
* When this parameter is set to TRUE, RM should disable hostclk slowdown.
|
||||
* If it is set to FALSE, RM will attempt to enable hostclk slowdown, but
|
||||
* in this case, slowdown is NOT guaranteed to be enabled since there may
|
||||
* be other reason (like regkey) preventing slowdown.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS (0x20801709) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x9U)
|
||||
|
||||
typedef struct NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
|
||||
NvBool bDisable;
|
||||
} NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP
|
||||
*
|
||||
|
||||
@@ -104,6 +104,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
|
||||
* Set if L3 is a supported power state on this subdevice/link, NV_FALSE otherwise.
|
||||
* VALID
|
||||
* Set if this link is supported on this subdevice, NV_FALSE otherwise. This field is used for *per-link* caps only and NOT for global caps.
|
||||
* UNCONTAINED_ERROR_RECOVERY
|
||||
* Set if this GPU supports resetless recovery from uncontained packet errors.
|
||||
*
|
||||
*/
|
||||
|
||||
@@ -121,6 +123,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
|
||||
#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2 1:0x04
|
||||
#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3 1:0x08
|
||||
#define NV2080_CTRL_NVLINK_CAPS_VALID 1:0x10
|
||||
#define NV2080_CTRL_NVLINK_CAPS_UNCONTAINED_ERROR_RECOVERY 1:0x20
|
||||
|
||||
/*
|
||||
* Size in bytes of nvlink caps table. This value should be one greater
|
||||
@@ -135,10 +138,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U)
|
||||
@@ -146,10 +146,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
|
||||
*
|
||||
@@ -377,10 +374,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005U)
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U)
|
||||
@@ -389,10 +383,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005U)
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U)
|
||||
@@ -986,8 +977,6 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
|
||||
|
||||
#define NV2080_CTRL_NVLINK_COUNTERS_MAX 107U
|
||||
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS 2U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ 28
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_V2_GROUP(i) ((i) / 64)
|
||||
@@ -1992,35 +1981,6 @@ typedef struct NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS {
|
||||
NvBool bLockPowerMode;
|
||||
} NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER
|
||||
*
|
||||
* This command is used to enable RM NVLink enabled peer state.
|
||||
* Note: This just updates the RM state. To reflect the state in the registers,
|
||||
* use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER
|
||||
*
|
||||
* [in] peerMask
|
||||
* Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled
|
||||
* [in] bEnable
|
||||
* Whether the bit needs to be set or unset
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* If the USE_NVLINK_PEER bit was enabled successfully
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* If NVLINK is not supported on the chip, or
|
||||
* If unsetting USE_NVLINK_PEER bit is not supported
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER (0x20803017U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x17U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
|
||||
NvU32 peerMask;
|
||||
NvBool bEnable;
|
||||
} NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U
|
||||
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
|
||||
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U
|
||||
@@ -2068,433 +2028,9 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
|
||||
NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS];
|
||||
} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
|
||||
|
||||
/*
|
||||
* NVLINK Link states
|
||||
* These should ALWAYS match the nvlink core library defines in nvlink.h
|
||||
*/
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_OFF 0x00U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_HS 0x01U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_SAFE 0x02U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_FAULT 0x03U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_RECOVERY 0x04U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_FAIL 0x05U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_DETECT 0x06U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_RESET 0x07U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT 0x0FU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_LANE_DISABLE 0x10U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN 0x11U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP 0x12U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE1 0x13U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_INITNEGOTIATE 0x14U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE 0x15U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_INITOPTIMIZE 0x16U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE 0x17U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_INITTL 0x1AU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_ALI 0x1CU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU
|
||||
#define NV2080_NVLINK_CORE_LINK_STATE_INVALID 0xFFU
|
||||
|
||||
/*
|
||||
* NVLINK TX Sublink states
|
||||
* These should ALWAYS match the nvlink core library defines in nvlink.h
|
||||
*/
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE 0x08U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY 0x0AU
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ 0x0BU
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN 0x0CU
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS 0x0DU
|
||||
|
||||
/*
|
||||
* NVLINK RX Sublink states
|
||||
* These should ALWAYS match the nvlink core library defines in nvlink.h
|
||||
*/
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL 0x08U
|
||||
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM 0x09U
|
||||
|
||||
/*
|
||||
* Link training seed values
|
||||
* These should ALWAYS match the values defined in nvlink.h
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_MAX_SEED_NUM 6U
|
||||
#define NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE (0x7U) /* finn: Evaluated from "NV2080_CTRL_NVLINK_MAX_SEED_NUM + 1" */
|
||||
|
||||
// NVLINK callback types
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE 0x00U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE 0x01U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE 0x02U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE 0x03U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE 0x04U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE 0x05U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE 0x06U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE 0x07U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN 0x0BU
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE 0x0CU
|
||||
#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD 0x0DU
|
||||
|
||||
/*
|
||||
* Structure to store the GET_DL_MODE callback params.
|
||||
* mode
|
||||
* The current Nvlink DL mode
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS {
|
||||
NvU32 mode;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback OFF params
|
||||
* seedData
|
||||
* The output seed data
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS {
|
||||
NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE];
|
||||
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback PRE_HS params
|
||||
* remoteDeviceType
|
||||
* The input remote Device Type
|
||||
* ipVerDlPl
|
||||
* The input DLPL version
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS {
|
||||
NvU32 remoteDeviceType;
|
||||
NvU32 ipVerDlPl;
|
||||
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params
|
||||
* seedData[]
|
||||
* The input seed data
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS {
|
||||
NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE];
|
||||
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the Nvlink Remote and Local SID info
|
||||
* remoteSid
|
||||
* The output remote SID
|
||||
* remoteDeviceType
|
||||
* The output remote Device Type
|
||||
* remoteLinkId
|
||||
* The output remote link ID
|
||||
* localSid
|
||||
* The output local SID
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO {
|
||||
NV_DECLARE_ALIGNED(NvU64 remoteSid, 8);
|
||||
NvU32 remoteDeviceType;
|
||||
NvU32 remoteLinkId;
|
||||
NV_DECLARE_ALIGNED(NvU64 localSid, 8);
|
||||
} NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params
|
||||
* bInitnegotiateConfigGood
|
||||
* The output bool if the config is good
|
||||
* remoteLocalSidInfo
|
||||
* The output structure containing the Nvlink Remote/Local SID info
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS {
|
||||
NvBool bInitnegotiateConfigGood;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
|
||||
} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params
|
||||
* bPollDone
|
||||
* The output bool if the polling has finished
|
||||
*/
|
||||
typedef struct NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS {
|
||||
NvBool bPollDone;
|
||||
} NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_DL_LINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink state to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
* linkMode
|
||||
* The input link mode to be set for the callback
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
NvU32 linkMode;
|
||||
union {
|
||||
NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS linkModeOffParams;
|
||||
NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS linkModePreHsParams;
|
||||
NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS linkModeInitPhase1Params;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8);
|
||||
NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams;
|
||||
} linkModeParams;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_TL_MODE callback params.
|
||||
* mode
|
||||
* The current Nvlink TL mode
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS {
|
||||
NvU32 mode;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_TL_LINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink mode to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_RX/TX_SUBLINK_MODE callback params
|
||||
* sublinkMode
|
||||
* The current Sublink mode
|
||||
* sublinkSubMode
|
||||
* The current Sublink sub mode
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS {
|
||||
NvU32 sublinkMode;
|
||||
NvU32 sublinkSubMode;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_TL_LINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink mode to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_RX_SUBLINK_MODE callback params
|
||||
* mode
|
||||
* The input nvlink mode to set
|
||||
* bSync
|
||||
* The input sync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 mode, 8);
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_RX_SUBLINK_DETECT callback params
|
||||
* laneRxdetStatusMask
|
||||
* The output RXDET per-lane status mask
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS {
|
||||
NvU32 laneRxdetStatusMask;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the SET_RX_DETECT callback params
|
||||
* bSync
|
||||
* The input bSync boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS {
|
||||
NvBool bSync;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the RD_WR_DISCOVERY_TOKEN callback params
|
||||
* ipVerDlPl
|
||||
* The input DLPL version
|
||||
* token
|
||||
* The output token
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS {
|
||||
NvU32 ipVerDlPl;
|
||||
NV_DECLARE_ALIGNED(NvU64 token, 8);
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the GET_UPHY_LOAD callback params
|
||||
* bUnlocked
|
||||
* The output unlocked boolean
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS {
|
||||
NvBool bUnlocked;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store the Union of Callback params
|
||||
* type
|
||||
* The input type of callback to be executed
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_CALLBACK_TYPE {
|
||||
NvU8 type;
|
||||
union {
|
||||
NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8);
|
||||
NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8);
|
||||
NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8);
|
||||
NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8);
|
||||
NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS getRxSublinkDetect;
|
||||
NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS setRxSublinkDetect;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8);
|
||||
NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS getUphyLoad;
|
||||
} callbackParams;
|
||||
} NV2080_CTRL_NVLINK_CALLBACK_TYPE;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK
|
||||
*
|
||||
* Generic NvLink callback RPC to route commands to GSP
|
||||
*
|
||||
* [In] linkdId
|
||||
* ID of the link to be used
|
||||
* [In/Out] callBackType
|
||||
* Callback params
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x19U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS {
|
||||
NvU32 linkId;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_TYPE callbackType, 8);
|
||||
} NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK (0x20803019U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED
|
||||
*
|
||||
* Returns if ALI is enabled
|
||||
*
|
||||
* [Out] bEnableAli
|
||||
* Output boolean for ALI enablement
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x1aU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS {
|
||||
NvBool bEnableAli;
|
||||
} NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED (0x2080301aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID
|
||||
*
|
||||
* Update Remote and Local Sid info via GSP
|
||||
*
|
||||
* [In] linkId
|
||||
* ID of the link to be used
|
||||
* [Out] remoteLocalSidInfo
|
||||
* The output structure containing the Nvlink Remote/Local SID info
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x1bU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS {
|
||||
NvU32 linkId;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
|
||||
} NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x2080301bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U
|
||||
#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET 0x1U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX
|
||||
*
|
||||
* Generic Hshub Mux Update RPC to route commands to GSP
|
||||
*
|
||||
* [In] updateType
|
||||
* HSHUB Mux update type to program or reset Mux
|
||||
* [In] bSysMem
|
||||
* Boolean to differentiate between sysmen and peer mem
|
||||
* [In] peerMask
|
||||
* Mask of peer IDs. Only parsed when bSysMem is false
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x1cU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
|
||||
NvBool updateType;
|
||||
NvBool bSysMem;
|
||||
NvU32 peerMask;
|
||||
} NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX (0x2080301cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER
|
||||
*
|
||||
* Performs all the necessary actions required before setting a peer on NVLink
|
||||
*
|
||||
* [In] peerId
|
||||
* Peer ID which will be set on NVLink
|
||||
* [In] peerLinkMask
|
||||
* Mask of links that connects the given peer
|
||||
* [In] bNvswitchConn
|
||||
* Is the GPU connected to NVSwitch
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1dU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
|
||||
NvU32 peerId;
|
||||
NvU32 peerLinkMask;
|
||||
NvBool bEgmPeer;
|
||||
NvBool bNvswitchConn;
|
||||
} NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER
|
||||
*
|
||||
* Performs all the necessary actions required after setting a peer on NVLink
|
||||
*
|
||||
* [In] peerMask
|
||||
* Mask of Peer IDs which has been set on NVLink
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1eU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
|
||||
NvU32 peerMask;
|
||||
} NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
|
||||
#define NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER (0x2080301eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
|
||||
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U
|
||||
@@ -3333,7 +2869,7 @@ typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS {
|
||||
*
|
||||
* [In] linkId
|
||||
* Id of the link on which error occured
|
||||
* [In] bIsGpuDegraded
|
||||
* [Out] bIsGpuDegraded
|
||||
* Boolean to track corresponding GPU is degraded or not
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x41U)
|
||||
@@ -3484,6 +3020,7 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH 496U
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_DATA {
|
||||
@@ -3513,7 +3050,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS {
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
*
|
||||
* NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS
|
||||
@@ -3609,15 +3145,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS {
|
||||
NvU8 slot_index;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTWE (0x2080305dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID (0x5dU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE (0x2080305eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID (0x5eU)
|
||||
@@ -3663,28 +3190,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS {
|
||||
NvU16 admin_mtu;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCIA (0x20803063U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID (0x63U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 slot_index;
|
||||
NvU8 module;
|
||||
NvBool pnv;
|
||||
NvBool l;
|
||||
NvU16 device_address;
|
||||
NvU8 page_number;
|
||||
NvU8 i2c_device_address;
|
||||
NvU16 size;
|
||||
NvU8 bank_number;
|
||||
NvBool passwd_length;
|
||||
NvU32 password;
|
||||
NvU32 dword[32];
|
||||
NvU32 password_msb;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP (0x20803064U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID (0x64U)
|
||||
@@ -4109,6 +3614,136 @@ typedef struct NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS {
|
||||
NvU8 moduleId;
|
||||
} NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS;
|
||||
|
||||
/*
|
||||
* Structure to store UPHY cmd data.
|
||||
* laneId
|
||||
* Lane ID for specified link
|
||||
* address
|
||||
* Desired address for read
|
||||
*/
|
||||
typedef struct NV2080_CTRL_NVLINK_UPHY_CLN_CMD {
|
||||
NvU8 pllIndex;
|
||||
NvU16 address;
|
||||
} NV2080_CTRL_NVLINK_UPHY_CLN_CMD;
|
||||
|
||||
#define NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS 18U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN
|
||||
*
|
||||
*
|
||||
* This command retrieves the land id cln select, lane id, and pll index.
|
||||
*
|
||||
* [in] linkMask
|
||||
* Mask of links whose uphy should be read
|
||||
* [in] uphyCmd
|
||||
* Array of input data (pll index and address) for each link,
|
||||
* where index 0 represents link 0's pll index
|
||||
* and index 16 represents link 16's pll index.
|
||||
* [out] data
|
||||
* Data from uphy cln for each link where index 0 represents link 0's pll index
|
||||
* and index 16 represents link 16's pll index.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* If the minion command completed successfully
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* If NVLINK is not supported on the chip
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* If the link is not enabled on the GPU or the lane is invalid
|
||||
* NV_ERR_TIMEOUT
|
||||
* If a timeout occurred waiting for minion response
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN (0x20803084U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID (0x84U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS {
|
||||
NvU32 linkMask;
|
||||
NV2080_CTRL_NVLINK_UPHY_CLN_CMD uphyCmd[NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS];
|
||||
NvU32 data[NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS];
|
||||
} NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT 23U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE
|
||||
*
|
||||
* This command gets the supported RBMs of the GPU
|
||||
*
|
||||
* [out] rbmModesList
|
||||
* List of supported RBM modes
|
||||
* [out] rbmTotalModes
|
||||
* Total RBM modes supported
|
||||
* Possible status values returned are: TODO: Update this
|
||||
* NV_OK
|
||||
* If the BW mode is retrieved successfully
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* If NVLINK is not supported on the chip
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* If the link is not enabled on the GPU
|
||||
* NV_ERR_INVALID_STATE
|
||||
* If the link is in an invalid state
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE (0x20803085U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID (0x85U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS {
|
||||
NvU8 rbmModesList[NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT];
|
||||
NvU8 rbmTotalModes;
|
||||
} NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_SET_BW_MODE
|
||||
*
|
||||
* This command sets the requested RBM of the GPU
|
||||
*
|
||||
* [in] rbmMode
|
||||
* Requested RBM mode
|
||||
*
|
||||
* Possible status values returned are: TODO: Update this
|
||||
* NV_OK
|
||||
* If the BW mode is set successfully
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* If NVLINK is not supported on the chip
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* If the link is not enabled on the GPU
|
||||
* NV_ERR_INVALID_STATE
|
||||
* If the link is in an invalid state
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_NVLINK_SET_BW_MODE (0x20803086U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID (0x86U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS {
|
||||
NvU8 rbmMode;
|
||||
} NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_BW_MODE
|
||||
*
|
||||
* This command gets the set RBM of the GPU
|
||||
*
|
||||
* [out] rbmMode
|
||||
* RBM mode currently set
|
||||
*
|
||||
* Possible status values returned are: TODO: Update this
|
||||
* NV_OK
|
||||
* If the BW mode is set successfully
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* If NVLINK is not supported on the chip
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* If the link is not enabled on the GPU
|
||||
* NV_ERR_INVALID_STATE
|
||||
* If the link is in an invalid state
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_BW_MODE (0x20803087U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID (0x87U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS {
|
||||
NvU8 rbmMode;
|
||||
} NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS;
|
||||
|
||||
|
||||
/* _ctrl2080nvlink_h_ */
|
||||
|
||||
@@ -40,21 +40,23 @@
|
||||
* @brief SPDM Command Types
|
||||
*
|
||||
*/
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
|
||||
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
|
||||
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
|
||||
|
||||
|
||||
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
|
||||
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
|
||||
|
||||
#define SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE 0x2400
|
||||
|
||||
|
||||
|
||||
#define RSVD7_SIZE 16
|
||||
#define RSVD7_SIZE 16
|
||||
|
||||
#define RSVD8_SIZE 2
|
||||
#define RSVD8_SIZE 2
|
||||
|
||||
/*!
|
||||
* Guest RM provides INIT context
|
||||
@@ -227,5 +229,20 @@ typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS {
|
||||
RM_GSP_SPDM_MSG msg;
|
||||
} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT
|
||||
*
|
||||
* This command retrieves the transcript of SPDM session establishment messages.
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID (0xDAU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS {
|
||||
NvU8 transcript[SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE];
|
||||
NvU32 transcriptSize;
|
||||
} NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS;
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -438,4 +438,24 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS {
|
||||
NvU32 flags;
|
||||
} NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS
|
||||
*
|
||||
* Returns information whether frame rate limiter is disabled.
|
||||
*
|
||||
* bFlrDisabled [OUT]
|
||||
* True, if frame rate limiter is disabled.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_STATE
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS (0x2080400d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID (0xDU)
|
||||
|
||||
typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
|
||||
NvBool bFlrDisabled;
|
||||
} NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS;
|
||||
|
||||
/* _ctrl2080vgpumgrinternal_h_ */
|
||||
|
||||
Reference in New Issue
Block a user