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This commit is contained in:
Bernhard Stoeckner
2024-10-22 17:38:58 +02:00
parent ed4be64962
commit d5a0858f90
1049 changed files with 209491 additions and 167508 deletions
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3
src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h
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@@ -32,7 +32,6 @@
NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType);
NvBool ceIsPartneredWithGr(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType, RM_ENGINE_TYPE grEngineType);
NvU32 ceCountGrCe(OBJGPU *pGpu);
NvBool ceIsDecompLce(OBJGPU *pGpu, NvU32 nv2080EngineId);
NvU32 ceCountGrCe(OBJGPU *pGpu);
#endif

19
src/nvidia/inc/kernel/gpu/error_cont.h
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@@ -199,6 +199,9 @@ typedef struct _NV_ERROR_CONT_LOCATION
* _E12A_CE_POISON_IN_USER_CHANNEL occurs.
* - RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION : RC Recovery compute channels of only specific MIG partition
* as that error can be attributed to a specific MIG partition.
* - RC_ALL_CHANNELS_IN_VF : RC Recovery compute channels of only specific GFID
* as that error can be attributed to a VF.
* - RC_ALL_USER_CHANNELS : RC Recovery ALL user channels on a GPU.
* - RC_ALL_COMPUTE_CHANNELS : RC Recovery ALL compute channels on a GPU that saw this interrupt.
* (If MIG is enabled, then RC Recovery compute channels in all MIG partitions)
* - CE_TSG_RESET : Reset the halted CE Engine. Impacts the CE channels loaded on the TSG when the CE Halted.
@@ -242,14 +245,14 @@ typedef struct _NV_ERROR_CONT_LOCATION
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_CHANNELS_IN_VF */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E21B_XALEP_INGRESS_UNCONTAINED_POISON, {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E22_PMU_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E23_SEC2_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E24_GSP_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , NO_RC */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E25_FBFALCON_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E22_PMU_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E23_SEC2_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E24_GSP_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_USER_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_USER_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E25_FBFALCON_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E26_NVDEC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E27_NVJPG_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \

6
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -235,7 +235,9 @@ NV_STATUS gsyncSetUseHouse_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU3
NV_STATUS gsyncGetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncRefSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, GSYNCSYNCSIGNAL, NvBool bRate, NvU32 *);
NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask, NvU32 *Refresh, NvBool retainMaster, NvBool skipSwapBarrierWar);
NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *DisplayMask,
NvU32 *Refresh, NvBool retainMaster,
NvBool skipSwapBarrierWar);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncGetCplStatus_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncGetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);

3
src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,5 +33,6 @@ NV_STATUS gsyncSetHouseSyncMode_P2061(OBJGPU *, DACEXTERNALDEVICE *, NvU8);
NV_STATUS gsyncGetCplStatus_P2061 (OBJGPU *, DACEXTERNALDEVICE *, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncSetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32);
NV_STATUS gsyncGetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *);
#endif // DAC_P2061_H

11
src/nvidia/inc/kernel/gpu/external_device/dev_p2061.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,4 +34,13 @@
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_INPUT 0 /* RWXVF */
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_OUTPUT 1 /* RWXVF */
// Used in FW 3.00 and above
#define NV_P2061_CONTROL5 0x33 /* RW-1R */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE 1:0 /* RWXVF */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE_VSYNC_SHORT_PULSE 0 /* RWXVF */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE_VSYNC_SINGLE_PULSE 1 /* RWXVF */
#define NV_P2061_CONTROL5_SYNC_MODE 2:2 /* RWXVF */
#define NV_P2061_CONTROL5_SYNC_MODE_FIXED_REFRESH_RATE 0 /* RWXVF */
#define NV_P2061_CONTROL5_SYNC_MODE_VARIABLE_REFRESH_RATE 1 /* RWXVF */
#endif //DEV_P2061_H

3
src/nvidia/inc/kernel/gpu/fifo/kernel_sched_mgr.h
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@@ -1,3 +0,0 @@
#include "g_kernel_sched_mgr_nvoc.h"

58
src/nvidia/inc/kernel/gpu/fsp/kern_fsp_cot_payload.h Normal file
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@@ -0,0 +1,58 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef KERN_FSP_COT_PAYLOAD_H
#define KERN_FSP_COT_PAYLOAD_H
#pragma pack(1)
typedef struct
{
NvU32 constBlob;
NvU8 msgType;
NvU16 vendorId;
} MCTP_HEADER;
// Needed to remove unnecessary padding
#pragma pack(1)
typedef struct
{
NvU16 version;
NvU16 size;
NvU64 gspFmcSysmemOffset;
NvU64 frtsSysmemOffset;
NvU32 frtsSysmemSize;
// Note this is an offset from the end of FB
NvU64 frtsVidmemOffset;
NvU32 frtsVidmemSize;
// Authentication related fields
NvU32 hash384[12];
NvU32 publicKey[96];
NvU32 signature[96];
NvU64 gspBootArgsSysmemOffset;
} NVDM_PAYLOAD_COT;
#pragma pack()
#endif // KERN_FSP_COT_PAYLOAD_H

36
src/nvidia/inc/kernel/gpu/fsp/kern_fsp_mctp_pkt_state.h Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef KERN_FSP_MCTP_PKT_STATE_H
#define KERN_FSP_MCTP_PKT_STATE_H
// Type of packet, can either be SOM, EOM, neither, or both (1-packet messages)
typedef enum
{
MCTP_PACKET_STATE_START,
MCTP_PACKET_STATE_INTERMEDIATE,
MCTP_PACKET_STATE_END,
MCTP_PACKET_STATE_SINGLE_PACKET
} MCTP_PACKET_STATE;
#endif // KERN_FSP_MCTP_PKT_STATE_H

60
src/nvidia/inc/kernel/gpu/gpu_ecc.h Normal file
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@@ -0,0 +1,60 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _GPU_ECC_H_
#define _GPU_ECC_H_
typedef struct ECC_INFO
{
NvU32 address;
NvU32 addressExt;
NvU32 locationId; // Holds GPC#, Partition#, etc. depending on unit
NvU32 subLocationId; // Holds TPC#, sub-partition#, slice#, etc. depending on unit
NvU64 corTotCnt;
NvU64 corUniCnt;
NvU64 uncTotCnt;
NvU64 uncUniCnt;
NvBool bCorError;
NvBool bCorTotOverflow;
NvBool bCorUniOverflow;
NvBool bUncError;
NvBool bUncTotOverflow;
NvBool bUncUniOverflow;
NvBool bPermanentCorError;
} ECC_INFO;
typedef struct ECC_COUNTERS
{
NvU64 corCntTotCached;
NvU64 corCntTotVolatile;
NvU64 corCntUniCached;
NvU64 corCntUniVolatile;
NvU64 uncCntTotCached;
NvU64 uncCntUniCached;
NvU32 corTotOverflowCount;
NvU32 corUniOverflowCount;
NvU32 uncTotOverflowCount;
NvU32 uncUniOverflowCount;
} ECC_COUNTERS;
#endif // _GPU_ECC_H

4
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
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@@ -50,7 +50,6 @@ typedef enum
RM_ENGINE_TYPE_COPY7 = (0x00000010),
RM_ENGINE_TYPE_COPY8 = (0x00000011),
RM_ENGINE_TYPE_COPY9 = (0x00000012),
// removal tracking bug: 3748354
RM_ENGINE_TYPE_COPY10 = (0x00000013),
RM_ENGINE_TYPE_COPY11 = (0x00000014),
RM_ENGINE_TYPE_COPY12 = (0x00000015),
@@ -95,7 +94,6 @@ typedef enum
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003c),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003d),
RM_ENGINE_TYPE_OFA0 = (0x0000003e),
// removal tracking bug: 3748354
RM_ENGINE_TYPE_OFA1 = (0x0000003f),
RM_ENGINE_TYPE_RESERVED40 = (0x00000040),
RM_ENGINE_TYPE_RESERVED41 = (0x00000041),
@@ -130,12 +128,10 @@ typedef enum
#define RM_ENGINE_TYPE_CIPHER RM_ENGINE_TYPE_TSEC
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
// removal tracking bug: 3748354
#define RM_ENGINE_TYPE_COPY_SIZE 20
#define RM_ENGINE_TYPE_NVENC_SIZE 3
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8
// removal tracking bug: 3748354
#define RM_ENGINE_TYPE_OFA_SIZE 2
#define RM_ENGINE_TYPE_GR_SIZE 8

1
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
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@@ -65,6 +65,7 @@ NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfo
NV_STATUS gpuFabricProbeGetFmStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NvBool gpuFabricProbeIsSupported(OBJGPU *pGpu);
NV_STATUS gpuFabricProbeSetBwMode(NvU8 mode);
NV_STATUS gpuFabricProbeSetBwModePerGpu(OBJGPU *pGpu, NvU8 mode);
NV_STATUS gpuFabricProbeGetlinkMaskToBeReduced(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel,
NvU32 *linkMaskToBeReduced);
NV_STATUS gpuFabricProbeReceiveUpdateKernelCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,

4
src/nvidia/inc/kernel/gpu/gpu_resource_desc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -32,6 +32,6 @@ typedef struct GPU_RESOURCE_DESC
} GPU_RESOURCE_DESC;
// CLASSDESCRIPTOR is deprecated, please use GPU_RESOURCE_DESC
typedef struct GPU_RESOURCE_DESC CLASSDESCRIPTOR, *PCLASSDESCRIPTOR;
typedef struct GPU_RESOURCE_DESC CLASSDESCRIPTOR;
#endif // _GPU_RESOURCE_DESC_H_

1
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h
View File

@@ -40,6 +40,7 @@ typedef struct GpuSharedDataMap {
NvP64 pMapBuffer;
NvU64 lastPolledDataMask;
NvU32 processId;
NvU32 pollingRegistryOverride;
TMR_EVENT *pRusdRefreshTmrEvent;

27
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -30,7 +30,6 @@
// CPU RM (aka GSP client) via NV_RM_RPC_GET_GSP_STATIC_INFO() call.
#include "ctrl/ctrl0080/ctrl0080gpu.h"
#include "ctrl/ctrl0080/ctrl0080gr.h"
#include "ctrl/ctrl2080/ctrl2080bios.h"
#include "ctrl/ctrl2080/ctrl2080fb.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
@@ -41,6 +40,7 @@
#include "platform/chipset/chipset.h" // BUSINFO
#include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX
// VF related info for GSP-RM
typedef struct GSP_VF_INFO
{
@@ -61,19 +61,6 @@ typedef struct
NvU32 linkCap;
} GSP_PCIE_CONFIG_REG;
typedef struct GspSMInfo_t
{
NvU32 version;
NvU32 regBankCount;
NvU32 regBankRegCount;
NvU32 maxWarpsPerSM;
NvU32 maxThreadsPerWarp;
NvU32 geomGsObufEntries;
NvU32 geomXbufEntries;
NvU32 maxSPPerSM;
NvU32 rtCoreCount;
} GspSMInfo;
typedef struct
{
NvU32 ecidLow;
@@ -86,9 +73,6 @@ typedef struct GspStaticConfigInfo_t
{
NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE];
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo;
NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS gpcInfo;
NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS tpcInfo[MAX_GPC_COUNT];
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS zcullInfo[MAX_GPC_COUNT];
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
@@ -97,8 +81,6 @@ typedef struct GspStaticConfigInfo_t
NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
GspSMInfo SM_info;
NvBool poisonFuseEnabled;
NvU64 fb_length;
@@ -108,9 +90,6 @@ typedef struct GspStaticConfigInfo_t
NvU64 fbp_mask;
NvU32 l2_cache_size;
NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL];
NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL];
NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
@@ -174,7 +153,7 @@ typedef struct GspStaticConfigInfo_t
NvBool bIsGpuUefi;
NvBool bIsEfiInit;
EcidManufacturingInfo ecidInfo[2];
EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -207,6 +186,7 @@ typedef struct GspSystemInfo
NvBool bUpstreamL1Unsupported;
NvBool bUpstreamL1PorSupported;
NvBool bUpstreamL1PorMobileOnly;
NvBool bSystemHasMux;
NvU8 upstreamAddressValid;
BUSINFO FHBBusInfo;
BUSINFO chipsetIDInfo;
@@ -222,6 +202,7 @@ typedef struct GspSystemInfo
NvBool bPreserveVideoMemoryAllocations;
NvBool bTdrEventSupported;
NvBool bFeatureStretchVblankCapable;
NvBool bEnableDynamicGranularityPageArrays;
NvBool bClockBoostSupported;
} GspSystemInfo;

8
src/nvidia/inc/kernel/gpu/gsp/gsp_trace_rats_macro.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,8 +40,4 @@
#define KERNEL_GSP_TRACING_RATS_ENABLED 1
#ifndef GET_RATS_TIMESTAMP_NS
#define GET_RATS_TIMESTAMP_NS() NV_ASSERT(0)
#endif
#endif
#endif // GSP_TRACE_RATS_MACRO_H

9
src/nvidia/inc/kernel/gpu/gsp/kernel_gsp_trace_rats.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,6 +28,7 @@
#include "containers/multimap.h"
#include "class/cl90cdtrace.h"
#include "rmapi/event_buffer.h"
#include "rmapi/rmapi.h"
typedef struct
{
@@ -36,6 +37,8 @@ typedef struct
NvHandle hNotifier;
NvHandle hEventBuffer;
NvU64 pUserInfo;
NvU32 *message_buffer;
MEMORY_DESCRIPTOR *pMemDesc;
} NV_EVENT_BUFFER_BIND_POINT_GSP_TRACE;
MAKE_MULTIMAP(GspTraceEventBufferBindMultiMap, NV_EVENT_BUFFER_BIND_POINT_GSP_TRACE);
@@ -44,6 +47,8 @@ void gspTraceNotifyAllConsumers(OBJGPU *pGpu, void *pArgs);
void gspTraceEventBufferLogRecord(OBJGPU *pGpu, NV_RATS_GSP_TRACE_RECORD *intrTraceRecord);
void gspTraceServiceVgpuEventTracing(OBJGPU *pGpu);
NV_STATUS gspTraceAddBindpoint(OBJGPU *pGpu,
RsClient *pClient,
RsResourceRef *pEventBufferRef,
@@ -52,7 +57,7 @@ NV_STATUS gspTraceAddBindpoint(OBJGPU *pGpu,
NvU32 gspLoggingBufferSize,
NvU32 gspLoggingBufferWatermark);
void gspTraceRemoveBindpoint(OBJGPU *pGpu, NvU64 uid, NV_EVENT_BUFFER_BIND_POINT_GSP_TRACE* pBind);
void gspTraceRemoveBindpoint(OBJGPU *pGpu, NvU64 uid, NV_EVENT_BUFFER_BIND_POINT_GSP_TRACE *pBind);
void gspTraceRemoveAllBindpoints(EventBuffer *pEventBuffer);

3
src/nvidia/inc/kernel/gpu/gsplite/kernel_gsplite.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_kernel_gsplite_nvoc.h"

2
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h
View File

@@ -94,7 +94,7 @@ typedef struct OBJMEMSCRUB {
Sec2Utils *pSec2Utils;
#endif // !defined(SRT_BUILD)
// Engine used for scrubbing
NvU32 engineType;
NvBool bIsEngineTypeSec2;
struct OBJGPU *pGpu;
VGPU_GUEST_PMA_SCRUB_BUFFER_RING vgpuScrubBuffRing;

14
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
View File

@@ -654,6 +654,20 @@ NV_STATUS pmaGetRegionInfo(PMA *pPma, NvU32 *pRegSize, PMA_REGION_DESCRIPTOR **p
*/
void pmaGetFreeMemory(PMA *pPma, NvU64 *pBytesFree);
/*!
* @brief Returns information about the client address space size
* that can be allocated
*
* @param[in] pPma PMA pointer
* @param[in] pSize Pointer that will return the size of the
* client-allocatable address space
*
* @return
* void
*/
void
pmaGetClientAddrSpaceSize(PMA *pPma, NvU64 *pSize);
/*!
* @brief Returns information about the largest free FB memory chunk across all regions.
*