From d5cb404571333ebf7a0b9922306e5bb2b63c4859 Mon Sep 17 00:00:00 2001 From: Bernhard Stoeckner Date: Mon, 19 May 2025 17:24:39 +0200 Subject: [PATCH] 570.153.02 --- README.md | 13 +- kernel-open/Kbuild | 58 +++-- kernel-open/common/inc/nv-timer.h | 11 +- kernel-open/conftest.sh | 31 +++ kernel-open/nvidia-drm/nvidia-drm-fence.c | 4 +- .../nvidia-drm/nvidia-drm-os-interface.c | 11 +- .../nvidia-drm/nvidia-drm-os-interface.h | 4 +- kernel-open/nvidia-drm/nvidia-drm-sources.mk | 1 + .../nvidia-modeset/nvidia-modeset-linux.c | 9 +- .../nvidia-modeset/nvidia-modeset.Kbuild | 1 + kernel-open/nvidia-uvm/nvidia-uvm.Kbuild | 3 + kernel-open/nvidia-uvm/uvm_ats_sva.c | 4 + kernel-open/nvidia-uvm/uvm_blackwell_host.c | 28 +++ kernel-open/nvidia-uvm/uvm_gpu.c | 25 ++- kernel-open/nvidia-uvm/uvm_gpu.h | 9 +- .../nvidia-uvm/uvm_gpu_access_counters.c | 193 ++++++++-------- kernel-open/nvidia-uvm/uvm_hal.c | 7 +- kernel-open/nvidia-uvm/uvm_hal.h | 21 ++ kernel-open/nvidia-uvm/uvm_hal_types.h | 7 + kernel-open/nvidia-uvm/uvm_hmm.c | 40 +++- kernel-open/nvidia-uvm/uvm_linux.h | 4 + kernel-open/nvidia-uvm/uvm_lock.c | 3 +- kernel-open/nvidia-uvm/uvm_lock.h | 8 +- kernel-open/nvidia-uvm/uvm_maxwell_host.c | 9 + kernel-open/nvidia-uvm/uvm_pmm_gpu.c | 4 +- kernel-open/nvidia-uvm/uvm_turing_host.c | 10 +- kernel-open/nvidia/nv-nano-timer.c | 9 +- kernel-open/nvidia/nv.c | 4 +- kernel-open/nvidia/nvidia.Kbuild | 3 + kernel-open/nvidia/os-interface.c | 6 +- src/common/displayport/inc/dp_connector.h | 3 + src/common/displayport/inc/dp_deviceimpl.h | 3 + .../displayport/src/dp_connectorimpl2x.cpp | 10 + src/common/displayport/src/dp_deviceimpl.cpp | 13 ++ src/common/inc/nvBldVer.h | 22 +- src/common/inc/nvUnixVersion.h | 2 +- src/common/nvswitch/kernel/ls10/intr_ls10.c | 3 +- src/common/nvswitch/kernel/ls10/minion_ls10.c | 1 - .../nvidia/inc/ctrl/ctrl0000/ctrl0000system.h | 13 ++ .../nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h | 1 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h | 104 ++++++++- src/common/sdk/nvidia/inc/nvos.h | 1 + src/nvidia/generated/g_chipset_nvoc.h | 3 + src/nvidia/generated/g_gpu_access_nvoc.h | 8 + src/nvidia/generated/g_gpu_nvoc.c | 12 + src/nvidia/generated/g_gpu_nvoc.h | 7 +- src/nvidia/generated/g_kern_disp_nvoc.h | 7 +- src/nvidia/generated/g_nv_name_released.h | 7 + src/nvidia/generated/g_subdevice_nvoc.c | 206 ++++++++++++------ src/nvidia/generated/g_subdevice_nvoc.h | 38 +++- src/nvidia/inc/kernel/platform/nvpcf.h | 8 +- src/nvidia/interface/nvrm_registry.h | 48 +++- src/nvidia/kernel/inc/gpuvideo/rmifvideng.h | 16 +- .../src/kernel/compute/imex_session_api.c | 11 +- .../kernel/gpu/arch/hopper/kern_gpu_gh100.c | 5 +- src/nvidia/src/kernel/gpu/disp/kern_disp.c | 24 +- .../arch/volta/kernel_channel_group_gv100.c | 11 +- .../gpu/fsp/arch/hopper/kern_fsp_gh100.c | 37 ++-- src/nvidia/src/kernel/gpu/fsp/kern_fsp.c | 1 - src/nvidia/src/kernel/gpu/gpu.c | 9 +- src/nvidia/src/kernel/gpu/gpu_registry.c | 6 + src/nvidia/src/kernel/gpu/gpu_timeout.c | 14 +- .../gpu/gsp/arch/blackwell/kernel_gsp_gb100.c | 7 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c | 7 + .../src/kernel/gpu/perf/kern_perf_ctrl.c | 4 + src/nvidia/src/kernel/gpu/rc/kernel_rc.c | 46 ++-- .../gpu/subdevice/subdevice_ctrl_gpu_kernel.c | 1 - src/nvidia/src/kernel/platform/acpi_common.c | 16 +- src/nvidia/src/kernel/rmapi/client_resource.c | 27 ++- src/nvidia/src/kernel/vgpu/rpc.c | 4 +- version.mk | 2 +- 71 files changed, 978 insertions(+), 330 deletions(-) diff --git a/README.md b/README.md index 28bb26757..d01e78410 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 570.144. +version 570.153.02. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -570.144 driver release. This can be achieved by installing +570.153.02 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -185,7 +185,7 @@ table below). For details on feature support and limitations, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/570.144/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/570.153.02/README/kernel_open.html For vGPU support, please refer to the README.vgpu packaged in the vGPU Host Package for more details. @@ -954,6 +954,10 @@ Subsystem Device ID. | NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 103C 204B | | NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 10DE 204B | | NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 17AA 204B | +| NVIDIA RTX PRO 5000 Blackwell | 2BB3 1028 204D | +| NVIDIA RTX PRO 5000 Blackwell | 2BB3 103C 204D | +| NVIDIA RTX PRO 5000 Blackwell | 2BB3 10DE 204D | +| NVIDIA RTX PRO 5000 Blackwell | 2BB3 17AA 204D | | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 1028 204C | | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 103C 204C | | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 10DE 204C | @@ -964,6 +968,9 @@ Subsystem Device ID. | NVIDIA GeForce RTX 5080 Laptop GPU | 2C19 | | NVIDIA GeForce RTX 5090 Laptop GPU | 2C58 | | NVIDIA GeForce RTX 5080 Laptop GPU | 2C59 | +| NVIDIA GeForce RTX 5060 Ti | 2D04 | +| NVIDIA GeForce RTX 5070 Laptop GPU | 2D18 | +| NVIDIA GeForce RTX 5070 Laptop GPU | 2D58 | | NVIDIA GeForce RTX 5070 | 2F04 | | NVIDIA GeForce RTX 5070 Ti Laptop GPU | 2F18 | | NVIDIA GeForce RTX 5070 Ti Laptop GPU | 2F58 | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index bf06edb75..7961d16c9 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -75,21 +75,14 @@ $(foreach _module, $(NV_KERNEL_MODULES), \ $(eval include $(src)/$(_module)/$(_module).Kbuild)) -# -# Define CFLAGS that apply to all the NVIDIA kernel modules. EXTRA_CFLAGS -# is deprecated since 2.6.24 in favor of ccflags-y, but we need to support -# older kernels which do not have ccflags-y. Newer kernels append -# $(EXTRA_CFLAGS) to ccflags-y for compatibility. -# - -EXTRA_CFLAGS += -I$(src)/common/inc -EXTRA_CFLAGS += -I$(src) -EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args -EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"570.144\" +ccflags-y += -I$(src)/common/inc +ccflags-y += -I$(src) +ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args +ccflags-y += -D__KERNEL__ -DMODULE -DNVRM +ccflags-y += -DNV_VERSION_STRING=\"570.153.02\" ifneq ($(SYSSRCHOST1X),) - EXTRA_CFLAGS += -I$(SYSSRCHOST1X) + ccflags-y += -I$(SYSSRCHOST1X) endif # Some Android kernels prohibit driver use of filesystem functions like @@ -99,57 +92,57 @@ endif PLATFORM_IS_ANDROID ?= 0 ifeq ($(PLATFORM_IS_ANDROID),1) - EXTRA_CFLAGS += -DNV_FILESYSTEM_ACCESS_AVAILABLE=0 + ccflags-y += -DNV_FILESYSTEM_ACCESS_AVAILABLE=0 else - EXTRA_CFLAGS += -DNV_FILESYSTEM_ACCESS_AVAILABLE=1 + ccflags-y += -DNV_FILESYSTEM_ACCESS_AVAILABLE=1 endif -EXTRA_CFLAGS += -Wno-unused-function +ccflags-y += -Wno-unused-function ifneq ($(NV_BUILD_TYPE),debug) - EXTRA_CFLAGS += -Wuninitialized + ccflags-y += -Wuninitialized endif -EXTRA_CFLAGS += -fno-strict-aliasing +ccflags-y += -fno-strict-aliasing ifeq ($(ARCH),arm64) - EXTRA_CFLAGS += -mstrict-align + ccflags-y += -mstrict-align endif ifeq ($(NV_BUILD_TYPE),debug) - EXTRA_CFLAGS += -g + ccflags-y += -g endif -EXTRA_CFLAGS += -ffreestanding +ccflags-y += -ffreestanding ifeq ($(ARCH),arm64) - EXTRA_CFLAGS += -mgeneral-regs-only -march=armv8-a - EXTRA_CFLAGS += $(call cc-option,-mno-outline-atomics,) + ccflags-y += -mgeneral-regs-only -march=armv8-a + ccflags-y += $(call cc-option,-mno-outline-atomics,) endif ifeq ($(ARCH),x86_64) - EXTRA_CFLAGS += -mno-red-zone -mcmodel=kernel + ccflags-y += -mno-red-zone -mcmodel=kernel endif ifeq ($(ARCH),powerpc) - EXTRA_CFLAGS += -mlittle-endian -mno-strict-align + ccflags-y += -mlittle-endian -mno-strict-align endif -EXTRA_CFLAGS += -DNV_UVM_ENABLE -EXTRA_CFLAGS += $(call cc-option,-Werror=undef,) -EXTRA_CFLAGS += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2) -EXTRA_CFLAGS += -DNV_KERNEL_INTERFACE_LAYER +ccflags-y += -DNV_UVM_ENABLE +ccflags-y += $(call cc-option,-Werror=undef,) +ccflags-y += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2) +ccflags-y += -DNV_KERNEL_INTERFACE_LAYER # # Detect SGI UV systems and apply system-specific optimizations. # ifneq ($(wildcard /proc/sgi_uv),) - EXTRA_CFLAGS += -DNV_CONFIG_X86_UV + ccflags-y += -DNV_CONFIG_X86_UV endif ifdef VGX_FORCE_VFIO_PCI_CORE - EXTRA_CFLAGS += -DNV_VGPU_FORCE_VFIO_PCI_CORE + ccflags-y += -DNV_VGPU_FORCE_VFIO_PCI_CORE endif WARNINGS_AS_ERRORS ?= @@ -183,7 +176,8 @@ NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST_SCRIPT) \ NV_CFLAGS_FROM_CONFTEST := $(shell $(NV_CONFTEST_CMD) build_cflags) -NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(EXTRA_CFLAGS) -fno-pie +NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(ccflags-y) -fno-pie +NV_CONFTEST_CFLAGS += $(filter -std=%,$(KBUILD_CFLAGS)) NV_CONFTEST_CFLAGS += $(call cc-disable-warning,pointer-sign) NV_CONFTEST_CFLAGS += $(call cc-option,-fshort-wchar,) NV_CONFTEST_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types,) diff --git a/kernel-open/common/inc/nv-timer.h b/kernel-open/common/inc/nv-timer.h index 6af49fb67..fc8def0c1 100644 --- a/kernel-open/common/inc/nv-timer.h +++ b/kernel-open/common/inc/nv-timer.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -63,4 +63,13 @@ static inline void nv_timer_setup(struct nv_timer *nv_timer, #endif } +static inline void nv_timer_delete_sync(struct timer_list *timer) +{ +#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync + timer_delete_sync(timer); +#else + del_timer_sync(timer); +#endif +} + #endif // __NV_TIMER_H__ diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 20f694ecb..50070eb98 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -3132,6 +3132,21 @@ compile_test() { compile_check_conftest "$CODE" "NV_FOLL_LONGTERM_PRESENT" "" "types" ;; + has_enum_pidtype_tgid) + # Determine if PIDTYPE_TGID is present in the kernel as an enum + # + # Added by commit 6883f81aac6f ("pid: Implement PIDTYPE_TGID") + # in v4.19 + # + CODE=" + #include + + enum pid_type type = PIDTYPE_TGID; + " + + compile_check_conftest "$CODE" "NV_HAS_ENUM_PIDTYPE_TGID" "" "types" + ;; + vfio_pin_pages_has_vfio_device_arg) # # Determine if vfio_pin_pages() kABI accepts "struct vfio_device *" @@ -7546,6 +7561,22 @@ compile_test() { compile_check_conftest "$CODE" "NV_STRUCT_PAGE_HAS_ZONE_DEVICE_DATA" "" "types" ;; + page_pgmap) + # + # Determine if the page_pgmap() function is present. + # + # Added by commit 82ba975e4c43 ("mm: allow compound zone device + # pages") in v6.14 + # + CODE=" + #include + int conftest_page_pgmap(void) { + return page_pgmap(NULL); + }" + + compile_check_conftest "$CODE" "NV_PAGE_PGMAP_PRESENT" "" "functions" + ;; + folio_test_swapcache) # # Determine if the folio_test_swapcache() function is present. diff --git a/kernel-open/nvidia-drm/nvidia-drm-fence.c b/kernel-open/nvidia-drm/nvidia-drm-fence.c index 81db734d9..3b243eef2 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-fence.c +++ b/kernel-open/nvidia-drm/nvidia-drm-fence.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1132,7 +1132,7 @@ static void __nv_drm_semsurf_fence_ctx_destroy( */ nv_drm_workthread_shutdown(&ctx->worker); - nv_drm_del_timer_sync(&ctx->timer); + nv_timer_delete_sync(&ctx->timer.kernel_timer); /* * The semaphore surface could still be sending callbacks, so it is still diff --git a/kernel-open/nvidia-drm/nvidia-drm-os-interface.c b/kernel-open/nvidia-drm/nvidia-drm-os-interface.c index 7617476d6..c7eb797c6 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-os-interface.c +++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -236,15 +236,6 @@ unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms) return jiffies + msecs_to_jiffies(relative_timeout_ms); } -bool nv_drm_del_timer_sync(nv_drm_timer *timer) -{ - if (del_timer_sync(&timer->kernel_timer)) { - return true; - } else { - return false; - } -} - #if defined(NV_DRM_FENCE_AVAILABLE) int nv_drm_create_sync_file(nv_dma_fence_t *fence) { diff --git a/kernel-open/nvidia-drm/nvidia-drm-os-interface.h b/kernel-open/nvidia-drm/nvidia-drm-os-interface.h index f8e8853b6..50c8e781f 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-os-interface.h +++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -111,8 +111,6 @@ void nv_drm_timer_setup(nv_drm_timer *timer, void nv_drm_mod_timer(nv_drm_timer *timer, unsigned long relative_timeout_ms); -bool nv_drm_del_timer_sync(nv_drm_timer *timer); - unsigned long nv_drm_timer_now(void); unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms); diff --git a/kernel-open/nvidia-drm/nvidia-drm-sources.mk b/kernel-open/nvidia-drm/nvidia-drm-sources.mk index d608ee21e..81b05297f 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-sources.mk +++ b/kernel-open/nvidia-drm/nvidia-drm-sources.mk @@ -37,6 +37,7 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_dec_and_test NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_fd_to_handle NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_handle_to_fd +NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index cbe2ad186..ef51e84e0 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -53,6 +53,7 @@ #include "nv-procfs.h" #include "nv-kthread-q.h" #include "nv-time.h" +#include "nv-timer.h" #include "nv-lock.h" #include "nv-chardev-numbers.h" @@ -738,7 +739,7 @@ static void nvkms_kthread_q_callback(void *arg) * pending timers and than waiting for workqueue callbacks. */ if (timer->kernel_timer_created) { - del_timer_sync(&timer->kernel_timer); + nv_timer_delete_sync(&timer->kernel_timer); } /* @@ -1922,7 +1923,11 @@ restart: * completion, and we wait for queue completion with * nv_kthread_q_stop below. */ +#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync + if (timer_delete_sync(&timer->kernel_timer) == 1) { +#else if (del_timer_sync(&timer->kernel_timer) == 1) { +#endif /* We've deactivated timer so we need to clean after it */ list_del(&timer->timers_list); diff --git a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild index 9f5e748d6..f6d5d9816 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild +++ b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild @@ -103,4 +103,5 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_real_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_backlight_use_native NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_register_backlight +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync NV_CONFTEST_FUNCTION_COMPILE_TESTS += kernel_read_has_pointer_pos_arg diff --git a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild index 7d4fce97b..db4634f55 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild @@ -63,6 +63,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += find_next_bit_wrap NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_is_dma_domain NV_CONFTEST_FUNCTION_COMPILE_TESTS += for_each_sgtable_dma_page NV_CONFTEST_FUNCTION_COMPILE_TESTS += folio_test_swapcache +NV_CONFTEST_FUNCTION_COMPILE_TESTS += page_pgmap NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_invalidate_range @@ -81,3 +82,5 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += struct_page_has_zone_device_data NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present___iowrite64_lo_hi +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_make_device_exclusive diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.c b/kernel-open/nvidia-uvm/uvm_ats_sva.c index a1256f265..f33fab037 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_sva.c +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.c @@ -139,7 +139,11 @@ static NvU32 smmu_vcmdq_read32(void __iomem *smmu_cmdqv_base, int reg) static void smmu_vcmdq_write64(void __iomem *smmu_cmdqv_base, int reg, NvU64 val) { +#if NV_IS_EXPORT_SYMBOL_PRESENT___iowrite64_lo_hi + __iowrite64_lo_hi(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +#else iowrite64(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +#endif } // Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU diff --git a/kernel-open/nvidia-uvm/uvm_blackwell_host.c b/kernel-open/nvidia-uvm/uvm_blackwell_host.c index a95a76f6c..130b73ecd 100644 --- a/kernel-open/nvidia-uvm/uvm_blackwell_host.c +++ b/kernel-open/nvidia-uvm/uvm_blackwell_host.c @@ -254,3 +254,31 @@ void uvm_hal_blackwell_host_tlb_invalidate_test(uvm_push_t *push, HWVALUE(C96F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi)); } } + +uvm_access_counter_clear_op_t +uvm_hal_blackwell_access_counter_query_clear_op_gb100(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries) +{ + if (parent_gpu->rm_info.accessCntrBufferCount > 1) { + NvU32 i; + + for (i = 0; i < num_entries; i++) { + const uvm_access_counter_buffer_entry_t *entry = buffer_entries[i]; + + // The LSb identifies the die ID. + if ((entry->tag & 0x1) == 1) + return UVM_ACCESS_COUNTER_CLEAR_OP_ALL; + } + } + + return UVM_ACCESS_COUNTER_CLEAR_OP_TARGETED; +} + +uvm_access_counter_clear_op_t +uvm_hal_blackwell_access_counter_query_clear_op_gb20x(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries) +{ + return UVM_ACCESS_COUNTER_CLEAR_OP_TARGETED; +} diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index 7344b9c1f..ebb35d3f6 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -1197,6 +1197,8 @@ static NV_STATUS alloc_parent_gpu(const NvProcessorUuid *gpu_uuid, uvm_sema_init(&parent_gpu->isr.replayable_faults.service_lock, 1, UVM_LOCK_ORDER_ISR); uvm_sema_init(&parent_gpu->isr.non_replayable_faults.service_lock, 1, UVM_LOCK_ORDER_ISR); uvm_mutex_init(&parent_gpu->access_counters_enablement_lock, UVM_LOCK_ORDER_ACCESS_COUNTERS); + uvm_mutex_init(&parent_gpu->access_counters_clear_tracker_lock, UVM_LOCK_ACCESS_COUNTERS_CLEAR_OPS); + uvm_tracker_init(&parent_gpu->access_counters_clear_tracker); uvm_spin_lock_irqsave_init(&parent_gpu->isr.interrupts_lock, UVM_LOCK_ORDER_LEAF); uvm_spin_lock_init(&parent_gpu->instance_ptr_table_lock, UVM_LOCK_ORDER_LEAF); uvm_rb_tree_init(&parent_gpu->instance_ptr_table); @@ -1214,6 +1216,7 @@ static NV_STATUS alloc_parent_gpu(const NvProcessorUuid *gpu_uuid, return NV_OK; cleanup: + uvm_tracker_deinit(&parent_gpu->access_counters_clear_tracker); uvm_kvfree(parent_gpu); return status; @@ -1644,19 +1647,12 @@ static void sync_parent_gpu_trackers(uvm_parent_gpu_t *parent_gpu, // Sync the access counter clear tracker too. if (parent_gpu->access_counters_supported && parent_gpu->access_counter_buffer) { - NvU32 notif_buf_index; - for (notif_buf_index = 0; notif_buf_index < parent_gpu->rm_info.accessCntrBufferCount; notif_buf_index++) { - uvm_access_counter_buffer_t *access_counters = &parent_gpu->access_counter_buffer[notif_buf_index]; + uvm_mutex_lock(&parent_gpu->access_counters_clear_tracker_lock); + status = uvm_tracker_wait(&parent_gpu->access_counters_clear_tracker); + uvm_mutex_unlock(&parent_gpu->access_counters_clear_tracker_lock); - if (access_counters->rm_info.accessCntrBufferHandle != 0) { - uvm_access_counters_isr_lock(access_counters); - status = uvm_tracker_wait(&access_counters->clear_tracker); - uvm_access_counters_isr_unlock(access_counters); - - if (status != NV_OK) - UVM_ASSERT(status == uvm_global_get_status()); - } - } + if (status != NV_OK) + UVM_ASSERT(status == uvm_global_get_status()); } } @@ -1787,6 +1783,8 @@ static void uvm_parent_gpu_destroy(nv_kref_t *nv_kref) for_each_sub_processor_index(sub_processor_index) UVM_ASSERT(!parent_gpu->gpus[sub_processor_index]); + uvm_tracker_deinit(&parent_gpu->access_counters_clear_tracker); + uvm_kvfree(parent_gpu); } @@ -2881,6 +2879,9 @@ static NV_STATUS gpu_retain_by_uuid_locked(const NvProcessorUuid *gpu_uuid, if (status != NV_OK) goto error_unregister; + if (gpu_info->accessCntrBufferCount > 1) + gpu_info->accessCntrBufferCount = 1; + if (parent_gpu != NULL) { // If the UUID has been seen before, and if SMC is enabled, then check // if this specific partition has been seen previously. The UUID-based diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index 7e1b8110e..d0977f981 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -522,10 +522,6 @@ struct uvm_access_counter_buffer_struct // PCIe NvU32 cached_put; - // Tracker used to aggregate access counters clear operations, needed for - // GPU removal - uvm_tracker_t clear_tracker; - // Current access counter configuration. During normal operation this // information is computed once during GPU initialization. However, tests // may override it to try different configuration values. @@ -1205,6 +1201,11 @@ struct uvm_parent_gpu_struct uvm_access_counter_buffer_t *access_counter_buffer; uvm_mutex_t access_counters_enablement_lock; + // Tracker used to aggregate access counters clear operations, needed for + // GPU removal. It is only used when supports_access_counters is set. + uvm_tracker_t access_counters_clear_tracker; + uvm_mutex_t access_counters_clear_tracker_lock; + // Number of uTLBs per GPC. This information is only valid on Pascal+ GPUs. NvU32 utlb_per_gpc_count; diff --git a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c index c1584ff9e..bac8dce25 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c @@ -216,38 +216,19 @@ static NV_STATUS config_granularity_to_bytes(UVM_ACCESS_COUNTER_GRANULARITY gran return NV_OK; } -// Clear the access counter notifications and add it to the per-GPU -// per-notification-buffer clear tracker. -static NV_STATUS access_counter_clear_notifications(uvm_gpu_t *gpu, - uvm_access_counter_buffer_t *access_counters, - uvm_access_counter_buffer_entry_t **notification_start, - NvU32 num_notifications) +static NV_STATUS parent_gpu_clear_tracker_wait(uvm_parent_gpu_t *parent_gpu) { - NvU32 i; NV_STATUS status; - uvm_push_t push; - status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &push, "Clear access counter batch"); - if (status != NV_OK) { - UVM_ERR_PRINT("Error creating push to clear access counters: %s, GPU %s, notif buf index %u\n", - nvstatusToString(status), - uvm_gpu_name(gpu), - access_counters->index); - return status; - } + uvm_mutex_lock(&parent_gpu->access_counters_clear_tracker_lock); + status = uvm_tracker_wait(&parent_gpu->access_counters_clear_tracker); + uvm_mutex_unlock(&parent_gpu->access_counters_clear_tracker_lock); - for (i = 0; i < num_notifications; i++) - gpu->parent->host_hal->access_counter_clear_targeted(&push, notification_start[i]); - - uvm_push_end(&push); - - uvm_tracker_remove_completed(&access_counters->clear_tracker); - - return uvm_tracker_add_push_safe(&access_counters->clear_tracker, &push); + return status; } -// Clear all access counters and add the operation to the per-GPU -// per-notification-buffer clear tracker +// Clear all access counters and add the operation to the per-GPU clear +// tracker. static NV_STATUS access_counter_clear_all(uvm_gpu_t *gpu, uvm_access_counter_buffer_t *access_counters) { NV_STATUS status; @@ -269,8 +250,52 @@ static NV_STATUS access_counter_clear_all(uvm_gpu_t *gpu, uvm_access_counter_buf uvm_push_end(&push); - uvm_tracker_remove_completed(&access_counters->clear_tracker); - return uvm_tracker_add_push_safe(&access_counters->clear_tracker, &push); + uvm_mutex_lock(&gpu->parent->access_counters_clear_tracker_lock); + uvm_tracker_remove_completed(&gpu->parent->access_counters_clear_tracker); + status = uvm_tracker_add_push_safe(&gpu->parent->access_counters_clear_tracker, &push); + uvm_mutex_unlock(&gpu->parent->access_counters_clear_tracker_lock); + + return status; +} + +// Clear the access counter notifications and add it to the per-GPU clear +// tracker. +static NV_STATUS access_counter_clear_notifications(uvm_gpu_t *gpu, + uvm_access_counter_buffer_t *access_counters, + uvm_access_counter_buffer_entry_t **notification_start, + NvU32 num_notifications) +{ + NvU32 i; + NV_STATUS status; + uvm_push_t push; + uvm_access_counter_clear_op_t clear_op; + + clear_op = gpu->parent->host_hal->access_counter_query_clear_op(gpu->parent, notification_start, num_notifications); + if (clear_op == UVM_ACCESS_COUNTER_CLEAR_OP_ALL) + return access_counter_clear_all(gpu, access_counters); + + UVM_ASSERT(clear_op == UVM_ACCESS_COUNTER_CLEAR_OP_TARGETED); + + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &push, "Clear access counter batch"); + if (status != NV_OK) { + UVM_ERR_PRINT("Error creating push to clear access counters: %s, GPU %s, notif buf index %u\n", + nvstatusToString(status), + uvm_gpu_name(gpu), + access_counters->index); + return status; + } + + for (i = 0; i < num_notifications; i++) + gpu->parent->host_hal->access_counter_clear_targeted(&push, notification_start[i]); + + uvm_push_end(&push); + + uvm_mutex_lock(&gpu->parent->access_counters_clear_tracker_lock); + uvm_tracker_remove_completed(&gpu->parent->access_counters_clear_tracker); + status = uvm_tracker_add_push_safe(&gpu->parent->access_counters_clear_tracker, &push); + uvm_mutex_unlock(&gpu->parent->access_counters_clear_tracker_lock); + + return status; } bool uvm_parent_gpu_access_counters_pending(uvm_parent_gpu_t *parent_gpu, NvU32 index) @@ -373,8 +398,6 @@ NV_STATUS uvm_parent_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu, NvU3 access_counters->notifications_ignored_count = 0; access_counters->test.reconfiguration_owner = NULL; - uvm_tracker_init(&access_counters->clear_tracker); - access_counters->max_notifications = access_counters->rm_info.bufferSize / parent_gpu->access_counter_buffer_hal->entry_size(parent_gpu); @@ -442,8 +465,6 @@ void uvm_parent_gpu_deinit_access_counters(uvm_parent_gpu_t *parent_gpu, NvU32 n UVM_ASSERT(status == NV_OK); access_counters->rm_info.accessCntrBufferHandle = 0; - uvm_tracker_deinit(&access_counters->clear_tracker); - uvm_kvfree(batch_context->notification_cache); uvm_kvfree(batch_context->notifications); batch_context->notification_cache = NULL; @@ -487,7 +508,7 @@ static NV_STATUS access_counters_take_ownership(uvm_gpu_t *gpu, NvU32 index, con if (status != NV_OK) goto error; - status = uvm_tracker_wait(&access_counters->clear_tracker); + status = parent_gpu_clear_tracker_wait(gpu->parent); if (status != NV_OK) goto error; @@ -521,7 +542,7 @@ static void access_counters_yield_ownership(uvm_parent_gpu_t *parent_gpu, NvU32 UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.access_counters[index].service_lock)); // Wait for any pending clear operation before releasing ownership - status = uvm_tracker_wait(&access_counters->clear_tracker); + status = parent_gpu_clear_tracker_wait(parent_gpu); if (status != NV_OK) UVM_ASSERT(status == uvm_global_get_status()); @@ -1750,28 +1771,21 @@ NV_STATUS uvm_api_clear_all_access_counters(UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS uvm_va_space_up_read(va_space); for_each_gpu_in_mask(gpu, retained_gpus) { - NvU32 notif_buf_index; + uvm_access_counter_buffer_t *access_counters; if (!gpu->parent->access_counters_supported) continue; - for (notif_buf_index = 0; notif_buf_index < gpu->parent->rm_info.accessCntrBufferCount; notif_buf_index++) { - uvm_access_counter_buffer_t *access_counters = parent_gpu_access_counter_buffer_get(gpu->parent, - notif_buf_index); - uvm_access_counters_isr_lock(access_counters); + // clear_all affects all the notification buffers, we issue it for + // the notif_buf_index 0. + access_counters = parent_gpu_access_counter_buffer_get(gpu->parent, 0); + status = access_counter_clear_all(gpu, access_counters); + if (status == NV_OK) + status = parent_gpu_clear_tracker_wait(gpu->parent); - // Access counters are not enabled. Nothing to clear. - if (gpu->parent->isr.access_counters[notif_buf_index].handling_ref_count) { - status = access_counter_clear_all(gpu, access_counters); - if (status == NV_OK) - status = uvm_tracker_wait(&access_counters->clear_tracker); - } - - uvm_access_counters_isr_unlock(access_counters); - - if (status != NV_OK) - break; - } + // Break the loop if clear_all failed in any of the retained gpus. + if (status != NV_OK) + break; } for_each_gpu_in_mask(gpu, retained_gpus) @@ -2054,7 +2068,9 @@ NV_STATUS uvm_test_reset_access_counters(UVM_TEST_RESET_ACCESS_COUNTERS_PARAMS * NV_STATUS status = NV_OK; uvm_gpu_t *gpu = NULL; uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_access_counter_buffer_t *access_counters; NvU32 notif_buf_index; + NvBool index0_state; if (params->mode >= UVM_TEST_ACCESS_COUNTER_RESET_MODE_MAX) return NV_ERR_INVALID_ARGUMENT; @@ -2068,51 +2084,52 @@ NV_STATUS uvm_test_reset_access_counters(UVM_TEST_RESET_ACCESS_COUNTERS_PARAMS * goto exit_release_gpu; } - for (notif_buf_index = 0; - notif_buf_index < gpu->parent->rm_info.accessCntrBufferCount && status == NV_OK; - notif_buf_index++) { - uvm_access_counter_buffer_t *access_counters = parent_gpu_access_counter_buffer_get(gpu->parent, - notif_buf_index); + uvm_mutex_lock(&gpu->parent->access_counters_enablement_lock); - uvm_access_counters_isr_lock(access_counters); + // Access counters not enabled. Nothing to reset + if (!uvm_parent_processor_mask_test(&va_space->access_counters_enabled_processors, gpu->parent->id)) { + uvm_mutex_unlock(&gpu->parent->access_counters_enablement_lock); + goto exit_release_gpu; + } - // Access counters not enabled. Nothing to reset - if (gpu->parent->isr.access_counters[notif_buf_index].handling_ref_count == 0) - goto exit_isr_unlock; + uvm_mutex_unlock(&gpu->parent->access_counters_enablement_lock); - if (params->mode == UVM_TEST_ACCESS_COUNTER_RESET_MODE_ALL) { - status = access_counter_clear_all(gpu, access_counters); - } - else { - uvm_access_counter_buffer_entry_t entry = { 0 }; - uvm_access_counter_buffer_entry_t *notification = &entry; + // Clear operations affect all notification buffers, we use the + // notif_buf_index = 0; + notif_buf_index = 0; + access_counters = parent_gpu_access_counter_buffer_get(gpu->parent, notif_buf_index); - entry.bank = params->bank; - entry.tag = params->tag; + uvm_access_counters_isr_lock(access_counters); - status = access_counter_clear_notifications(gpu, access_counters, ¬ification, 1); - } + // Recheck access counters are enabled. + index0_state = gpu->parent->isr.access_counters[notif_buf_index].handling_ref_count == 0; + if (index0_state) { + NvU32 i; - if (status == NV_OK) - status = uvm_tracker_wait(&access_counters->clear_tracker); + for (i = notif_buf_index + 1; i < gpu->parent->rm_info.accessCntrBufferCount; i++) + UVM_ASSERT((gpu->parent->isr.access_counters[i].handling_ref_count == 0) == index0_state); + + goto exit_isr_unlock; + } + + if (params->mode == UVM_TEST_ACCESS_COUNTER_RESET_MODE_ALL) { + status = access_counter_clear_all(gpu, access_counters); + } + else { + uvm_access_counter_buffer_entry_t entry = { 0 }; + uvm_access_counter_buffer_entry_t *notification = &entry; + + entry.bank = params->bank; + entry.tag = params->tag; + + status = access_counter_clear_notifications(gpu, access_counters, ¬ification, 1); + } + + if (status == NV_OK) + status = parent_gpu_clear_tracker_wait(gpu->parent); exit_isr_unlock: - uvm_access_counters_isr_unlock(access_counters); - - // We only need to clear_all() once. - if (params->mode == UVM_TEST_ACCESS_COUNTER_RESET_MODE_ALL) { - NvU32 i; - - // Early exit of the main loop; since we only need to clear_all() - // once. Check that all the remaining notification buffers have - // access counters in same state. - NvBool index0_state = (gpu->parent->isr.access_counters[notif_buf_index].handling_ref_count == 0); - for (i = notif_buf_index + 1; i < gpu->parent->rm_info.accessCntrBufferCount; i++) - UVM_ASSERT((gpu->parent->isr.access_counters[i].handling_ref_count == 0) == index0_state); - - break; - } - } + uvm_access_counters_isr_unlock(access_counters); exit_release_gpu: uvm_gpu_release(gpu); diff --git a/kernel-open/nvidia-uvm/uvm_hal.c b/kernel-open/nvidia-uvm/uvm_hal.c index 720127b9a..200f477a4 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.c +++ b/kernel-open/nvidia-uvm/uvm_hal.c @@ -218,6 +218,7 @@ static uvm_hal_class_ops_t host_table[] = .clear_faulted_channel_register = uvm_hal_maxwell_host_clear_faulted_channel_register_unsupported, .access_counter_clear_all = uvm_hal_maxwell_access_counter_clear_all_unsupported, .access_counter_clear_targeted = uvm_hal_maxwell_access_counter_clear_targeted_unsupported, + .access_counter_query_clear_op = uvm_hal_maxwell_access_counter_query_clear_op_unsupported, .get_time = uvm_hal_maxwell_get_time, } }, @@ -269,6 +270,7 @@ static uvm_hal_class_ops_t host_table[] = .tlb_invalidate_test = uvm_hal_turing_host_tlb_invalidate_test, .access_counter_clear_all = uvm_hal_turing_access_counter_clear_all, .access_counter_clear_targeted = uvm_hal_turing_access_counter_clear_targeted, + .access_counter_query_clear_op = uvm_hal_turing_access_counter_query_clear_op, } }, { @@ -308,12 +310,15 @@ static uvm_hal_class_ops_t host_table[] = .tlb_invalidate_all = uvm_hal_blackwell_host_tlb_invalidate_all, .tlb_invalidate_va = uvm_hal_blackwell_host_tlb_invalidate_va, .tlb_invalidate_test = uvm_hal_blackwell_host_tlb_invalidate_test, + .access_counter_query_clear_op = uvm_hal_blackwell_access_counter_query_clear_op_gb100, } }, { .id = BLACKWELL_CHANNEL_GPFIFO_B, .parent_id = BLACKWELL_CHANNEL_GPFIFO_A, - .u.host_ops = {} + .u.host_ops = { + .access_counter_query_clear_op = uvm_hal_blackwell_access_counter_query_clear_op_gb20x + } }, }; diff --git a/kernel-open/nvidia-uvm/uvm_hal.h b/kernel-open/nvidia-uvm/uvm_hal.h index 387bfebe3..cfe751928 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.h +++ b/kernel-open/nvidia-uvm/uvm_hal.h @@ -703,6 +703,10 @@ typedef NvU32 (*uvm_hal_access_counter_buffer_entry_size_t)(uvm_parent_gpu_t *pa typedef void (*uvm_hal_access_counter_clear_all_t)(uvm_push_t *push); typedef void (*uvm_hal_access_counter_clear_targeted_t)(uvm_push_t *push, const uvm_access_counter_buffer_entry_t *buffer_entry); +typedef uvm_access_counter_clear_op_t + (*uvm_hal_access_counter_query_clear_op_t)(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries); void uvm_hal_maxwell_enable_access_counter_notifications_unsupported(uvm_access_counter_buffer_t *access_counters); void uvm_hal_maxwell_disable_access_counter_notifications_unsupported(uvm_access_counter_buffer_t *access_counters); @@ -719,6 +723,10 @@ NvU32 uvm_hal_maxwell_access_counter_buffer_entry_size_unsupported(uvm_parent_gp void uvm_hal_maxwell_access_counter_clear_all_unsupported(uvm_push_t *push); void uvm_hal_maxwell_access_counter_clear_targeted_unsupported(uvm_push_t *push, const uvm_access_counter_buffer_entry_t *buffer_entry); +uvm_access_counter_clear_op_t +uvm_hal_maxwell_access_counter_query_clear_op_unsupported(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries); void uvm_hal_turing_enable_access_counter_notifications(uvm_access_counter_buffer_t *access_counters); void uvm_hal_turing_disable_access_counter_notifications(uvm_access_counter_buffer_t *access_counters); @@ -732,6 +740,18 @@ NvU32 uvm_hal_turing_access_counter_buffer_entry_size(uvm_parent_gpu_t *parent_g void uvm_hal_turing_access_counter_clear_all(uvm_push_t *push); void uvm_hal_turing_access_counter_clear_targeted(uvm_push_t *push, const uvm_access_counter_buffer_entry_t *buffer_entry); +uvm_access_counter_clear_op_t +uvm_hal_turing_access_counter_query_clear_op(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries); +uvm_access_counter_clear_op_t +uvm_hal_blackwell_access_counter_query_clear_op_gb100(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries); +uvm_access_counter_clear_op_t +uvm_hal_blackwell_access_counter_query_clear_op_gb20x(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries); // The source and destination addresses must be 16-byte aligned. Note that the // best performance is achieved with 256-byte alignment. The decrypt size must @@ -785,6 +805,7 @@ struct uvm_host_hal_struct uvm_hal_host_clear_faulted_channel_register_t clear_faulted_channel_register; uvm_hal_access_counter_clear_all_t access_counter_clear_all; uvm_hal_access_counter_clear_targeted_t access_counter_clear_targeted; + uvm_hal_access_counter_query_clear_op_t access_counter_query_clear_op; uvm_hal_get_time_t get_time; }; diff --git a/kernel-open/nvidia-uvm/uvm_hal_types.h b/kernel-open/nvidia-uvm/uvm_hal_types.h index 0763e7115..f84289c14 100644 --- a/kernel-open/nvidia-uvm/uvm_hal_types.h +++ b/kernel-open/nvidia-uvm/uvm_hal_types.h @@ -471,6 +471,13 @@ static uvm_membar_t uvm_membar_max(uvm_membar_t membar_1, uvm_membar_t membar_2) return max(membar_1, membar_2); } +typedef enum +{ + UVM_ACCESS_COUNTER_CLEAR_OP_NONE = 0, + UVM_ACCESS_COUNTER_CLEAR_OP_TARGETED, + UVM_ACCESS_COUNTER_CLEAR_OP_ALL +} uvm_access_counter_clear_op_t; + struct uvm_access_counter_buffer_entry_struct { // Address of the region for which a notification was sent diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c index 92bfd7cab..6f904aa6f 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.c +++ b/kernel-open/nvidia-uvm/uvm_hmm.c @@ -1991,7 +1991,7 @@ static void fill_dst_pfn(uvm_va_block_t *va_block, dpage = pfn_to_page(pfn); UVM_ASSERT(is_device_private_page(dpage)); - UVM_ASSERT(dpage->pgmap->owner == &g_uvm_global); + UVM_ASSERT(page_pgmap(dpage)->owner == &g_uvm_global); hmm_mark_gpu_chunk_referenced(va_block, gpu, gpu_chunk); UVM_ASSERT(!page_count(dpage)); @@ -2437,6 +2437,39 @@ static void hmm_release_atomic_pages(uvm_va_block_t *va_block, } } +static int hmm_make_device_exclusive_range(struct mm_struct *mm, + unsigned long start, + unsigned long end, + struct page **pages) +{ +#if NV_IS_EXPORT_SYMBOL_PRESENT_make_device_exclusive + unsigned long addr; + int npages = 0; + + for (addr = start; addr < end; addr += PAGE_SIZE) { + struct folio *folio; + struct page *page; + + page = make_device_exclusive(mm, addr, &g_uvm_global, &folio); + if (IS_ERR(page)) { + while (npages) { + page = pages[--npages]; + unlock_page(page); + put_page(page); + } + npages = PTR_ERR(page); + break; + } + + pages[npages++] = page; + } + + return npages; +#else + return make_device_exclusive_range(mm, start, end, pages, &g_uvm_global); +#endif +} + static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, @@ -2490,11 +2523,10 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, uvm_mutex_unlock(&va_block->lock); - npages = make_device_exclusive_range(service_context->block_context->mm, + npages = hmm_make_device_exclusive_range(service_context->block_context->mm, uvm_va_block_cpu_page_address(va_block, region.first), uvm_va_block_cpu_page_address(va_block, region.outer - 1) + PAGE_SIZE, - pages + region.first, - &g_uvm_global); + pages + region.first); uvm_mutex_lock(&va_block->lock); diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index 75d9b2a78..0dbf22fff 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -425,4 +425,8 @@ static inline pgprot_t uvm_pgprot_decrypted(pgprot_t prot) #define UVM_FOR_EACH_SGTABLE_DMA_PAGE_PRESENT() 1 #endif +#ifndef NV_PAGE_PGMAP_PRESENT +#define page_pgmap(page) (page)->pgmap +#endif + #endif // _UVM_LINUX_H diff --git a/kernel-open/nvidia-uvm/uvm_lock.c b/kernel-open/nvidia-uvm/uvm_lock.c index 1ee17044f..1fec9c7d6 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.c +++ b/kernel-open/nvidia-uvm/uvm_lock.c @@ -27,7 +27,7 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) { - BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 37); + BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 38); switch (lock_order) { UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_INVALID); @@ -58,6 +58,7 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM_PMA); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM_ROOT_CHUNK); + UVM_ENUM_STRING_CASE(UVM_LOCK_ACCESS_COUNTERS_CLEAR_OPS); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CHANNEL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_WLC_CHANNEL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST); diff --git a/kernel-open/nvidia-uvm/uvm_lock.h b/kernel-open/nvidia-uvm/uvm_lock.h index 2371e0f8c..6286f50e7 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.h +++ b/kernel-open/nvidia-uvm/uvm_lock.h @@ -432,6 +432,11 @@ // Order: UVM_LOCK_ORDER_PMM_ROOT_CHUNK // Exclusive bitlock (mutex) per each root chunk internal to PMM. // +// - Access counters clear operations +// Order: UVM_LOCK_ACCESS_COUNTERS_CLEAR_OPS +// +// It protects the parent_gpu's access counters clear tracker. +// // - Channel lock // Order: UVM_LOCK_ORDER_CHANNEL // Spinlock (uvm_spinlock_t) or exclusive lock (mutex) @@ -477,7 +482,7 @@ // // CE semaphore payloads are encrypted, and require to take the CSL lock // (UVM_LOCK_ORDER_LEAF) to decrypt the payload. - +// // - CSL Context // Order: UVM_LOCK_ORDER_CSL_CTX // When the Confidential Computing feature is enabled, encrypt/decrypt @@ -523,6 +528,7 @@ typedef enum UVM_LOCK_ORDER_PMM, UVM_LOCK_ORDER_PMM_PMA, UVM_LOCK_ORDER_PMM_ROOT_CHUNK, + UVM_LOCK_ACCESS_COUNTERS_CLEAR_OPS, UVM_LOCK_ORDER_CHANNEL, UVM_LOCK_ORDER_WLC_CHANNEL, UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST, diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_host.c b/kernel-open/nvidia-uvm/uvm_maxwell_host.c index 8b580fd4b..6caee098b 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_host.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_host.c @@ -336,6 +336,15 @@ void uvm_hal_maxwell_access_counter_clear_targeted_unsupported(uvm_push_t *push, UVM_ASSERT_MSG(false, "host access_counter_clear_targeted called on Maxwell GPU\n"); } +uvm_access_counter_clear_op_t +uvm_hal_maxwell_access_counter_query_clear_op_unsupported(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries) +{ + UVM_ASSERT_MSG(false, "host access_counter_query_clear_op called on Maxwell GPU\n"); + return UVM_ACCESS_COUNTER_CLEAR_OP_NONE; +} + NvU64 uvm_hal_maxwell_get_time(uvm_gpu_t *gpu) { NvU32 time0; diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c index d8c082786..cf626ad5c 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c @@ -3329,7 +3329,7 @@ void uvm_pmm_gpu_device_p2p_init(uvm_gpu_t *gpu) // TODO: Bug 4672502: [Linux Upstream][UVM] Allow drivers to manage and // allocate PCI P2PDMA pages directly p2p_page = pfn_to_page(pci_start_pfn); - p2p_page->pgmap->ops = &uvm_device_p2p_pgmap_ops; + page_pgmap(p2p_page)->ops = &uvm_device_p2p_pgmap_ops; for (; page_to_pfn(p2p_page) < pci_end_pfn; p2p_page++) p2p_page->zone_device_data = NULL; @@ -3344,7 +3344,7 @@ void uvm_pmm_gpu_device_p2p_deinit(uvm_gpu_t *gpu) if (gpu->device_p2p_initialised && !uvm_parent_gpu_is_coherent(gpu->parent)) { p2p_page = pfn_to_page(pci_start_pfn); - devm_memunmap_pages(&gpu->parent->pci_dev->dev, p2p_page->pgmap); + devm_memunmap_pages(&gpu->parent->pci_dev->dev, page_pgmap(p2p_page)); } gpu->device_p2p_initialised = false; diff --git a/kernel-open/nvidia-uvm/uvm_turing_host.c b/kernel-open/nvidia-uvm/uvm_turing_host.c index 0d31e3b89..2363d36b5 100644 --- a/kernel-open/nvidia-uvm/uvm_turing_host.c +++ b/kernel-open/nvidia-uvm/uvm_turing_host.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2024 NVIDIA Corporation + Copyright (c) 2017-2025 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -382,3 +382,11 @@ void uvm_hal_turing_access_counter_clear_targeted(uvm_push_t *push, HWCONST(C46F, MEM_OP_D, ACCESS_COUNTER_CLR_TARGETED_TYPE, MIMC) | HWVALUE(C46F, MEM_OP_D, ACCESS_COUNTER_CLR_TARGETED_BANK, buffer_entry->bank)); } + +uvm_access_counter_clear_op_t +uvm_hal_turing_access_counter_query_clear_op(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t **buffer_entries, + NvU32 num_entries) +{ + return UVM_ACCESS_COUNTER_CLEAR_OP_TARGETED; +} diff --git a/kernel-open/nvidia/nv-nano-timer.c b/kernel-open/nvidia/nv-nano-timer.c index 6549c82f4..dcb5719c9 100644 --- a/kernel-open/nvidia/nv-nano-timer.c +++ b/kernel-open/nvidia/nv-nano-timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -154,8 +154,13 @@ void NV_API_CALL nv_create_nano_timer( nv_nstimer->nv_nano_timer_callback = nvidia_nano_timer_callback; #if NV_NANO_TIMER_USE_HRTIMER +#if NV_IS_EXPORT_SYMBOL_PRESENT_hrtimer_setup + hrtimer_setup(&nv_nstimer->hr_timer, &nv_nano_timer_callback_typed_data, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); +#else hrtimer_init(&nv_nstimer->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); nv_nstimer->hr_timer.function = nv_nano_timer_callback_typed_data; +#endif // NV_IS_EXPORT_SYMBOL_PRESENT_hrtimer_setup #else #if defined(NV_TIMER_SETUP_PRESENT) timer_setup(&nv_nstimer->jiffy_timer, nv_jiffy_timer_callback_typed_data, 0); @@ -207,7 +212,7 @@ void NV_API_CALL nv_cancel_nano_timer( #if NV_NANO_TIMER_USE_HRTIMER hrtimer_cancel(&nv_nstimer->hr_timer); #else - del_timer_sync(&nv_nstimer->jiffy_timer); + nv_timer_delete_sync(&nv_nstimer->jiffy_timer); #endif } diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 8edc49192..040a36f8e 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -4106,7 +4106,7 @@ int NV_API_CALL nv_stop_rc_timer( nv_printf(NV_DBG_INFO, "NVRM: stopping rc timer\n"); nv->rc_timer_enabled = 0; - del_timer_sync(&nvl->rc_timer.kernel_timer); + nv_timer_delete_sync(&nvl->rc_timer.kernel_timer); nv_printf(NV_DBG_INFO, "NVRM: rc timer stopped\n"); return 0; @@ -4150,7 +4150,7 @@ void NV_API_CALL nv_stop_snapshot_timer(void) NV_SPIN_UNLOCK_IRQRESTORE(&nvl->snapshot_timer_lock, flags); if (timer_active) - del_timer_sync(&nvl->snapshot_timer.kernel_timer); + nv_timer_delete_sync(&nvl->snapshot_timer.kernel_timer); } void NV_API_CALL nv_flush_snapshot_timer(void) diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index 6ae67c3f9..eef07bcbb 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -234,6 +234,8 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += follow_pte_arg_vma NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_follow_pfnmap_start NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_pci_ats_supported NV_CONFTEST_SYMBOL_COMPILE_TESTS += ecc_digits_from_bytes +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_hrtimer_setup NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops @@ -260,6 +262,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += foll_longterm_present NV_CONFTEST_TYPE_COMPILE_TESTS += bus_type_has_iommu_ops NV_CONFTEST_TYPE_COMPILE_TESTS += class_create_has_no_owner_arg NV_CONFTEST_TYPE_COMPILE_TESTS += class_devnode_has_const_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += has_enum_pidtype_tgid NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 9bd1e99d5..20e6e6826 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -2644,7 +2644,11 @@ NV_STATUS NV_API_CALL os_offline_page_at_address void* NV_API_CALL os_get_pid_info(void) { - return get_task_pid(current, PIDTYPE_PID); +#if defined(NV_HAS_ENUM_PIDTYPE_TGID) + return get_task_pid(current, PIDTYPE_TGID); +#else + return get_task_pid(current->group_leader, PIDTYPE_PID); +#endif } void NV_API_CALL os_put_pid_info(void *pid_info) diff --git a/src/common/displayport/inc/dp_connector.h b/src/common/displayport/inc/dp_connector.h index f9220cad2..939af2682 100644 --- a/src/common/displayport/inc/dp_connector.h +++ b/src/common/displayport/inc/dp_connector.h @@ -333,6 +333,9 @@ namespace DisplayPort virtual bool getDeviceSpecificData(NvU8 *oui, NvU8 *deviceIdString, NvU8 *hwRevision, NvU8 *swMajorRevision, NvU8 *swMinorRevision) = 0; + virtual bool getParentSpecificData(NvU8 *oui, NvU8 *deviceIdString, + NvU8 *hwRevision, NvU8 *swMajorRevision, + NvU8 *swMinorRevision) = 0; virtual bool setModeList(DisplayPort::DpModesetParams *pModeList, unsigned numModes) = 0; diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index 8cc9ac24f..0fad3ed7a 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -508,6 +508,9 @@ namespace DisplayPort virtual bool getDeviceSpecificData(NvU8 *oui, NvU8 *deviceIdString, NvU8 *hwRevision, NvU8 *swMajorRevision, NvU8 *swMinorRevision); + virtual bool getParentSpecificData(NvU8 *oui, NvU8 *deviceIdString, + NvU8 *hwRevision, NvU8 *swMajorRevision, + NvU8 *swMinorRevision); virtual bool setModeList(DisplayPort::DpModesetParams *pModeList, unsigned numModes); }; diff --git a/src/common/displayport/src/dp_connectorimpl2x.cpp b/src/common/displayport/src/dp_connectorimpl2x.cpp index 9f74a6554..70c45e20e 100644 --- a/src/common/displayport/src/dp_connectorimpl2x.cpp +++ b/src/common/displayport/src/dp_connectorimpl2x.cpp @@ -490,12 +490,22 @@ bool ConnectorImpl2x::compoundQueryAttachMSTGeneric(Group * target, tail->bandwidth.compound_query_state.totalTimeSlots) { compoundQueryResult = false; + if(this->bEnableLowerBppCheckForDsc) + { + tail->bandwidth.compound_query_state.timeslots_used_by_query -= linkConfig->slotsForPBN(base_pbn); + tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex &= ~(1 << compoundQueryCount); + } SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH) } } tail = (DeviceImpl*)tail->getParent(); } } + // If the compoundQueryResult is false, we need to reset the compoundQueryLocalLinkPBN + if (!compoundQueryResult && this->bEnableLowerBppCheckForDsc) + { + compoundQueryLocalLinkPBN -= slots_pbn; + } } else { diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index 484f8ddc5..3a7daab6b 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -3232,6 +3232,19 @@ bool DeviceImpl::getDeviceSpecificData(NvU8 *oui, NvU8 *devIdString, return true; } +bool DeviceImpl::getParentSpecificData(NvU8 *oui, NvU8 *devIdString, + NvU8 *hwRevision, NvU8 *swMajorRevision, + NvU8 *swMinorRevision) +{ + if (this->parent == NULL) + { + return false; + } + + return this->parent->getDeviceSpecificData(oui, devIdString, hwRevision, + swMajorRevision, swMinorRevision); +} + bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned numModes) { // Create a dummy group for compoundQuery diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index daafd3605..0722876e2 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,25 +36,25 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r570_00 + #define NV_BUILD_BRANCH r573_24 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r570_00 + #define NV_PUBLIC_BRANCH r573_24 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r570_00-407" -#define NV_BUILD_CHANGELIST_NUM (35817632) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r573_24-444" +#define NV_BUILD_CHANGELIST_NUM (35974374) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r570/r570_00-407" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35817632) +#define NV_BUILD_NAME "rel/gpu_drv/r570/r573_24-444" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35974374) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r570_00-404" -#define NV_BUILD_CHANGELIST_NUM (35811382) -#define NV_BUILD_TYPE "Nightly" -#define NV_BUILD_NAME "r570_00-250410" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35811869) +#define NV_BUILD_BRANCH_VERSION "r573_24-1" +#define NV_BUILD_CHANGELIST_NUM (35972701) +#define NV_BUILD_TYPE "Official" +#define NV_BUILD_NAME "573.25" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35972701) #define NV_BUILD_BRANCH_BASE_VERSION R570 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index 278fe8c79..1ab83b8dc 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "570.144" +#define NV_VERSION_STRING "570.153.02" #else diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index d51919abf..bb4727b78 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -6349,7 +6349,8 @@ _nvswitch_deferred_link_state_check_ls10 lastLinkUpTime = chip_device->deferredLinkErrors[link].state.lastLinkUpTime; lastRetrainTime = chip_device->deferredLinkErrors[link].state.lastRetrainTime; // Sanity Check - NVSWITCH_ASSERT(nvswitch_is_link_valid(device, link)); + if (!nvswitch_is_link_valid(device, link)) + return; chip_device->deferredLinkErrors[link].state.bLinkStateCallBackEnabled = NV_FALSE; bRedeferLinkStateCheck = NV_FALSE; diff --git a/src/common/nvswitch/kernel/ls10/minion_ls10.c b/src/common/nvswitch/kernel/ls10/minion_ls10.c index 69cfe07f6..e40370682 100644 --- a/src/common/nvswitch/kernel/ls10/minion_ls10.c +++ b/src/common/nvswitch/kernel/ls10/minion_ls10.c @@ -941,7 +941,6 @@ cleanup: if (tempStatus != NVL_SUCCESS) { NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer for RX_BUFFER_CLEAR\n", linkId); - return; } if (device->link[linkId].inbandData.message != NULL) { diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index 51b7a23c9..587646714 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -2143,6 +2143,16 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT { NvU32 shortTimescaleBatteryCurrentLimitmA; } NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT; +/*! + * States for the Battery CPU TDP Control ability. + * _CPU_TDP_CONTROL_TYPE_DC_ONLY :==> Legacy setting for DC only CPU TDP Control + * _CPU_TDP_CONTROL_TYPE_DC_AC :==> AC and DC both support CPU TDP Control + */ +typedef enum QBOOST_CPU_TDP_CONTROL_TYPE { + QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY = 0, + QBOOST_CPU_TDP_CONTROL_TYPE_DC_AC = 1, +} QBOOST_CPU_TDP_CONTROL_TYPE; + #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { @@ -2277,6 +2287,9 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { /* CPU TDP Limit to be set (milliwatts) */ NvU32 cpuTdpmw; + + /* CPU TDP Control Support */ + QBOOST_CPU_TDP_CONTROL_TYPE cpuTdpControlType; } NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h index d36440d01..edf0f4750 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -1552,3 +1552,4 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS { #define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES (0x00000001) #define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO (0x00000000) + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h index c4b2120fc..dd781fd4b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -2537,6 +2537,9 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS { NvU8 ee_ls; NvU8 ee; NvU8 ase; + NvBool ee_nmxas; + NvU8 nmxas_e; + NvU8 ps_e_ext; } NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS; @@ -2599,6 +2602,14 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS { NvU16 fec_override_admin_800g_8x; NvU16 fec_override_admin_100g_1x; NvU16 fec_override_admin_200g_2x; + NvBool tx_crc_plr_vld; + NvBool tx_crc_plr_override_to_default; + NvBool plr_reject_mode_override_to_default; + NvU16 nvlink_fec_override_admin_nvl_phy6; + NvU16 fec_override_admin_800g_4x; + NvU16 fec_override_admin_1600g_8x; + NvU16 fec_override_admin_200g_1x; + NvU16 fec_override_admin_400g_2x; } NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC (0x20803055U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID" */ @@ -2618,6 +2629,12 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS { NvU16 l1_hw_active_time; NvU16 l1_hw_inactive_time; NvU8 qem[8]; + NvBool l0_rx_cap_adv; + NvBool l0_rx_req_en; + NvBool l0_tx_cap_adv; + NvBool l0_tx_req_en; + NvBool l0_all_queues_are_import; + NvU16 l0_hw_inactive_time; } NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM (0x20803056U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID" */ @@ -2699,6 +2716,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS { NvU8 local_port; NvBool m_lane_m; NvBool rxtx; + NvBool mod_lab_map; } NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT (0x20803065U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID" */ @@ -2726,6 +2744,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS { NvU8 local_port; NvU8 page_select; NvU8 module_info_ext; + NvU8 module_ind_type; } NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT (0x20803068U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID" */ @@ -2795,6 +2814,9 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS { NvU8 swid; NvU8 plane_ind; NvU8 phy_status_admin; + NvBool ee_nmxas; + NvU8 nmxas_e; + NvU8 ps_e_ext; } NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR (0x2080306cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID" */ @@ -2827,6 +2849,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS { NvU8 pnat; NvU8 local_port; NvU8 lp_msb; + NvBool conf_mod; } NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID (0x2080306eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID" */ @@ -2932,6 +2955,8 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS { NvU8 lp_msb; NvU8 local_port; NvU16 lb_en; + NvBool lb_cap_mode_idx; + NvBool lb_link_mode_idx; } NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS; #define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS (0x20803074U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID" */ @@ -3040,6 +3065,8 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS { NvU8 critical_inactive_time; NvU8 critical_active_time; NvBool cc; + NvBool l0_all_queues_are_import; + NvBool ge; } NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR (0x2080307dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID" */ @@ -3359,6 +3386,81 @@ typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS { NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS]; } NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTASV2 (0x20803093U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS { + NvBool bWrite; + NV2080_CTRL_NVLINK_PRM_DATA prm; + NvU8 lp_msb; + NvU8 pnat; + NvU8 local_port; + NvU8 xdr_lt_c2c_en; + NvU8 xdr_lt_c2m_en; + NvU8 kr_ext_req; + NvU8 lt_ext_neg_type; + NvU8 lt_ext_timeout_admin; + NvU8 prbs_type_admin; + NvBool ber_cnt_mlsd_dis; + NvU8 num_of_iter_admin; + NvU16 iter_time_admin; + NvU8 ber_target_coef_admin; + NvU8 ber_target_magnitude_admin; +} NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLLM_5NM (0x20803094U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS { + NvBool bWrite; + NV2080_CTRL_NVLINK_PRM_DATA prm; + NvBool c_db; + NvBool br_lanes; + NvU8 port_type; + NvU8 lane; + NvU8 lp_msb; + NvU8 pnat; + NvU8 local_port; + NvBool peq_cap; + NvU16 peq_interval_period; +} NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS (0x20803090U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID (0x90U) + +typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS { + NV2080_CTRL_NVLINK_PRM_DATA prm; +} NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRM (0x20803091U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID (0x91U) + +typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS { + NvBool bWrite; + NV2080_CTRL_NVLINK_PRM_DATA prm; + NvU8 ovrd_no_neg_bhvr; + NvU8 plane_ind; + NvU8 lp_msb; + NvU8 pnat; + NvU8 local_port; + NvU8 no_neg_bhvr; + NvU8 wd_logic_re_lock_res; + NvU8 module_datapath_full_toggle; + NvU8 module_tx_disable; + NvU8 host_serdes_feq; + NvU8 host_logic_re_lock; + NvU16 link_down_timeout; + NvU8 draining_timeout; + NvU8 wd_module_full_toggle; + NvU8 wd_module_tx_disable; + NvU8 wd_host_serdes_feq; + NvU8 wd_host_logic_re_lock; +} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS; + /* _ctrl2080nvlink_h_ */ diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index 39ce059de..dc532bda8 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -79,6 +79,7 @@ extern "C" { #define NVOS_STATUS_ERROR_ILLEGAL_ACTION NV_ERR_ILLEGAL_ACTION #define NVOS_STATUS_ERROR_IN_USE NV_ERR_STATE_IN_USE #define NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES NV_ERR_INSUFFICIENT_RESOURCES +#define NVOS_STATUS_ERROR_INSUFFICIENT_ZBC_ENTRY NV_ERR_INSUFFICIENT_ZBC_ENTRY #define NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE NV_ERR_INVALID_ACCESS_TYPE #define NVOS_STATUS_ERROR_INVALID_ARGUMENT NV_ERR_INVALID_ARGUMENT #define NVOS_STATUS_ERROR_INVALID_BASE NV_ERR_INVALID_BASE diff --git a/src/nvidia/generated/g_chipset_nvoc.h b/src/nvidia/generated/g_chipset_nvoc.h index 8635511ef..96635df25 100644 --- a/src/nvidia/generated/g_chipset_nvoc.h +++ b/src/nvidia/generated/g_chipset_nvoc.h @@ -157,6 +157,9 @@ struct PCIECONFIGSPACEBASE #define CL_AER_ERROR_SOURCE (CL_AER_BEGIN + 0x34) #define CL_AER_END (CL_AER_BEGIN + 0x34) +// Advanced Error Reporting Root Error Status ERR_COR Subclass Capable Mask +#define CL_AER_ROOT_ERROR_STATUS_ERR_COR_SUBCLASS_MASK (NVBIT32(7) | NVBIT32(8)) + // PCI Express Device Capabilities 2 #define CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT NVBIT(6) #define CL_PCIE_DEV_CAP_2_ATOMIC_32BIT NVBIT(7) diff --git a/src/nvidia/generated/g_gpu_access_nvoc.h b/src/nvidia/generated/g_gpu_access_nvoc.h index 3a6e29e0c..ebf08fe81 100644 --- a/src/nvidia/generated/g_gpu_access_nvoc.h +++ b/src/nvidia/generated/g_gpu_access_nvoc.h @@ -228,6 +228,14 @@ void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 v // Get the address of a register given the Aperture and offset. #define REG_GET_ADDR(ap, offset) ioaprtGetRegAddr(ap, offset) +// +// These UNCHECKED macros are provided for extenuating circumstances to avoid the 0xbadf +// sanity checking done by the usual register read utilities and must not be used generally +// +// +#define GPU_REG_RD08_UNCHECKED(g,a) osDevReadReg008(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a) +#define GPU_REG_RD32_UNCHECKED(g,a) osDevReadReg032(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a) + // GPU macros defined in terms of DEV_ macros #define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a) #define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a) diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index ef64fb83d..2f43327a4 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -391,6 +391,18 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, NV_FALSE); pThis->setProperty(pThis, PDB_PROP_GPU_RECOVERY_DRAIN_P2P_REQUIRED, NV_FALSE); + // NVOC Property Hal field -- PDB_PROP_GPU_REUSE_INIT_CONTING_MEM + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) ) || + ( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000ec1UL) )) /* ChipHal: GB100 | GB102 | GB10B | GB202 | GB203 | GB205 | GB206 | GB207 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM, NV_TRUE); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM, NV_FALSE); + } + // NVOC Property Hal field -- PDB_PROP_GPU_RUSD_POLLING_SUPPORT_MONOLITHIC if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xd1f0f800UL) ) || ( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000ec1UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB202 | GB203 | GB205 | GB206 | GB207 */ diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index ad476afba..7f9e1adbf 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -1073,7 +1073,7 @@ struct OBJGPU { NvBool (*__gpuIsInternalSkuFuseEnabled__)(struct OBJGPU * /*this*/); // halified (2 hals) body NvBool (*__gpuGetIsCmpSku__)(struct OBJGPU * /*this*/); // halified (2 hals) body - // 114 PDB properties + // 115 PDB properties NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED; NvBool PDB_PROP_GPU_IN_STANDBY; NvBool PDB_PROP_GPU_IN_HIBERNATE; @@ -1187,6 +1187,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_FASTPATH_SEQ_ENABLED; NvBool PDB_PROP_GPU_PREPARING_FULLCHIP_RESET; NvBool PDB_PROP_GPU_RECOVERY_DRAIN_P2P_REQUIRED; + NvBool PDB_PROP_GPU_REUSE_INIT_CONTING_MEM; NvBool PDB_PROP_GPU_RUSD_POLLING_SUPPORT_MONOLITHIC; // Data members @@ -1247,6 +1248,8 @@ struct OBJGPU { DEVICE_MAPPING *pDeviceMappingsByDeviceInstance[12]; void *gpuCfgAddr; TIMEOUT_DATA timeoutData; + NvBool bBug5203024OverrideTimeoutsRegkeySet; + NvU32 bug5203024OverrideTimeouts; NvU32 computeModeRules; NvS32 computeModeRefCount; NvHandle hComputeModeReservation; @@ -1427,6 +1430,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU #define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST #define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP +#define PDB_PROP_GPU_REUSE_INIT_CONTING_MEM_BASE_CAST +#define PDB_PROP_GPU_REUSE_INIT_CONTING_MEM_BASE_NAME PDB_PROP_GPU_REUSE_INIT_CONTING_MEM #define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_CAST #define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_NAME PDB_PROP_GPU_IN_FATAL_ERROR #define PDB_PROP_GPU_VGA_ENABLED_BASE_CAST diff --git a/src/nvidia/generated/g_kern_disp_nvoc.h b/src/nvidia/generated/g_kern_disp_nvoc.h index ade3e1e1d..bbb77271e 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.h +++ b/src/nvidia/generated/g_kern_disp_nvoc.h @@ -14,7 +14,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -212,12 +212,13 @@ struct KernelDisplay { NvU32 (*__kdispServiceAwakenIntr__)(OBJGPU *, struct KernelDisplay * /*this*/, struct THREAD_STATE_NODE *); // halified (2 hals) body NV_STATUS (*__kdispComputeDpModeSettings__)(OBJGPU *, struct KernelDisplay * /*this*/, NvU32, DPMODESETDATA *, DPIMPINFO *); // halified (3 hals) body - // 6 PDB properties + // 7 PDB properties NvBool PDB_PROP_KDISP_IMP_ENABLE; NvBool PDB_PROP_KDISP_IMP_ALLOC_BW_IN_KERNEL_RM_DEF; NvBool PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE; NvBool PDB_PROP_KDISP_IN_AWAKEN_INTR; NvBool PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE; + NvBool PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED; // Data members struct DisplayInstanceMemory *pInst; @@ -302,6 +303,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelDisplay; #define PDB_PROP_KDISP_IMP_ENABLE_BASE_NAME PDB_PROP_KDISP_IMP_ENABLE #define PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE_BASE_CAST #define PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE_BASE_NAME PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE +#define PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED_BASE_CAST +#define PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED_BASE_NAME PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED NV_STATUS __nvoc_objCreateDynamic_KernelDisplay(KernelDisplay**, Dynamic*, NvU32, va_list); diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index c7f5b6741..d1ab8103b 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -5420,6 +5420,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2BB1, 0x204b, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" }, { 0x2BB1, 0x204b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" }, { 0x2BB1, 0x204b, 0x17aa, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" }, + { 0x2BB3, 0x204d, 0x1028, "NVIDIA RTX PRO 5000 Blackwell" }, + { 0x2BB3, 0x204d, 0x103c, "NVIDIA RTX PRO 5000 Blackwell" }, + { 0x2BB3, 0x204d, 0x10de, "NVIDIA RTX PRO 5000 Blackwell" }, + { 0x2BB3, 0x204d, 0x17aa, "NVIDIA RTX PRO 5000 Blackwell" }, { 0x2BB4, 0x204c, 0x1028, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" }, { 0x2BB4, 0x204c, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" }, { 0x2BB4, 0x204c, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" }, @@ -5430,6 +5434,9 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2C19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" }, { 0x2C58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" }, { 0x2C59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" }, + { 0x2D04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Ti" }, + { 0x2D18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" }, + { 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" }, { 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" }, { 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" }, { 0x2F58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" }, diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 58f88c9a9..446e675a4 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -8758,6 +8758,66 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [576] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccess_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*flags=*/ 0x44u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803090u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkPRMAccess" +#endif + }, + { /* [577] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*flags=*/ 0x44u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803091u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPRM" +#endif + }, + { /* [578] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*flags=*/ 0x44u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803093u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPTASV2" +#endif + }, + { /* [579] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + /*flags=*/ 0x44u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803094u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM" +#endif + }, + { /* [580] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8772,7 +8832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [577] */ + { /* [581] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8787,7 +8847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [578] */ + { /* [582] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8802,7 +8862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [579] */ + { /* [583] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8817,7 +8877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [580] */ + { /* [584] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8832,7 +8892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [581] */ + { /* [585] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8847,7 +8907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [582] */ + { /* [586] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8862,7 +8922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [583] */ + { /* [587] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8877,7 +8937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [584] */ + { /* [588] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8892,7 +8952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetVolatileCounts" #endif }, - { /* [585] */ + { /* [589] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8907,7 +8967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [586] */ + { /* [590] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10244u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8922,7 +8982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [587] */ + { /* [591] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8937,7 +8997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [588] */ + { /* [592] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x108u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8952,7 +9012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [589] */ + { /* [593] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40549u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8967,7 +9027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [590] */ + { /* [594] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8982,7 +9042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats" #endif }, - { /* [591] */ + { /* [595] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8997,7 +9057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetVgpuHeapStats" #endif }, - { /* [592] */ + { /* [596] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x248u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9012,7 +9072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLibosGetHeapStats" #endif }, - { /* [593] */ + { /* [597] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x248u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9027,7 +9087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [594] */ + { /* [598] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9042,7 +9102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [595] */ + { /* [599] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9057,7 +9117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [596] */ + { /* [600] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9072,7 +9132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [597] */ + { /* [601] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xbu) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9087,7 +9147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [598] */ + { /* [602] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9102,7 +9162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [599] */ + { /* [603] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9117,7 +9177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [600] */ + { /* [604] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9132,7 +9192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [601] */ + { /* [605] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9147,7 +9207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [602] */ + { /* [606] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9162,7 +9222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [603] */ + { /* [607] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9177,7 +9237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [604] */ + { /* [608] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9192,7 +9252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [605] */ + { /* [609] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1d0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9207,7 +9267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [606] */ + { /* [610] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9222,7 +9282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [607] */ + { /* [611] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9237,7 +9297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [608] */ + { /* [612] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9252,7 +9312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [609] */ + { /* [613] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9267,7 +9327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [610] */ + { /* [614] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9282,7 +9342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalFreeStates" #endif }, - { /* [611] */ + { /* [615] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9297,7 +9357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetFrameRateLimiterStatus" #endif }, - { /* [612] */ + { /* [616] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9312,7 +9372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuHeterogeneousMode" #endif }, - { /* [613] */ + { /* [617] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9327,7 +9387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [614] */ + { /* [618] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9342,7 +9402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlSetEcThrottleMode" #endif }, - { /* [615] */ + { /* [619] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -9596,7 +9656,7 @@ NV_STATUS __nvoc_up_thunk_Notifier_subdeviceGetOrAllocNotifShare(struct Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 616, + /*numEntries=*/ 620, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -10301,6 +10361,26 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkPRMAccessPLIB__ = &subdeviceCtrlCmdNvlinkPRMAccessPLIB_IMPL; #endif + // subdeviceCtrlCmdNvlinkPRMAccessPTASV2 -- exported (id=0x20803093) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + pThis->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__ = &subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL; +#endif + + // subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM -- exported (id=0x20803094) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + pThis->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__ = &subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL; +#endif + + // subdeviceCtrlCmdNvlinkPRMAccessPPRM -- exported (id=0x20803091) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + pThis->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__ = &subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL; +#endif + + // subdeviceCtrlCmdNvlinkPRMAccess -- exported (id=0x20803090) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) + pThis->__subdeviceCtrlCmdNvlinkPRMAccess__ = &subdeviceCtrlCmdNvlinkPRMAccess_IMPL; +#endif + // subdeviceCtrlCmdNvlinkGetPlatformInfo -- exported (id=0x20803083) #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) pThis->__subdeviceCtrlCmdNvlinkGetPlatformInfo__ = &subdeviceCtrlCmdNvlinkGetPlatformInfo_IMPL; @@ -10937,6 +11017,16 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) pThis->__subdeviceCtrlCmdKGrGetCtxswStats__ = &subdeviceCtrlCmdKGrGetCtxswStats_IMPL; #endif +} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s). + +// Vtable initialization 2/3 +static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // subdeviceCtrlCmdKGrGetCtxBufferSize -- exported (id=0x20801218) #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x18u) @@ -10957,16 +11047,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) pThis->__subdeviceCtrlCmdKGrGetCurrentResidentChannel__ = &subdeviceCtrlCmdKGrGetCurrentResidentChannel_IMPL; #endif -} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s). - -// Vtable initialization 2/3 -static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // subdeviceCtrlCmdKGrGetVatAlarmData -- exported (id=0x2080121d) #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u) @@ -12258,6 +12338,16 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400c0u) pThis->__subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer__ = &subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer_IMPL; #endif +} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s). + +// Vtable initialization 3/3 +static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer -- exported (id=0x20800a9c) #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400c0u) @@ -12278,16 +12368,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u) pThis->__subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer__ = &subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_IMPL; #endif -} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s). - -// Vtable initialization 3/3 -static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // subdeviceCtrlCmdCeGetPhysicalCaps -- exported (id=0x20802a07) #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x301d0u) @@ -12978,10 +13058,10 @@ static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u) pThis->__subdeviceSpdmRetrieveTranscript__ = &subdeviceSpdmRetrieveTranscript_IMPL; #endif -} // End __nvoc_init_funcTable_Subdevice_3 with approximately 138 basic block(s). +} // End __nvoc_init_funcTable_Subdevice_3 with approximately 142 basic block(s). -// Initialize vtable(s) for 646 virtual method(s). +// Initialize vtable(s) for 650 virtual method(s). void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { // Per-class vtable definition @@ -13100,7 +13180,7 @@ void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspe pThis->__nvoc_base_Notifier.__nvoc_vtable = &vtable.Notifier; // (notify) super pThis->__nvoc_vtable = &vtable; // (subdevice) this - // Initialize vtable(s) with 616 per-object function pointer(s). + // Initialize vtable(s) with 620 per-object function pointer(s). // To reduce stack pressure with some unoptimized builds, the logic is distributed among 3 functions. __nvoc_init_funcTable_Subdevice_1(pThis, pRmhalspecowner); __nvoc_init_funcTable_Subdevice_2(pThis, pRmhalspecowner); diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 70dcdd719..29ca16e5c 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -148,7 +148,7 @@ struct Subdevice { struct Notifier *__nvoc_pbase_Notifier; // notify super struct Subdevice *__nvoc_pbase_Subdevice; // subdevice - // Vtable with 616 per-object function pointers + // Vtable with 620 per-object function pointers NV_STATUS (*__subdeviceCtrlCmdBiosGetInfoV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *); // halified (2 hals) exported (id=0x20800810) body NV_STATUS (*__subdeviceCtrlCmdBiosGetNbsiV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS *); // exported (id=0x2080080e) NV_STATUS (*__subdeviceCtrlCmdBiosGetSKUInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *); // halified (2 hals) exported (id=0x20800808) @@ -269,6 +269,10 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPPSLS__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS *); // exported (id=0x2080307e) NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMLPC__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS *); // exported (id=0x2080307f) NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPLIB__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS *); // exported (id=0x20803080) + NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *); // exported (id=0x20803093) + NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *); // exported (id=0x20803094) + NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPPRM__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *); // exported (id=0x20803091) + NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccess__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *); // exported (id=0x20803090) NV_STATUS (*__subdeviceCtrlCmdNvlinkGetPlatformInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *); // exported (id=0x20803083) NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice * /*this*/, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *); // exported (id=0x20800601) NV_STATUS (*__subdeviceCtrlCmdI2cWriteBuffer__)(struct Subdevice * /*this*/, NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS *); // exported (id=0x20800602) @@ -1121,6 +1125,14 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkPRMAccessMLPC(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessMLPC_DISPATCH(arg_this, arg2) #define subdeviceCtrlCmdNvlinkPRMAccessPLIB_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPLIB__ #define subdeviceCtrlCmdNvlinkPRMAccessPLIB(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPLIB_DISPATCH(arg_this, arg2) +#define subdeviceCtrlCmdNvlinkPRMAccessPTASV2_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__ +#define subdeviceCtrlCmdNvlinkPRMAccessPTASV2(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPTASV2_DISPATCH(arg_this, arg2) +#define subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__ +#define subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_DISPATCH(arg_this, arg2) +#define subdeviceCtrlCmdNvlinkPRMAccessPPRM_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__ +#define subdeviceCtrlCmdNvlinkPRMAccessPPRM(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPPRM_DISPATCH(arg_this, arg2) +#define subdeviceCtrlCmdNvlinkPRMAccess_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccess__ +#define subdeviceCtrlCmdNvlinkPRMAccess(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccess_DISPATCH(arg_this, arg2) #define subdeviceCtrlCmdNvlinkGetPlatformInfo_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkGetPlatformInfo__ #define subdeviceCtrlCmdNvlinkGetPlatformInfo(arg_this, arg2) subdeviceCtrlCmdNvlinkGetPlatformInfo_DISPATCH(arg_this, arg2) #define subdeviceCtrlCmdI2cReadBuffer_FNPTR(pSubdevice) pSubdevice->__subdeviceCtrlCmdI2cReadBuffer__ @@ -2703,6 +2715,22 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPLIB_DISPATCH(struct Subd return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPLIB__(arg_this, arg2); } +static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPTASV2_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *arg2) { + return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__(arg_this, arg2); +} + +static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *arg2) { + return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__(arg_this, arg2); +} + +static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPRM_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *arg2) { + return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__(arg_this, arg2); +} + +static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccess_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *arg2) { + return arg_this->__subdeviceCtrlCmdNvlinkPRMAccess__(arg_this, arg2); +} + static inline NV_STATUS subdeviceCtrlCmdNvlinkGetPlatformInfo_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *arg2) { return arg_this->__subdeviceCtrlCmdNvlinkGetPlatformInfo__(arg_this, arg2); } @@ -5085,6 +5113,14 @@ NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMLPC_IMPL(struct Subdevice *arg1, NV208 NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPLIB_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS *arg2); +NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *arg2); + +NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *arg2); + +NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *arg2); + +NV_STATUS subdeviceCtrlCmdNvlinkPRMAccess_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *arg2); + NV_STATUS subdeviceCtrlCmdNvlinkGetPlatformInfo_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *arg2); NV_STATUS subdeviceCtrlCmdI2cReadBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams); diff --git a/src/nvidia/inc/kernel/platform/nvpcf.h b/src/nvidia/inc/kernel/platform/nvpcf.h index 4f7d10973..02a9a9f50 100644 --- a/src/nvidia/inc/kernel/platform/nvpcf.h +++ b/src/nvidia/inc/kernel/platform/nvpcf.h @@ -83,6 +83,7 @@ typedef struct #define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22 (0x22) #define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23 (0x23) #define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24 (0x24) +#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25 (0x25) #define NVPCF_CONTROLLER_STATIC_TABLE_MAX_ENTRIES (8) // format for 2.0 and 2.1 @@ -184,8 +185,9 @@ typedef struct #define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FILTER_RESERVED 31:16 // Param0 -#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_INCREASE_GAIN 15:0 +#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_INCREASE_GAIN 15:0 #define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_DECREASE_GAIN 31:16 +#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V25_PARAM0_CPU_TDP_TYPE 4:1 // Param1 #define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM1_QBOOST_DC_SUPPORT 0:0 @@ -196,6 +198,10 @@ typedef struct #define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_SIZE_05 (0x05U) #define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_FMT_SIZE_05 ("1b1d") +// Param0 +#define NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_ONLY (0x00) +#define NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_AC (0x01) + /*! * Static system controller header table v2.2, unpacked */ diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index b2e80c50d..30cb24120 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -64,7 +64,7 @@ // Type Dword // Change all RM internal timeouts to experiment with Bug 5203024. // -// Some timeouts may still silently clamp to differnt min/max values and this +// Some timeouts may still silently clamp to different min/max values and this // regkey does NOT validate their range. // #define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT "RmOverrideInternalTimeoutsMs" @@ -84,6 +84,20 @@ #define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_FECS_WATCHDOG_TIMEOUT 26:26 +// +// This regkey is experimental +// +// Type Dword +// Change video Watchdog and GP timeouts to experiment with Bug 5203024. +// Stores the timeout value in ms. +// If this regkey is set and has non-zero value, also disables MB timeouts. +// +// Some timeouts may still silently clamp to different min/max values and this +// regkey does NOT validate their range. +// +#define NV_REG_STR_RM_BUG5203024_OVERRIDE_VIDEO_TIMEOUT "RmVideoEngineTimeoutMs" + + // // Type Dword // Override default RM timeout. Measured in milliseconds. @@ -1332,6 +1346,11 @@ #define NV_REG_STR_RM_INTR_LOCKING_MODE_DEFAULT (0x00000000) #define NV_REG_STR_RM_INTR_LOCKING_MODE_INTR_MASK (0x00000001) +#define NV_REG_INTERNAL_PANEL_DISCONNECTED "RMInternalPanelDisconnected" +#define NV_REG_INTERNAL_PANEL_DISCONNECTED_DISABLE 0x00000000 +#define NV_REG_INTERNAL_PANEL_DISCONNECTED_ENABLE 0x00000001 +#define NV_REG_INTERNAL_PANEL_DISCONNECTED_DEFAULT RM_REG_INTERNAL_PANEL_DISCONNECTED_DISABLE + #define NV_REG_STR_RM_PER_INTR_DPC_QUEUING "RMDisablePerIntrDPCQueueing" // Type DWORD // This regkey is used to disable per interrupt DPC queuing. @@ -1398,14 +1417,14 @@ #define NV_REG_STR_RM_RC_WATCHDOG_DEFAULT NV_REG_STR_RM_RC_WATCHDOG_ENABLE #define NV_REG_STR_RM_WATCHDOG_TIMEOUT "RmWatchDogTimeOut" -#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 0x00000007 -#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 0x0000000C -#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW +#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 5 +#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 60 +#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT 7 -#define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval" -#define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 0x00000007 -#define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 0x0000000C -#define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW +#define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval" +#define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 5 +#define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 30 +#define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT 7 // Enable/Disable watchcat in GSP-Plugin for Guest RPC // Default is Enabled @@ -2620,6 +2639,19 @@ #define NV_REG_STR_RM_RUSD_POLLING_INTERVAL_MIN 100 #define NV_REG_STR_RM_RUSD_POLLING_INTERVAL_MAX 1000 +// +// Type: DWORD +// This regkey enables some path to reuse the initially allocated continguous memory +// instead of freeing it dynamically which causes memory fragmentation and +// under low available memory configuration the allocation could fail and leads to BSOD +// Enable the key to reuse the initially allocated mem withoug free and reallocate +// - Default for Blackwell and up +// Disable the key to free and allocate dynamically +// +#define NV_REG_STR_RM_INIT_MEM_REUSE "RmInitMemReuse" +#define NV_REG_STR_RM_INIT_MEM_REUSE_ENABLE 0x00000001 +#define NV_REG_STR_RM_INIT_MEM_REUSE_DISABLE 0x00000000 + // // Type DWORD (Boolean) // This regkey controls the use of BAR1 SPA instead of GPA for p2p subsystems diff --git a/src/nvidia/kernel/inc/gpuvideo/rmifvideng.h b/src/nvidia/kernel/inc/gpuvideo/rmifvideng.h index 8296b1496..0be774785 100644 --- a/src/nvidia/kernel/inc/gpuvideo/rmifvideng.h +++ b/src/nvidia/kernel/inc/gpuvideo/rmifvideng.h @@ -85,8 +85,20 @@ typedef struct * You can reorder or change below this point but update version. * Make sure to align it to 16B as ucode expect 16byte alignment to DMA efficiently. */ - NvU32 videoPgPmuHandshake; // Handshake between PMU and Video Ucode for SW controlled IDLE signal. - NvU64 rsvd2; // reserved field + NvU32 videoPgPmuHandshake; // Handshake between PMU and Video Ucode for SW controlled IDLE signal. + + /* + * WAR to avoid triggering HS signing on older chips, as these bootargs are only used on RISCV anyways. + * Always define videngTimeoutMs for RM builds. Assumption is that ENG_TYPE will be undefined for RM builds + * Only define it in video ucode builds that enable GB10X_OVERRIDE_TIMEOUT in build cfgs. + */ +#if (!defined(ENG_TYPE) || defined(GB10X_OVERRIDE_TIMEOUT)) + NvU32 videngTimeoutMs; // SW WAR for bug 5203864, increasing timeouts on GB10x via regkey RmOverrideInternalTimeoutsMs. + // Specify the timeout value in ms. If the value is 0, do not override the timeouts sent from KMD and/or UMD. + NvU32 rsvd2; // reserved field +#else + NvU64 rsvd2; // reserved field +#endif } NV_VIDENG_BOOT_PARAMS, *PNV_VIDENG_BOOT_PARAMS; #endif // RMIFVIDENG_H diff --git a/src/nvidia/src/kernel/compute/imex_session_api.c b/src/nvidia/src/kernel/compute/imex_session_api.c index 1eaac97db..091735401 100644 --- a/src/nvidia/src/kernel/compute/imex_session_api.c +++ b/src/nvidia/src/kernel/compute/imex_session_api.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -339,7 +339,7 @@ imexsessionapiDestruct_IMPL if (_checkDanglingExports(RES_GET_CLIENT(pImexSessionApi))) { fabricDisableMemAlloc(pFabric); - NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, disabled fabric allocations!\n"); + NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, disabled fabric allocations\n"); } // Invalidate export cache to block future imports on this node ID. @@ -361,7 +361,7 @@ imexsessionapiDestruct_IMPL { if (rcAndDisableOutstandingClientsWithImportedMemory(NULL, NV_FABRIC_INVALID_NODE_ID)) { - NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, robust channel recovery invoked!\n"); + NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, robust channel recovery invoked\n"); } } } @@ -426,7 +426,10 @@ imexsessionapiCtrlCmdDisableImporters_IMPL return NV_ERR_NOT_SUPPORTED; if (rcAndDisableOutstandingClientsWithImportedMemory(NULL, pParams->nodeId)) - NV_PRINTF(LEVEL_ERROR, "nvidia-imex daemon has invoked robust channel recovery!\n"); + { + NV_PRINTF(LEVEL_ERROR, "nvidia-imex daemon has invoked robust channel recovery for remote node: %u\n", + pParams->nodeId); + } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c index e9e7012e1..d9d235d85 100644 --- a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c +++ b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #include "gpu/gpu.h" +#include "gpu/gpu_access.h" #include "gpu/gpu_child_class_defs.h" #include "os/os.h" #include "nverror.h" @@ -101,7 +102,7 @@ gpuReadPassThruConfigReg_GH100 NvU32 *pData ) { - *pData = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index); + *pData = GPU_REG_RD32_UNCHECKED(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index b90fa2906..932e7b104 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -102,6 +102,7 @@ kdispConstructEngine_IMPL(OBJGPU *pGpu, ENGDESCRIPTOR engDesc) { NV_STATUS status; + NvU32 data; // // NOTE: DO NOT call IpVersion _HAL functions in ConstructEngine. @@ -140,6 +141,20 @@ kdispConstructEngine_IMPL(OBJGPU *pGpu, pKernelDisplay->pLowLatencySpinLock = (PORT_SPINLOCK *) portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); NV_ASSERT_OR_RETURN((pKernelDisplay->pLowLatencySpinLock != NULL), NV_ERR_INSUFFICIENT_RESOURCES); + if ((osReadRegistryDword(pGpu, NV_REG_INTERNAL_PANEL_DISCONNECTED, &data) == NV_OK) + && (data == NV_REG_INTERNAL_PANEL_DISCONNECTED_ENABLE)) + { + pKernelDisplay->setProperty(pKernelDisplay, + PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED, + NV_TRUE); + } + else + { + pKernelDisplay->setProperty(pKernelDisplay, + PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED, + NV_FALSE); + } + return status; } @@ -342,14 +357,17 @@ kdispInitBrightcStateLoad_IMPL(OBJGPU *pGpu, portMemSet(pBrightcInfo, 0, sizeof(*pBrightcInfo)); pBrightcInfo->status = status; - if ((pKernelDisplay != NULL) && (pKernelDisplay->pStaticInfo->internalDispActiveMask != 0) && !bInternalSkuFuseEnabled) + if ((pKernelDisplay != NULL) + && (pKernelDisplay->pStaticInfo->internalDispActiveMask != 0) + && !(bInternalSkuFuseEnabled + || (pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED)))) { // Fill in the Backlight Method Data. pBrightcInfo->backLightDataSize = sizeof(pBrightcInfo->backLightData); status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_GETBACKLIGHT, (NvU32 *)(pBrightcInfo->backLightData), &pBrightcInfo->backLightDataSize); - pBrightcInfo->status = status; + pBrightcInfo->status = status; } status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c index 2457fe0d3..bc220b50d 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,6 +52,7 @@ kchangrpAllocFaultMethodBuffers_GV100 HW_ENG_FAULT_METHOD_BUFFER *pFaultMthdBuf = NULL; NvU32 gfid = pKernelChannelGroup->gfid; TRANSFER_SURFACE surf = {0}; + NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM); // // Allocate method buffer if applicable @@ -91,6 +92,12 @@ kchangrpAllocFaultMethodBuffers_GV100 { // Get the right aperture/attribute faultBufApert = ADDR_SYSMEM; + + if (bReUseInitMem) + { + faultBufApert = ADDR_FBMEM; + } + faultBufAttr = NV_MEMORY_CACHED; memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_3, _FAULT_METHOD_BUFFER, pGpu->instLocOverrides3), "fault method buffer", &faultBufApert, &faultBufAttr); @@ -112,7 +119,7 @@ kchangrpAllocFaultMethodBuffers_GV100 goto fail; } - memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_34, + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_34, pFaultMthdBuf->pMemDesc); if (status != NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c index dec26693d..2f758e601 100644 --- a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -952,7 +952,6 @@ kfspGetGspBootArgs ) { NV_STATUS status = NV_OK; - ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); NV_ASSERT(pCC != NULL); @@ -993,6 +992,7 @@ kfspSetupGspImages PBINDATA_STORAGE pGspImageHash; PBINDATA_STORAGE pGspImageSignature; PBINDATA_STORAGE pGspImagePublicKey; + NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM); NvU32 pGspImageSize; NvU32 pGspImageMapSize; NvP64 pVaKernel = NULL; @@ -1029,15 +1029,17 @@ kfspSetupGspImages pGspImageSize = bindataGetBufferSize(pGspImage); pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000); + if ((pKernelFsp->pGspFmcMemdesc == NULL) || !bReUseInitMem) + { + NV_ASSERT(pKernelFsp->pGspFmcMemdesc == NULL); // If we assert the pointer becomes a zombie. + status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize, + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); - status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); - NV_ASSERT_OR_GOTO(status == NV_OK, failed); - - memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_7, - pKernelFsp->pGspFmcMemdesc); - NV_ASSERT_OR_GOTO(status == NV_OK, failed); - + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_7, + pKernelFsp->pGspFmcMemdesc); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + } status = memdescMap(pKernelFsp->pGspFmcMemdesc, 0, pGspImageMapSize, NV_TRUE, NV_PROTECT_READ_WRITE, &pVaKernel, &pPrivKernel); NV_ASSERT_OR_GOTO(status == NV_OK, failed); @@ -1292,6 +1294,7 @@ kfspPrepareBootCommands_GH100 NvBool bIsKeepWPRGc6D3Cold = pGpu->getProperty(pGpu, PDB_PROP_GPU_KEEP_WPR_ACROSS_GC6_SUPPORTED) && IS_GPU_GC6_STATE_EXITING(pGpu) && pKernelFsp->bUseKeepWPRGc6FSPCommand; + NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM); statusBoot = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); @@ -1374,13 +1377,17 @@ kfspPrepareBootCommands_GH100 // FSP (an unit inside GPU) and hence placed in unprotected sysmem // flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; - status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); - NV_ASSERT_OR_GOTO(status == NV_OK, failed); + if ((pKernelFsp->pSysmemFrtsMemdesc == NULL) || !bReUseInitMem) + { + NV_ASSERT(pKernelFsp->pSysmemFrtsMemdesc == NULL); // If we assert the pointer becomes a zombie. + status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); - memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_8, - pKernelFsp->pSysmemFrtsMemdesc); - NV_ASSERT_OR_GOTO(status == NV_OK, failed); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_8, + pKernelFsp->pSysmemFrtsMemdesc); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + } // Set up a kernel mapping for future use in RM status = memdescMap(pKernelFsp->pSysmemFrtsMemdesc, 0, frtsSize, NV_TRUE, diff --git a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c index b2d6cbc67..fbccaca79 100644 --- a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c +++ b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c @@ -242,7 +242,6 @@ kfspStateUnload_IMPL NvU32 flags ) { - kfspReleaseProxyImage(pGpu, pKernelFsp); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 8d3928997..708d527f8 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -6186,7 +6186,11 @@ gpuLogOobXidMessage_KERNEL { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status; + NvBool bGspFatalError = NV_FALSE; NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS params = {0}; + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + + bGspFatalError = pKernelGsp->bFatalError; // Exclude conditions that indicate issues with GSP communication. if ((xid == GSP_ERROR) || @@ -6196,7 +6200,8 @@ gpuLogOobXidMessage_KERNEL !pGpu->gspRmInitialized || pGpu->getProperty(pGpu, PDB_PROP_GPU_PREPARING_FULLCHIP_RESET) || pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST) || - !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED)) + !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED) || + bGspFatalError) { return; } diff --git a/src/nvidia/src/kernel/gpu/gpu_registry.c b/src/nvidia/src/kernel/gpu/gpu_registry.c index 915f335ef..08eeb841a 100644 --- a/src/nvidia/src/kernel/gpu/gpu_registry.c +++ b/src/nvidia/src/kernel/gpu/gpu_registry.c @@ -225,6 +225,12 @@ gpuInitRegistryOverrides_KERNEL pGpu->userSharedData.pollingFrequencyMs = NV_REG_STR_RM_RUSD_POLLING_INTERVAL_DEFAULT; pGpu->userSharedData.bPollFrequencyOverridden = NV_FALSE; } + + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_INIT_MEM_REUSE, &data32) == NV_OK) && + (data32 == NV_REG_STR_RM_INIT_MEM_REUSE_DISABLE)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM, NV_FALSE); + } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/gpu_timeout.c b/src/nvidia/src/kernel/gpu/gpu_timeout.c index 4d134e78a..65e411038 100644 --- a/src/nvidia/src/kernel/gpu/gpu_timeout.c +++ b/src/nvidia/src/kernel/gpu/gpu_timeout.c @@ -105,11 +105,15 @@ timeoutRegistryOverride { NvU32 data32 = 0; - NvU32 bug5203024OverrideTimeouts = ( - (osReadRegistryDword(pGpu, NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT, - &data32) == NV_OK) ? - data32 : - 0); + pGpu->bBug5203024OverrideTimeoutsRegkeySet = + (osReadRegistryDword(pGpu, + NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT, + &data32) == NV_OK); + + pGpu->bug5203024OverrideTimeouts = + pGpu->bBug5203024OverrideTimeoutsRegkeySet ? data32 : 0; + + NvU32 bug5203024OverrideTimeouts = pGpu->bug5203024OverrideTimeouts; NvBool bOverrideDefaultTimeout = (DRF_VAL(_REG_STR, _RM_BUG5203024_OVERRIDE_TIMEOUT, diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/blackwell/kernel_gsp_gb100.c b/src/nvidia/src/kernel/gpu/gsp/arch/blackwell/kernel_gsp_gb100.c index 285f70e07..56414f78c 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/blackwell/kernel_gsp_gb100.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/blackwell/kernel_gsp_gb100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -169,6 +169,8 @@ kgspServiceFatalHwError_GB100 NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_IRQSTAT_FATAL_ERROR PENDING error_code 0x%x\n", errorCode); MODS_ARCH_ERROR_PRINTF("NV_PGSP_FALCON_IRQSTAT_FATAL_ERROR=0x%x\n", errorCode); + pKernelGsp->bFatalError = NV_TRUE; + // Poison error if (FLD_TEST_DRF(_PGSP, _RISCV_FAULT_CONTAINMENT_SRCSTAT, _GLOBAL_MEM, _FAULTED, errorCode)) { @@ -190,9 +192,8 @@ kgspServiceFatalHwError_GB100 else { nvErrorLog_va((void *)pGpu, ROBUST_CHANNEL_CONTAINED_ERROR, "GSP-RISCV instance 0 fatal error"); + NV_ASSERT_OK(gpuMarkDeviceForReset(pGpu)); } - pKernelGsp->bFatalError = NV_TRUE; kgspRcAndNotifyAllChannels(pGpu, pKernelGsp, ROBUST_CHANNEL_CONTAINED_ERROR, NV_TRUE); - NV_ASSERT_OK(gpuMarkDeviceForReset(pGpu)); } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index 84dd3a2a3..5dea0a07f 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -333,6 +333,13 @@ memmgrTestCeUtils NvU32 vidmemData = 0xAABBCCDD; NvU32 sysmemData = 0x11223345; NV_STATUS status; + NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM); + + // Under low sysmem case we skip the testing since it requries extra memory + if (bReUseInitMem) + { + return NV_OK; + } NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils != NULL, NV_ERR_INVALID_STATE); diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c index 41927931f..9feef391a 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c @@ -111,6 +111,10 @@ subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_KERNEL pParams, sizeof(*pParams))); + // Skip translation if the request from root namespace. + if (osIsInitNs()) + return NV_OK; + // Now translate the sample's procId. numEntries = pParams->bufSize / sizeof (NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE); NV_ASSERT_OR_RETURN(numEntries <= NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL, diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c index c1ebf8e21..73036345d 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c @@ -451,7 +451,6 @@ krcCheckBusError_KERNEL NvU32 clDevCtrlStatus = 0; PcieAerCapability clAer; - // PCI-E provides extended error reporting if (pKernelBif == NULL || kbifGetBusIntfType_HAL(pKernelBif) != NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS) @@ -470,8 +469,8 @@ krcCheckBusError_KERNEL &clDevCtrlStatus) == NV_OK && clDevCtrlStatusFlags != 0) { - NV_PRINTF(LEVEL_ERROR, - "PCI-E corelogic status has pending errors (CL_PCIE_DEV_CTRL_STATUS = %08X):\n", + NV_PRINTF(LEVEL_INFO, + "PCI-E corelogic: Pending errors in DEV_CTRL_STATUS = %08X\n", clDevCtrlStatus); clDevCtrlStatusFlags_Org = clDevCtrlStatusFlags; @@ -479,7 +478,7 @@ krcCheckBusError_KERNEL if (clDevCtrlStatusFlags & NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR) { - NV_PRINTF(LEVEL_ERROR, " _CORR_ERROR_DETECTED\n"); + NV_PRINTF(LEVEL_INFO, "PCI-E corelogic: CORR_ERROR_DETECTED\n"); // not much interested in this one clDevCtrlStatusFlags &= ~NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR; @@ -487,63 +486,64 @@ krcCheckBusError_KERNEL if (clDevCtrlStatusFlags & NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR) { - NV_PRINTF(LEVEL_ERROR, " _NON_FATAL_ERROR_DETECTED\n"); + NV_PRINTF(LEVEL_INFO, "PCI-E corelogic: NON_FATAL_ERROR_DETECTED\n"); } if (clDevCtrlStatusFlags & NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR) { - NV_PRINTF(LEVEL_ERROR, " _FATAL_ERROR_DETECTED\n"); + NV_PRINTF(LEVEL_ERROR, "PCI-E corelogic: FATAL_ERROR_DETECTED\n"); } if (clDevCtrlStatusFlags & NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST) { - NV_PRINTF(LEVEL_ERROR, " _UNSUPP_REQUEST_DETECTED\n"); + NV_PRINTF(LEVEL_INFO, "PCI-E corelogic: UNSUPP_REQUEST_DETECTED\n"); } } // Corelogic AER if (pCl != NULL && clPcieReadAerCapability(pGpu, pCl, &clAer) == NV_OK && - (clAer.UncorrErrStatusReg != 0 || clAer.RooErrStatus != 0)) + (clAer.UncorrErrStatusReg != 0 || + (clAer.RooErrStatus & ~CL_AER_ROOT_ERROR_STATUS_ERR_COR_SUBCLASS_MASK) != 0)) { - NV_PRINTF(LEVEL_ERROR, - "PCE-I Advanced Error Reporting Corelogic Info:\n"); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, + "PCI-E Advanced Error Reporting Corelogic Info:\n"); + NV_PRINTF(LEVEL_NOTICE, " Uncorr Error Status Register : %08X\n", clAer.UncorrErrStatusReg); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Uncorr Error Mask Register : %08X\n", clAer.UncorrErrMaskReg); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Uncorr Error Severity Register : %08X\n", clAer.UncorrErrSeverityReg); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Corr Error Status Register : %08X\n", clAer.CorrErrStatusReg); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Corr Error Mask Register : %08X\n", clAer.CorrErrMaskReg); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Advanced Err Cap & Ctrl Register: %08X\n", clAer.AEcapCrtlReg); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Header Log [0-3] : %08X\n", clAer.HeaderLogReg.Header[0]); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Header Log [4-7] : %08X\n", clAer.HeaderLogReg.Header[1]); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Header Log [8-B] : %08X\n", clAer.HeaderLogReg.Header[2]); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Header Log [C-F] : %08X\n", clAer.HeaderLogReg.Header[3]); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Root Error Command Register : %08X\n", clAer.RootErrCmd); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Root Error Status : %08X\n", clAer.RooErrStatus); - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, " Error Source ID Register : %08X\n", clAer.ErrSrcReg); diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index 8e707104c..4221c5b5e 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -458,7 +458,6 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, data = NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO; if (osDmabufIsSupported() && - (!IS_VIRTUAL(pGpu)) && (!gpuIsApmFeatureEnabled(pGpu)) && (!NVCPU_IS_PPC64LE)) { diff --git a/src/nvidia/src/kernel/platform/acpi_common.c b/src/nvidia/src/kernel/platform/acpi_common.c index db6383151..6341418e8 100644 --- a/src/nvidia/src/kernel/platform/acpi_common.c +++ b/src/nvidia/src/kernel/platform/acpi_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,6 +40,9 @@ #include "mxm_spec.h" #include "gpu/gsp/gsp_static_config.h" #include "platform/nbsi/nbsi_read.h" +#include "nvrm_registry.h" + +#include "gpu/disp/kern_disp.h" // // DSM ACPI Routines common routines for Linux @@ -706,6 +709,17 @@ checkDsmCall NV_ASSERT_OR_RETURN(pInOut, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pSize, NV_ERR_INVALID_ARGUMENT); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + if (pKernelDisplay != NULL + && pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED)) + { + if (*pAcpiDsmFunction == ACPI_DSM_FUNCTION_NBCI) + { + return NV_ERR_NOT_SUPPORTED; + } + } + // Do any remapping of subfunction if function is current if (remapDsmFunctionAndSubFunction(pGpu, pAcpiDsmFunction, pAcpiDsmSubFunction) != NV_OK) { diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index dbcc913b9..abf5335fa 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -2601,6 +2601,7 @@ _controllerParseStaticTable_v22 switch (header.version) { + case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25: case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24: case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23: case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22: @@ -2639,10 +2640,12 @@ _controllerParseStaticTable_v22 } } + CONTROLLER_STATIC_TABLE_ENTRY_V22 entry = { 0 }; + // Parse each entry for (loop = 0; loop < header.entryCount; loop++) { - CONTROLLER_STATIC_TABLE_ENTRY_V22 entry = { 0 }; + portMemSet(&entry, 0, sizeof(entry)); NvU32 offset = header.headerSize + (loop * NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_SIZE_05); @@ -2671,6 +2674,28 @@ _controllerParseStaticTable_v22 } } + if (header.version == NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25) + { + switch(DRF_VAL(PCF_CONTROLLER_STATIC_TABLE_ENTRY_V25, _PARAM0, _CPU_TDP_TYPE,entry.flags0)) + { + case NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_ONLY: + { + pParams->cpuTdpControlType = QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY; + break; + } + case NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_AC: + { + pParams->cpuTdpControlType = QBOOST_CPU_TDP_CONTROL_TYPE_DC_AC; + break; + } + default: + { + pParams->cpuTdpControlType = QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY; + break; + } + } + } + pParams->version = (NvU8)header.version; pParams->samplingPeriodmS = CONTROLLER_GRP_DEFAULT_BASE_SAMPLING_PERIOD_MS; *pEntryCount = (NvU8)header.entryCount; diff --git a/src/nvidia/src/kernel/vgpu/rpc.c b/src/nvidia/src/kernel/vgpu/rpc.c index 2042a7ce0..55dc65972 100644 --- a/src/nvidia/src/kernel/vgpu/rpc.c +++ b/src/nvidia/src/kernel/vgpu/rpc.c @@ -9698,6 +9698,8 @@ NV_STATUS rpcDumpProtobufComponent_v18_12 if (IS_GSP_CLIENT(pGpu)) { rpc_dump_protobuf_component_v18_12 *rpc_params = &rpc_message->dump_protobuf_component_v18_12; + const NvU32 fixed_param_size = sizeof(rpc_message_header_v) + sizeof(*rpc_params); + NV_ASSERT_OR_RETURN(fixed_param_size <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE); status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT, sizeof(*rpc_params)); @@ -9709,7 +9711,7 @@ NV_STATUS rpcDumpProtobufComponent_v18_12 rpc_params->countOnly = ((pPrbEnc->flags & PRB_COUNT_ONLY) != 0); rpc_params->bugCheckCode = pNvDumpState->bugCheckCode; rpc_params->internalCode = pNvDumpState->internalCode; - rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize, prbEncBufLeft(pPrbEnc)); + rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize - fixed_param_size, prbEncBufLeft(pPrbEnc)); status = _issueRpcAndWait(pGpu, pRpc); diff --git a/version.mk b/version.mk index b746a69a9..fe94e16c7 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 570.144 +NVIDIA_VERSION = 570.153.02 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))