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This commit is contained in:
Andy Ritger
2023-01-05 10:40:27 -08:00
parent 9594cc0169
commit dac2350c7f
180 changed files with 9465 additions and 4853 deletions
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3
src/common/displayport/inc/dp_configcaps.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -245,6 +245,7 @@ namespace DisplayPort
public:
virtual bool getOuiSupported() = 0;
virtual AuxRetry::status setOuiSource(unsigned ouiId, const char * model, size_t modelNameLength, NvU8 chipRevision) = 0;
virtual bool getOuiSource(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) = 0;
virtual bool getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) = 0;
};

15
src/common/displayport/inc/dp_connectorimpl.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -89,6 +89,11 @@ namespace DisplayPort
Timer * timer; // OS provided timer services
Connector::EventSink * sink; // Event Sink
// Cached Source OUI for restoring eDP OUI when powering up
unsigned cachedSourceOUI;
char cachedSourceModelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1];
NvU8 cachedSourceChipRevision;
unsigned ouiId; // Sink ouiId
char modelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1]; // Device Model-name
bool bIgnoreSrcOuiHandshake; // Skip writing source OUI
@@ -294,6 +299,8 @@ namespace DisplayPort
bool bEnableFastLT;
NvU32 maxLinkRateFromRegkey;
bool bEnableOuiRestoring;
//
// Latency(ms) to apply between link-train and FEC enable for bug
// 2561206.
@@ -322,6 +329,12 @@ namespace DisplayPort
//
bool bDscCapBasedOnParent;
//
// MST device connnected to dock may issue IRQ for link lost.
// Send PowerDown path msg to suppress that.
//
bool bPowerDownPhyBeforeD3;
void sharedInit();
ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);

2
src/common/displayport/inc/dp_discovery.h
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@@ -57,7 +57,7 @@ namespace DisplayPort
bool videoSink; // Should be true when a video sink is supported
NvU64 maxTmdsClkRate;
Device():peerDevice(None),SDPStreams(0),SDPStreamSinks(0),dirty(false),videoSink(false)
Device():peerDevice(None),SDPStreams(0),SDPStreamSinks(0),dirty(false),videoSink(false),maxTmdsClkRate(0)
{
portMap.validMap = portMap.inputMap = portMap.internalMap = 0;
}

5
src/common/displayport/inc/dp_linkconfig.h
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@@ -385,6 +385,11 @@ namespace DisplayPort
void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn)
{
base_pbn = pbnForMode(modesetInfo);
if (bEnableFEC)
{
// IF FEC is enabled, we need to consider 3% overhead as per DP1.4 spec.
base_pbn = (NvU32)(divide_ceil(base_pbn * 100, 97));
}
slots = slotsForPBN(base_pbn);
slots_pbn = PBNForSlots(slots);
}

10
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,6 +59,12 @@
#define NV_DP_REGKEY_FORCE_EDP_ILR "DP_BYPASS_EDP_ILR_REV_CHECK"
// Regkey to enable OUI caching/restoring in release branch.
#define NV_DP_REGKEY_ENABLE_OUI_RESTORING "DP_ENABLE_OUI_RESTORING"
// Message to power down video stream before power down link (set D3)
#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY"
//
// DSC capability of downstream device should be decided based on device's own
// and its parent's DSC capability.
@@ -96,6 +102,8 @@ struct DP_REGKEY_DATABASE
bool bOptLinkKeptAliveSst;
bool bBypassEDPRevCheck;
bool bDscMstCapBug3143315;
bool bEnableOuiRestoring;
bool bPowerDownPhyBeforeD3;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

38
src/common/displayport/src/dp_configcaps.cpp
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -863,6 +863,42 @@ struct DPCDHALImpl : DPCDHAL
return bus.write(NV_DPCD_SOURCE_IEEE_OUI, &ouiBuffer[0], sizeof ouiBuffer);
}
virtual bool getOuiSource(unsigned &ouiId, char * modelName,
size_t modelNameBufferSize, NvU8 & chipRevision)
{
NvU8 ouiBuffer[16];
int address = NV_DPCD_SOURCE_IEEE_OUI;
if (caps.revisionMajor <= 0)
DP_ASSERT(0 && "Something is wrong, revision major should be > 0");
// If buffer size is larger than dev_id size, the extras are not used.
// If buffer size is smaller, than we can only get certain bytes.
if (modelNameBufferSize > NV_DPCD_SOURCE_DEV_ID_STRING__SIZE)
{
modelNameBufferSize = NV_DPCD_SOURCE_DEV_ID_STRING__SIZE;
}
if (AuxRetry::ack != bus.read(address, &ouiBuffer[0], sizeof ouiBuffer))
{
*modelName = 0;
ouiId = 0;
chipRevision = 0;
return false;
}
// The first 3 bytes are IEEE_OUI. 2 hex digits per register.
ouiId = ouiBuffer[0] | (ouiBuffer[1] << 8) | (ouiBuffer[2] << 16);
// Next 6 bytes are Device Identification String, copy as much as we can (limited buffer case).
unsigned int i;
for (i = 0; i < modelNameBufferSize; i++)
modelName[i] = ouiBuffer[3+i];
chipRevision = ouiBuffer[9];
return true;
}
virtual bool getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision)
{
NvU8 ouiBuffer[16];

71
src/common/displayport/src/dp_connectorimpl.cpp
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -188,6 +188,8 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bDisableSSC = dpRegkeyDatabase.bSscDisabled;
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bEnableOuiRestoring = dpRegkeyDatabase.bEnableOuiRestoring;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -704,6 +706,13 @@ create:
newDev->applyOUIOverrides();
if (main->isEDP() && this->bEnableOuiRestoring)
{
// Save Source OUI information for eDP.
hal->getOuiSource(cachedSourceOUI, &cachedSourceModelName[0],
sizeof(cachedSourceModelName), cachedSourceChipRevision);
}
fireEvents();
}
@@ -1178,7 +1187,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
this->isFECSupported() && // If GPU supports FEC
pDscParams && // If client sent DSC info
pDscParams->bCheckWithDsc && // If client wants to check with DSC
(dev && dev->isDSCPossible()) && // Either device or it's parent supports DSC
(dev && dev->devDoingDscDecompression) && // Either device or it's parent supports DSC
bFecCapable && // If path up to dsc decoding device supports FEC
(modesetParams.modesetInfo.bitsPerComponent != 6)) // DSC doesn't support bpc = 6
{
@@ -1239,9 +1248,13 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
(modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) ||
(modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422))
{
if (pDscParams->forceDsc == DSC_FORCE_ENABLE)
if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) ||
(modesetParams.modesetInfo.mode == DSC_DUAL))
{
// If DSC is force enabled then return failure here
//
// If DSC is force enabled or DSC_DUAL mode is requested,
// then return failure here
//
compoundQueryResult = false;
pDscParams->bEnableDsc = false;
return false;
@@ -1270,9 +1283,24 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16))) != NVT_STATUS_SUCCESS)
{
if (pDscParams->forceDsc == DSC_FORCE_ENABLE)
//
// If generating PPS failed
// AND
// (DSC is force enabled
// OR
// the requested DSC mode = DUAL)
//then
// return failure here
// Else
// we will check if non DSC path is possible.
//
// If dsc mode = DUAL failed to generate PPS and if we pursue
// non DSC path, DD will still follow 2Head1OR modeset path with
// DSC disabled, eventually leading to HW hang. Bug 3632901
//
if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) ||
(modesetParams.modesetInfo.mode == DSC_DUAL))
{
// If DSC is force enabled then return failure here
compoundQueryResult = false;
pDscParams->bEnableDsc = false;
return false;
@@ -2667,6 +2695,21 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
this->bFECEnable |= bEnableFEC;
highestAssessedLC.enableFEC(this->bFECEnable);
if (main->isEDP() && this->bEnableOuiRestoring)
{
// Power-up eDP and restore eDP OUI if it's powered off now.
bool bPanelPowerOn;
main->getEdpPowerData(&bPanelPowerOn, NULL);
if (!bPanelPowerOn)
{
main->configurePowerState(true);
hal->setOuiSource(cachedSourceOUI,
&cachedSourceModelName[0],
6 /* string length of ieeeOuiDevId */,
cachedSourceChipRevision);
}
}
// if failed, we're guaranteed that assessed link rate didn't meet the mode requirements
// isZombie() will catch this
bLinkTrainingStatus = trainLinkOptimized(getMaxLinkConfig());
@@ -3248,6 +3291,22 @@ void ConnectorImpl::powerdownLink(bool bPowerdownPanel)
powerOff.lanes = 0;
// Inform Sink about Main Link Power Down.
if (linkUseMultistream() && bPowerDownPhyBeforeD3)
{
PowerDownPhyMessage powerDownPhyMsg;
NakData nack;
for (Device * i = enumDevices(0); i; i=enumDevices(i))
{
if (i->isPlugged() && i->isVideoSink())
{
Address devAddress = ((DeviceImpl*)i)->address;
powerDownPhyMsg.set(devAddress.parent(), devAddress.tail(), NV_TRUE);
this->messageManager->send(&powerDownPhyMsg, nack);
}
}
}
//
// 1> If it is eDP and the power is not on, we don't need to put it into D3 here
// 2> If FEC is enabled then we have to put panel in D3 after powering down mainlink

36
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -920,23 +920,31 @@ void DeviceImpl::applyOUIOverrides()
if ((buffer[3] == 0x53) && (buffer[4] == 0x59) && (buffer[5] == 0x4E) && (buffer[6] == 0x41))
{
// For Synaptic VMM5331 and VMM5320, it only support MSA-Over-MST for DP after Firmware 5.4.5
if (buffer[7] == 0x53 &&
(buffer[8] == 0x31 || buffer[8] == 0x20))
if (buffer[7] == 0x53)
{
this->bSdpExtCapable = False;
//
// This flag will be checked only in DSC Pass through cases (MST).
// All Synaptics VMM53XX chips which support pass through can only support
// color formats that are listed in 0x69h even in pass through mode.
//
this->bDscPassThroughColorFormatWar = true;
//
// Check firmware version
// 0x50A: FW/SW Major Revision.
// 0x50B: FW/SW Minor Revision.
// 0x50C: Build Number.
//
if ((buffer[10] >= 0x06) ||
((buffer[10] == 0x05) && (buffer[11] >= 0x05)) ||
((buffer[10] == 0x05) && (buffer[11] == 0x04) && (buffer[12] >= 0x05)))
if ((buffer[8] == 0x31) || (buffer[8] == 0x20))
{
this->bSdpExtCapable = True;
this->bSdpExtCapable = False;
//
// Check firmware version
// 0x50A: FW/SW Major Revision.
// 0x50B: FW/SW Minor Revision.
// 0x50C: Build Number.
//
if ((buffer[10] >= 0x06) ||
((buffer[10] == 0x05) && (buffer[11] >= 0x05)) ||
((buffer[10] == 0x05) && (buffer[11] == 0x04) && (buffer[12] >= 0x05)))
{
this->bSdpExtCapable = True;
}
}
}
}

4
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -93,7 +93,9 @@ const struct
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_OUI_RESTORING, &dpRegkeyDatabase.bEnableOuiRestoring, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

13
src/common/displayport/src/dp_watermark.cpp
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@@ -852,21 +852,16 @@ bool DisplayPort::isModePossibleMSTWithFEC
unsigned DisplayPort::pbnForMode(const ModesetInfo & modesetInfo)
{
// When DSC is enabled consider depth will multiplied by 16
unsigned dsc_factor = modesetInfo.bEnableDsc ? 16 : 1;
//
// Calculate PBN in terms of 54/64 mbyte/sec
// round up by .6% for spread de-rate. Note: if we're not spreading our link
// this MUST still be counted. It's also to allow downstream links to be spread.
//
unsigned pbnForMode = (NvU32)(divide_ceil(modesetInfo.pixelClockHz * modesetInfo.depth * 1006 * 64 / 8,
(NvU64)54000000 *1000));
if(modesetInfo.bEnableDsc)
{
//
// When DSC is enabled consider depth will multiplied by 16 and also 3% FEC Overhead
// as per DP1.4 spec
pbnForMode = (NvU32)(divide_ceil(pbnForMode * 100, 97 * DSC_DEPTH_FACTOR));
}
(NvU64)54000000 * 1000 * dsc_factor));
return pbnForMode;
}