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525.78.01

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This commit is contained in:
Andy Ritger
2023-01-05 10:40:27 -08:00
parent 9594cc0169
commit dac2350c7f
180 changed files with 9465 additions and 4853 deletions
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10
src/common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c
View File

@@ -23,6 +23,7 @@
#include "flcn/haldefs_flcn_nvswitch.h"
#include "flcn/flcn_nvswitch.h"
#include "rmflcncmdif_nvswitch.h"
#include "flcnifcmn.h"
@@ -109,7 +110,10 @@ flcnQueueCmdPostBlocking
if (status != NV_OK)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
"Fatal, Failed to post command to SOE\n");
"Fatal, Failed to post command to SOE. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags,
pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd);
return status;
}
@@ -117,7 +121,9 @@ flcnQueueCmdPostBlocking
if (status == NV_ERR_TIMEOUT)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_TIMEOUT,
"Fatal, Timed out while waiting for SOE command completion\n");
"Fatal, Timed out while waiting for SOE command completion. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags,
pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd);
flcnQueueCmdCancel(device, pFlcn, *pSeqDesc);
}

7
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -119,6 +119,7 @@
_op(NvlStatus, nvswitch_deassert_link_reset, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvBool, nvswitch_is_soe_supported, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch) \
_op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_inforom_supported, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_spi_supported, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \
@@ -147,6 +148,7 @@
_op(void, nvswitch_initialize_oms_state, (nvswitch_device *device, INFOROM_OMS_STATE *pOmsState), _arch) \
_op(NvlStatus, nvswitch_oms_inforom_flush, (nvswitch_device *device), _arch) \
_op(void, nvswitch_inforom_ecc_get_total_errors, (nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, NvU64 *corCount, NvU64 *uncCount), _arch) \
_op(NvlStatus, nvswitch_inforom_load_obd, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_bbx_add_sxid, (nvswitch_device *device, NvU32 exceptionType, NvU32 data0, NvU32 data1, NvU32 data2), _arch) \
_op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \
@@ -218,7 +220,10 @@
_op(NvlStatus, nvswitch_service_minion_link, (nvswitch_device *device, NvU32 link_id), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_err_info, (nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret), _arch) \
_op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch)
_op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch)
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
_op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \

11
src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h
View File

@@ -74,8 +74,15 @@ struct inforom
struct
{
NvBool bValid;
NvU8 packedObject[INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE];
INFOROM_OBD_OBJECT_V1_XX object;
union {
NvU8 v1[INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE];
NvU8 v2[INFOROM_OBD_OBJECT_V2_XX_PACKED_SIZE];
} packedObject;
union {
INFOROM_OBJECT_HEADER_V1_00 header;
INFOROM_OBD_OBJECT_V1_XX v1;
INFOROM_OBD_OBJECT_V2_XX v2;
} object;
} OBD;
struct

6
src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h
View File

@@ -108,6 +108,12 @@ nvswitch_oms_inforom_flush_lr10
struct nvswitch_device *device
);
NvlStatus
nvswitch_inforom_load_obd_lr10
(
nvswitch_device *device
);
NvlStatus
nvswitch_bbx_add_sxid_lr10
(

1
src/common/nvswitch/kernel/inc/lr10/lr10.h
View File

@@ -652,6 +652,7 @@ NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_S
void nvswitch_setup_link_system_registers_lr10(nvswitch_device *device, nvlink_link *link);
void nvswitch_load_link_disable_settings_lr10(nvswitch_device *device, nvlink_link *link);
NvBool nvswitch_is_smbpbi_supported_lr10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_get_board_part_number_lr10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p);
NvlStatus nvswitch_ctrl_set_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p);
NvlStatus nvswitch_ctrl_get_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p);

1
src/common/nvswitch/kernel/inc/lr10/soe_lr10.h
View File

@@ -62,4 +62,5 @@ void nvswitch_soe_unregister_events_lr10(nvswitch_device *device);
void nvswitch_therm_soe_callback_lr10(nvswitch_device *device, union RM_FLCN_MSG *pMsg,
void *pParams, NvU32 seqDesc, NV_STATUS status);
NvlStatus nvswitch_soe_register_event_callbacks_lr10(nvswitch_device *device);
void nvswitch_soe_init_l2_state_lr10(nvswitch_device *device);
#endif //_SOE_LR10_H_

6
src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h
View File

@@ -79,6 +79,12 @@ nvswitch_inforom_ecc_get_total_errors_ls10
NvU64 *pUncorrectedTotal
);
NvlStatus
nvswitch_inforom_load_obd_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_bbx_add_sxid_ls10
(

5
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -371,6 +371,7 @@ typedef struct
_op(XAL, ) \
_op(XPL, ) \
_op(XTL, ) \
_op(XTL_CONFIG, ) \
_op(SAW, ) \
_op(SOE, ) \
_op(SMR, ) \
@@ -962,12 +963,14 @@ NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, Nv
NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params);
void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link);
void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link);
void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link);
void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link);
void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link);
NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask);
void nvswitch_service_minion_all_links_ls10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_get_board_part_number_ls10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p);
//
// SU generated functions
@@ -988,6 +991,8 @@ NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 lin
void nvswitch_service_minion_all_links_ls10(nvswitch_device *device);
NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device);
void nvswitch_set_error_rate_threshold_ls10(nvlink_link *link, NvBool bIsDefault);
void nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink_link *link, NvBool bEnable);
#endif //_LS10_H_

1
src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
View File

@@ -42,5 +42,6 @@ void nvswitch_soe_unregister_events_ls10(nvswitch_device *device);
NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device);
NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport);
NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport);
void nvswitch_soe_init_l2_state_ls10(nvswitch_device *device);
#endif //_SOE_LS10_H_

10
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b,
0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2,
0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043,
0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200,
0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d,
0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x62f5c2c4, 0xc41c2f31, 0x9af0cbcc, 0xb7efe098,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x5f24a73a, 0x55cea6d1, 0x59205a69, 0x18a31f2d,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

10
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b,
0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2,
0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043,
0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200,
0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d,
0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x62f5c2c4, 0xc41c2f31, 0x9af0cbcc, 0xb7efe098,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x5f24a73a, 0x55cea6d1, 0x59205a69, 0x18a31f2d,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

5
src/common/nvswitch/kernel/inforom/ifrro_nvswitch.c
View File

@@ -38,10 +38,7 @@ nvswitch_inforom_read_only_objects_load
return -NVL_ERR_NOT_SUPPORTED;
}
status = nvswitch_inforom_load_object(device, pInforom, "OBD",
INFOROM_OBD_OBJECT_V1_XX_FMT,
pInforom->OBD.packedObject,
&pInforom->OBD.object);
status = device->hal.nvswitch_inforom_load_obd(device);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Failed to load OBD object, rc:%d\n",

44
src/common/nvswitch/kernel/inforom/inforom_nvswitch.c
View File

@@ -493,7 +493,7 @@ _nvswitch_inforom_read_file
nvswitch_os_memset(pDmaBuf, 0, transferSize);
cmdSeqDesc = 0;
nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL,
SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout);
if (status != NV_OK)
@@ -591,7 +591,8 @@ _nvswitch_inforom_write_file
}
cmdSeqDesc = 0;
nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL,
SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout);
if (status != NV_OK)
@@ -899,6 +900,7 @@ done:
/*!
* Fill in the static identification data structure for the use by the SOE
* to be passed on to a BMC over the I2CS interface.
* For LR10 only so no HAL is needed.
*
* @param[in] device switch device pointer
* @param[in] pInforom INFOROM object pointer
@@ -916,13 +918,13 @@ nvswitch_inforom_read_static_data
#define _INFOROM_TO_SOE_STRING_COPY(obj, irName, soeName) \
{ \
NvU32 _i; \
ct_assert(NV_ARRAY_ELEMENTS(pInforom->obj.object.irName) <= \
ct_assert(NV_ARRAY_ELEMENTS(pInforom->obj.object.v1.irName) <= \
NV_ARRAY_ELEMENTS(pData->obj.soeName)); \
for (_i = 0; _i < NV_ARRAY_ELEMENTS(pInforom->obj.object.irName); ++_i) \
for (_i = 0; _i < NV_ARRAY_ELEMENTS(pInforom->obj.object.v1.irName); ++_i) \
{ \
pData->obj.soeName[_i] = (NvU8)(pInforom->obj.object.irName[_i] & 0xff); \
pData->obj.soeName[_i] = (NvU8)(pInforom->obj.object.v1.irName[_i] & 0xff); \
} \
if (NV_ARRAY_ELEMENTS(pInforom->obj.object.irName) < \
if (NV_ARRAY_ELEMENTS(pInforom->obj.object.v1.irName) < \
NV_ARRAY_ELEMENTS(pData->obj.soeName)) \
{ \
do \
@@ -935,21 +937,25 @@ nvswitch_inforom_read_static_data
if (pInforom->OBD.bValid)
{
pData->OBD.bValid = NV_TRUE;
pData->OBD.buildDate = (NvU32)pInforom->OBD.object.buildDate;
nvswitch_inforom_string_copy(pInforom->OBD.object.marketingName,
pData->OBD.marketingName,
NV_ARRAY_ELEMENTS(pData->OBD.marketingName));
/* This should be called for LR10 (i.e., version 1.xx) only */
if ((pInforom->OBD.object.header.version & 0xFF) == 1)
{
pData->OBD.bValid = NV_TRUE;
pData->OBD.buildDate = (NvU32)pInforom->OBD.object.v1.buildDate;
nvswitch_inforom_string_copy(pInforom->OBD.object.v1.marketingName,
pData->OBD.marketingName,
NV_ARRAY_ELEMENTS(pData->OBD.marketingName));
nvswitch_inforom_string_copy(pInforom->OBD.object.serialNumber,
pData->OBD.serialNum,
NV_ARRAY_ELEMENTS(pData->OBD.serialNum));
nvswitch_inforom_string_copy(pInforom->OBD.object.v1.serialNumber,
pData->OBD.serialNum,
NV_ARRAY_ELEMENTS(pData->OBD.serialNum));
//
// boardPartNum requires special handling, as its size exceeds that
// of its InfoROM representation
//
_INFOROM_TO_SOE_STRING_COPY(OBD, productPartNumber, boardPartNum);
//
// boardPartNum requires special handling, as its size exceeds that
// of its InfoROM representation
//
_INFOROM_TO_SOE_STRING_COPY(OBD, productPartNumber, boardPartNum);
}
}
if (pInforom->OEM.bValid)

19
src/common/nvswitch/kernel/lr10/inforom_lr10.c
View File

@@ -747,6 +747,25 @@ nvswitch_oms_set_device_disable_lr10
_oms_update_entry_checksum(pVerData->pNext);
}
NvlStatus
nvswitch_inforom_load_obd_lr10
(
nvswitch_device *device
)
{
struct inforom *pInforom = device->pInforom;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
return nvswitch_inforom_load_object(device, pInforom, "OBD",
INFOROM_OBD_OBJECT_V1_XX_FMT,
pInforom->OBD.packedObject.v1,
&pInforom->OBD.object.v1);
}
NvlStatus
nvswitch_bbx_add_sxid_lr10
(

2
src/common/nvswitch/kernel/lr10/link_lr10.c
View File

@@ -872,7 +872,7 @@ nvswitch_corelib_set_dl_link_mode_lr10
NVSWITCH_PRINT(device, ERROR,
"%s: link #%d is still in reset, cannot change link state\n",
__FUNCTION__, link->linkNumber);
return NVL_ERR_INVALID_STATE;
return -NVL_ERR_INVALID_STATE;
}
val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _LINK_STATE);

84
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -6403,8 +6403,22 @@ nvswitch_ctrl_get_fom_values_lr10
{
NvlStatus status;
NvU32 statData;
nvlink_link *link;
NVSWITCH_ASSERT(p->linkId < nvswitch_get_num_links(device));
link = nvswitch_get_link(device, p->linkId);
if (link == NULL)
{
NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n",
__FUNCTION__, p->linkId);
return -NVL_BAD_ARGS;
}
if (nvswitch_is_link_in_reset(device, link))
{
NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n",
__FUNCTION__, p->linkId);
return -NVL_ERR_INVALID_STATE;
}
status = nvswitch_minion_get_dl_status(device, p->linkId,
NV_NVLSTAT_TR16, 0, &statData);
@@ -6791,6 +6805,8 @@ nvswitch_post_init_device_setup_lr10
NVSWITCH_PRINT(device, SETUP, "Skipping INFOROM init\n");
}
nvswitch_soe_init_l2_state(device);
return NVL_SUCCESS;
}
@@ -7373,6 +7389,52 @@ nvswitch_ctrl_inband_read_data_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
/*
* CTRL_NVSWITCH_GET_BOARD_PART_NUMBER
*/
NvlStatus
nvswitch_ctrl_get_board_part_number_lr10
(
nvswitch_device *device,
NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p
)
{
struct inforom *pInforom = device->pInforom;
INFOROM_OBD_OBJECT_V1_XX *pOBDObj;
int byteIdx;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (!pInforom->OBD.bValid)
{
NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n");
return -NVL_ERR_GENERIC;
}
pOBDObj = &pInforom->OBD.object.v1;
if (sizeof(p->data) != sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008))
{
NVSWITCH_PRINT(device, ERROR,
"board part number available size %lu is not same as the request size %lu\n",
sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008), sizeof(p->data));
return -NVL_ERR_GENERIC;
}
nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR));
/* Copy board type data */
for (byteIdx = 0; byteIdx < NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES; byteIdx++)
{
p->data[byteIdx] =(NvU8)(pOBDObj->productPartNumber[byteIdx] & 0xFF);
}
return NVL_SUCCESS;
}
/*
* @brief: This function retrieves the NVLIPT public ID for a given global link idx
* @params[in] device reference to current nvswitch device
@@ -7765,6 +7827,26 @@ nvswitch_ctrl_clear_counters_lr10
return status;
}
NvlStatus
nvswitch_ctrl_set_nvlink_error_threshold_lr10
(
nvswitch_device *device,
NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *ret
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
static NvlStatus
nvswitch_ctrl_get_nvlink_error_threshold_lr10
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *ret
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
//
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
// macro in haldef_nvswitch.h

11
src/common/nvswitch/kernel/lr10/soe_lr10.c
View File

@@ -872,6 +872,17 @@ nvswitch_init_soe_lr10
return status;
}
void
nvswitch_soe_init_l2_state_lr10
(
nvswitch_device *device
)
{
NVSWITCH_PRINT(device, WARN,
"%s: Function not implemented on lr10\n",
__FUNCTION__);
}
/**
* @brief SOE construct
*

49
src/common/nvswitch/kernel/ls10/discovery_ls10.c
View File

@@ -1316,6 +1316,30 @@ nvswitch_process_discovery_ls10
NVSWITCH_ENG_VALID_LS10(device, NVLIPT, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT));
}
//
// Process common engine information
//
// Mark all entries as invalid
for (i = 0; i < NVSWITCH_ENGINE_ID_SIZE; i++)
{
chip_device->io.common[i].eng_name = "";
chip_device->io.common[i].eng_id = NVSWITCH_ENGINE_ID_SIZE; // Out of range
chip_device->io.common[i].eng_count = 0;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE; j++)
{
chip_device->io.common[i].uc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].bc_addr = NVSWITCH_BASE_ADDR_INVALID;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE; j++)
{
chip_device->io.common[i].mc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].mc_addr_count = 0;
}
NVSWITCH_LIST_LS10_ENGINES(NVSWITCH_PROCESS_COMMON)
//
// Disable engines requested by regkey "LinkEnableMask".
// All the links are enabled by default.
@@ -1330,6 +1354,7 @@ nvswitch_process_discovery_ls10
NVSWITCH_PRINT(device, SETUP,
"%s: Disable link #%d\n",
__FUNCTION__, i);
nvswitch_link_disable_interrupts_ls10(device, i);
device->link[i].valid = NV_FALSE;
chip_device->engNPORT[i].valid = NV_FALSE;
chip_device->engNPORT_PERFMON[i].valid = NV_FALSE;
@@ -1362,30 +1387,6 @@ nvswitch_process_discovery_ls10
}
}
//
// Process common engine information
//
// Mark all entries as invalid
for (i = 0; i < NVSWITCH_ENGINE_ID_SIZE; i++)
{
chip_device->io.common[i].eng_name = "";
chip_device->io.common[i].eng_id = NVSWITCH_ENGINE_ID_SIZE; // Out of range
chip_device->io.common[i].eng_count = 0;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE; j++)
{
chip_device->io.common[i].uc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].bc_addr = NVSWITCH_BASE_ADDR_INVALID;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE; j++)
{
chip_device->io.common[i].mc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].mc_addr_count = 0;
}
NVSWITCH_LIST_LS10_ENGINES(NVSWITCH_PROCESS_COMMON)
return retval;
}

72
src/common/nvswitch/kernel/ls10/flcn_ls10.c
View File

@@ -277,8 +277,8 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
PFLCN pFlcn
)
{
NvU32 ctl, ridx, widx, count, bufferSize;
NvBool full;
NvU32 ctl, ridx, widx, bufferSize;
NvBool bWasFull;
// Only supported on riscv
if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn))
@@ -290,23 +290,22 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
return;
}
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL,
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MMODE_ENABLE, _TRUE) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _INTR_ENABLE, _FALSE) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _HIGH_THSHD, _INIT));
ctl = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL);
if (ctl == 0)
{
NVSWITCH_PRINT(device, ERROR, "Trace buffer is disabled.\n");
return;
}
full = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl);
if (full)
bWasFull = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl);
if (bWasFull)
{
NVSWITCH_PRINT(device, INFO, "%s: Trace buffer full. Entries may have been lost.\n", __FUNCTION__);
}
// Reset and disable buffer, we don't need it during dump
// Reset and disable buffer, we don't need it during dump (and if core is running)
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, 0);
widx = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_WTIDX);
@@ -316,35 +315,48 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
bufferSize = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _MAXIDX, ridx);
ridx = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx);
count = widx > ridx ? widx - ridx : bufferSize + widx - ridx;
//
// Trace buffer is full when write idx == read idx and full is set,
// otherwise it is empty.
//
if (widx == ridx && !full)
count = 0;
if (count)
if (bufferSize > 0)
{
NvU32 entry;
NVSWITCH_PRINT(device, INFO, "%s: Tracebuffer has %d entries. Starting with latest.\n", __FUNCTION__, count);
switch (DRF_VAL(_PRISCV_RISCV, _TRACECTL, _MODE, ctl))
{
case NV_PRISCV_RISCV_TRACECTL_MODE_FULL:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in full mode.\n");
break;
case NV_PRISCV_RISCV_TRACECTL_MODE_REDUCED:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in reduced mode.\n");
break;
case NV_PRISCV_RISCV_TRACECTL_MODE_STACK:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in stack mode.\n");
break;
default:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in unknown mode.\n");
}
NVSWITCH_PRINT(device, ERROR, "Entries (most recent first):\n");
ridx = widx;
for (entry = 0; entry < count; ++entry)
for (entry = 0; entry < bufferSize; entry++)
{
NvU64 pc;
ridx = ridx > 0 ? ridx - 1 : bufferSize - 1;
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx));
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX,
DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx));
pc = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_HI);
pc = (pc << 32) | flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_LO);
NVSWITCH_PRINT(device, INFO, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc);
// Non-mod2 values are invalid here, so stop (this likely indicates an init-marker val)
if (NvU64_LO32(pc) % 2U != 0U)
{
break;
}
NVSWITCH_PRINT(device, ERROR, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc);
}
}
else
{
NVSWITCH_PRINT(device, INFO, "%s: Trace buffer is empty.\n", __FUNCTION__);
}
// reset trace buffer
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, 0);

24
src/common/nvswitch/kernel/ls10/inforom_ls10.c
View File

@@ -108,6 +108,25 @@ nvswitch_inforom_ecc_get_total_errors_ls10
return;
}
NvlStatus
nvswitch_inforom_load_obd_ls10
(
nvswitch_device *device
)
{
struct inforom *pInforom = device->pInforom;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
return nvswitch_inforom_load_object(device, pInforom, "OBD",
INFOROM_OBD_OBJECT_V2_XX_FMT,
pInforom->OBD.packedObject.v2,
&pInforom->OBD.object.v2);
}
NvlStatus
nvswitch_bbx_add_sxid_ls10
(
@@ -178,7 +197,7 @@ nvswitch_bbx_unload_ls10
NVSWITCH_TIMEOUT timeout;
pFlcn = device->pSoe->pFlcn;
nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
@@ -217,7 +236,7 @@ nvswitch_bbx_load_ls10
NVSWITCH_TIMEOUT timeout;
pFlcn = device->pSoe->pFlcn;
nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
@@ -254,4 +273,3 @@ nvswitch_bbx_get_sxid_ls10
{
return -NVL_ERR_NOT_SUPPORTED;
}

25
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -455,6 +455,8 @@ _nvswitch_initialize_nport_interrupts_ls10
nvswitch_device *device
)
{
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NvU32 val;
val =
@@ -462,6 +464,7 @@ _nvswitch_initialize_nport_interrupts_ls10
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 1) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 1);
NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _ERR_CONTROL_COMMON_NPORT, val);
#endif // 0
_nvswitch_initialize_route_interrupts(device);
_nvswitch_initialize_ingress_interrupts(device);
@@ -494,7 +497,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10
DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, 1) |
DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, 1);
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILE, _ERR_FATAL_INTR_EN, report_fatal);
#endif // 0
chip_device->intr_mask.tile.fatal = report_fatal;
chip_device->intr_mask.tile.nonfatal = 0;
@@ -509,7 +515,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10
DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1) |
DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, 1);
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, report_fatal);
#endif // 0
chip_device->intr_mask.tileout.fatal = report_fatal;
chip_device->intr_mask.tileout.nonfatal = 0;
@@ -5341,6 +5350,10 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10
bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1);
if (nvswitch_test_flags(pending, bit))
{
// Disable further interrupts
nvlink_link *nvlink = nvswitch_get_link(device, link);
nvlink->errorThreshold.bInterruptTrigerred = NV_TRUE;
nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE);
NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate");
}
}
@@ -6295,18 +6308,24 @@ _nvswitch_service_nvlipt_link_nonfatal_ls10
NvU32 interruptingLinks = 0;
NvU32 lnkStatusChangeLinks = 0;
NvlStatus status;
NvU64 link_enable_mask;
link_enable_mask = ((NvU64)device->regkeys.link_enable_mask2 << 32 |
(NvU64)device->regkeys.link_enable_mask);
for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i)
{
globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i;
if ((NVBIT64(globalLink) & link_enable_mask) == 0)
{
continue;
}
intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
if(intrLink)
{
interruptingLinks |= NVBIT(i);
}
intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS);
if(intrLink)

179
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@@ -1070,17 +1070,16 @@ nvswitch_store_topology_information_ls10
}
void
nvswitch_init_dlpl_interrupts_ls10
nvswitch_set_error_rate_threshold_ls10
(
nvlink_link *link
nvlink_link *link,
NvBool bSetDefault
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 intrRegVal;
NvU32 crcRegVal;
NvU32 shortRateMask;
NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short;
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short;
NvU32 crcRegVal;
ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) ==
DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN));
@@ -1099,6 +1098,124 @@ nvswitch_init_dlpl_interrupts_ls10
ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP) ==
DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP));
crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL);
//
// Case 1: When a Regkey is provided. We use it to calculate crcRegVal.
//
// Case 2: When the bSetDefault variable is set to NV_FALSE. This can happen
// when any client/application like NSCQ would provide specific values for
// the error threshold. In this case we use those values to calculate crcRegVal.
//
// Case 3: In all other cases, we want the default values to be used, which are
// provided in Bug 3365481.
//
if(crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT)
{
NvU32 shortRateMask;
shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
crcRegVal &= ~shortRateMask;
crcRegVal |= crcShortRegkeyVal;
link->errorThreshold.bUserConfig = NV_FALSE;
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
}
else if (!bSetDefault)
{
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN,
link->errorThreshold.thresholdMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP,
link->errorThreshold.thresholdExp,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN,
link->errorThreshold.timescaleMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP,
link->errorThreshold.timescaleExp,
crcRegVal);
}
else
{
//
// Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT
// default values used below.
//
link->errorThreshold.thresholdMan =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT;
link->errorThreshold.thresholdExp =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT;
link->errorThreshold.timescaleMan =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT;
link->errorThreshold.timescaleExp =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT;
link->errorThreshold.bUserConfig = NV_FALSE;
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN,
link->errorThreshold.thresholdMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP,
link->errorThreshold.thresholdExp,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN,
link->errorThreshold.timescaleMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP,
link->errorThreshold.timescaleExp,
crcRegVal);
}
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal);
}
void
nvswitch_configure_error_rate_threshold_interrupt_ls10
(
nvlink_link *link,
NvBool bEnable
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 intrRegVal;
link->errorThreshold.bInterruptEn = bEnable;
intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN);
if (bEnable)
{
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 1,
intrRegVal);
}
else
{
intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0,
intrRegVal);
}
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal);
}
void
nvswitch_init_dlpl_interrupts_ls10
(
nvlink_link *link
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
// W1C any stale state.
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR, 0xffffffff);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_SW2, 0xffffffff);
@@ -1136,44 +1253,8 @@ nvswitch_init_dlpl_interrupts_ls10
DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_PROTOCOL, _DISABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _MINION_REQUEST, _DISABLE));
intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN);
crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL);
//
// Enable RX error rate short interrupt.
// Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT
// values used below.
//
// Enable RX error rate short interrupt if the regkey is set
if (crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT)
{
shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE);
crcRegVal &= ~shortRateMask;
crcRegVal |= crcShortRegkeyVal;
}
else
{
shortRateMask = DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE);
crcRegVal &= ~shortRateMask;
}
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal);
nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE);
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE);
}
static NvU32
@@ -1318,12 +1399,12 @@ nvswitch_execute_unilateral_link_shutdown_ls10
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvlStatus status = NVL_SUCCESS;
NvlStatus status = NVL_SUCCESS;
NvU32 retry_count = 3;
NvU32 link_state_request;
NvU32 link_state;
NvU32 stat_data;
NvU32 link_intr_subcode;
NvU32 stat_data = 0;
NvU32 link_intr_subcode = 0;
if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber))
{

183
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -65,7 +65,7 @@
#include "ls10/minion_nvlink_defines_public_ls10.h"
#define NVSWITCH_IFR_MIN_BIOS_VER_LS10 0x9610170000ull
#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610170000ull
#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610220000ull
void *
nvswitch_alloc_chipdevice_ls10
@@ -1091,8 +1091,8 @@ _nvswitch_portstat_reset_latency_counters_ls10
/*
* Disable interrupts comming from NPG & NVLW blocks.
*/
static void
_nvswitch_link_disable_interrupts_ls10
void
nvswitch_link_disable_interrupts_ls10
(
nvswitch_device *device,
NvU32 link
@@ -1434,7 +1434,7 @@ nvswitch_reset_and_drain_links_ls10
//
// Step 2.0 : Disable NPG & NVLW interrupts
//
_nvswitch_link_disable_interrupts_ls10(device, link);
nvswitch_link_disable_interrupts_ls10(device, link);
//
// Step 3.0 :
@@ -1575,6 +1575,7 @@ nvswitch_set_nport_port_config_ls10
)
{
NvU32 val;
NvlStatus status = NVL_SUCCESS;
if (p->requesterLinkID >= NVBIT(
DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID) +
@@ -1624,7 +1625,7 @@ nvswitch_set_nport_port_config_ls10
if (p->type == CONNECT_TRUNK_SWITCH)
{
if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device))
if (!nvswitch_is_soe_supported(device))
{
// Set trunk specific settings (TPROD) on PRE-SILION
@@ -1773,7 +1774,13 @@ nvswitch_set_nport_port_config_ls10
else
{
// Set trunk specific settings (TPROD) in SOE
// nvswitch_set_nport_tprod_state_ls10(device, p->portNum);
status = nvswitch_set_nport_tprod_state_ls10(device, p->portNum);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to set NPORT TPROD state\n",
__FUNCTION__);
}
}
}
else
@@ -1784,7 +1791,7 @@ nvswitch_set_nport_port_config_ls10
NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE0, NvU64_LO32(p->trunkSrcMask));
NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE1, NvU64_HI32(p->trunkSrcMask));
return NVL_SUCCESS;
return status;
}
/*
@@ -4216,6 +4223,8 @@ _nvswitch_init_nport_ecc_control_ls10
nvswitch_device *device
)
{
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
// Set ingress ECC error limits
NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER,
DRF_NUM(_INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0));
@@ -4274,6 +4283,7 @@ _nvswitch_init_nport_ecc_control_ls10
NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_ECC_CTRL,
DRF_DEF(_SOURCETRACK, _ERR_ECC_CTRL, _CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE, __PROD));
#endif // 0
}
NvlStatus
@@ -4306,6 +4316,8 @@ nvswitch_init_nport_ls10
_nvswitch_init_nport_ecc_control_ls10(device);
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
if (DRF_VAL(_SWITCH_REGKEY, _ATO_CONTROL, _DISABLE, device->regkeys.ato_control) ==
NV_SWITCH_REGKEY_ATO_CONTROL_DISABLE_TRUE)
{
@@ -4329,7 +4341,7 @@ nvswitch_init_nport_ls10
DRF_NUM(_TSTATE, _ATO_TIMER_LIMIT, _LIMIT, timeout));
}
}
#endif // 0
if (DRF_VAL(_SWITCH_REGKEY, _STO_CONTROL, _DISABLE, device->regkeys.sto_control) ==
NV_SWITCH_REGKEY_STO_CONTROL_DISABLE_TRUE)
{
@@ -4366,17 +4378,7 @@ nvswitch_init_nxbar_ls10
nvswitch_device *device
)
{
NvlStatus status = NVL_SUCCESS;
status = nvswitch_apply_prod_nxbar_ls10(device);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: NXBAR PRODs failed\n",
__FUNCTION__);
return status;
}
NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__);
return NVL_SUCCESS;
}
@@ -5314,6 +5316,52 @@ nvswitch_ctrl_inband_read_data_ls10
return nvswitch_inband_read_data(device, p->buffer, p->linkId, &p->dataSize);
}
/*
* CTRL_NVSWITCH_GET_BOARD_PART_NUMBER
*/
NvlStatus
nvswitch_ctrl_get_board_part_number_ls10
(
nvswitch_device *device,
NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p
)
{
struct inforom *pInforom = device->pInforom;
INFOROM_OBD_OBJECT_V2_XX *pOBDObj;
int byteIdx;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (!pInforom->OBD.bValid)
{
NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n");
return -NVL_ERR_GENERIC;
}
pOBDObj = &pInforom->OBD.object.v2;
if (sizeof(p->data) != sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008))
{
NVSWITCH_PRINT(device, ERROR,
"board part number available size %lu is not same as the request size %lu\n",
sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008), sizeof(p->data));
return -NVL_ERR_GENERIC;
}
nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR));
/* Copy board type data */
for (byteIdx = 0; byteIdx < NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES; byteIdx++)
{
p->data[byteIdx] =(NvU8)(pOBDObj->productPartNumber[byteIdx] & 0xFF);
}
return NVL_SUCCESS;
}
NvlStatus
nvswitch_ctrl_get_nvlink_lp_counters_ls10
(
@@ -5466,6 +5514,103 @@ nvswitch_ctrl_clear_counters_ls10
return status;
}
NvlStatus
nvswitch_ctrl_set_nvlink_error_threshold_ls10
(
nvswitch_device *device,
NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams
)
{
nvlink_link *link;
NvU8 i;
FOR_EACH_INDEX_IN_MASK(64, i, pParams->link_mask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
{
continue;
}
if (pParams->errorThreshold[link->linkNumber].flags & NVSWITCH_NVLINK_ERROR_THRESHOLD_RESET)
{
link->errorThreshold.bUserConfig = NV_FALSE;
// Disable the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_FALSE);
// Set to default value
nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE);
// Enable the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE);
}
else
{
link->errorThreshold.thresholdMan =
pParams->errorThreshold[link->linkNumber].thresholdMan;
link->errorThreshold.thresholdExp =
pParams->errorThreshold[link->linkNumber].thresholdExp;
link->errorThreshold.timescaleMan =
pParams->errorThreshold[link->linkNumber].timescaleMan;
link->errorThreshold.timescaleExp =
pParams->errorThreshold[link->linkNumber].timescaleExp;
link->errorThreshold.bInterruptEn =
pParams->errorThreshold[link->linkNumber].bInterruptEn;
link->errorThreshold.bUserConfig = NV_TRUE;
// Disable the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_FALSE);
// Set the Error threshold
nvswitch_set_error_rate_threshold_ls10(link, NV_FALSE);
// Configure the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link,
link->errorThreshold.bInterruptEn);
}
}
FOR_EACH_INDEX_IN_MASK_END;
return NVL_SUCCESS;
}
NvlStatus
nvswitch_ctrl_get_nvlink_error_threshold_ls10
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams
)
{
nvlink_link *link;
NvU8 i;
FOR_EACH_INDEX_IN_MASK(64, i, pParams->link_mask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
{
continue;
}
pParams->errorThreshold[link->linkNumber].thresholdMan =
link->errorThreshold.thresholdMan;
pParams->errorThreshold[link->linkNumber].thresholdExp =
link->errorThreshold.thresholdExp;
pParams->errorThreshold[link->linkNumber].timescaleMan =
link->errorThreshold.timescaleMan;
pParams->errorThreshold[link->linkNumber].timescaleExp =
link->errorThreshold.timescaleExp;
pParams->errorThreshold[link->linkNumber].bInterruptEn =
link->errorThreshold.bInterruptEn;
pParams->errorThreshold[link->linkNumber].bInterruptTrigerred =
link->errorThreshold.bInterruptTrigerred;
}
FOR_EACH_INDEX_IN_MASK_END;
return NVL_SUCCESS;
}
NvlStatus
nvswitch_read_vbios_link_entries_ls10
(

65
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -337,6 +337,13 @@ nvswitch_set_nport_tprod_state_ls10
NVSWITCH_TIMEOUT timeout;
RM_SOE_CORE_CMD_NPORT_TPROD_STATE *nportTprodState;
if (!NVSWITCH_ENG_IS_VALID(device, NPORT, nport))
{
NVSWITCH_PRINT(device, ERROR, "%s: NPORT #%d invalid\n",
__FUNCTION__, nport);
return -NVL_BAD_ARGS;
}
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
@@ -364,6 +371,56 @@ nvswitch_set_nport_tprod_state_ls10
return NVL_SUCCESS;
}
/*
* @Brief : INIT L2 register state in SOE
*
* @param[in] device
* @param[in] nport
*/
void
nvswitch_soe_init_l2_state_ls10
(
nvswitch_device *device
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_CORE_CMD_L2_STATE *pL2State;
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported. skipping!\n",
__FUNCTION__);
return;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
cmd.hdr.size = sizeof(cmd);
pL2State = &cmd.cmd.core.l2State;
pL2State->cmdType = RM_SOE_CORE_CMD_INIT_L2_STATE;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to send INIT_L2_STATE command to SOE, status 0x%x\n",
__FUNCTION__, status);
}
}
/*
* @Brief : Init sequence for SOE FSP RISCV image
*
@@ -424,6 +481,14 @@ nvswitch_init_soe_ls10
return status;
}
//
// Set TRACEPC to stack mode for better ucode trace
// In Vulcan CR firmware, this is set to reduced mode in the SOE's manifest
//
data = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL);
data = FLD_SET_DRF(_PRISCV, _RISCV_TRACECTL, _MODE, _STACK, data);
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, data);
// Sanity the command and message queues as a final check
if (_nvswitch_soe_send_test_cmd(device) != NV_OK)
{

27
src/common/nvswitch/kernel/ls10/sugen_ls10.c
View File

@@ -706,8 +706,8 @@ nvswitch_apply_prod_nxbar_ls10
nvswitch_device *device
)
{
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
// .NXBAR PROD value application
NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _CTRL0,
@@ -724,6 +724,7 @@ nvswitch_apply_prod_nxbar_ls10
DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, __PROD) |
DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, __PROD) |
DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG,
DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _DI_DT_SKEW_VAL, __PROD) |
@@ -742,7 +743,9 @@ nvswitch_apply_prod_nxbar_ls10
NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1,
DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1, _MONITOR_CG_EN, __PROD));
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _CTRL0,
DRF_DEF(_NXBAR_TILE, _CTRL0, _MULTI_VALID_XFN_CTRL, _ENABLE) |
DRF_DEF(_NXBAR_TILE, _CTRL0, _PARTIAL_RAM_WR_CTRL, _ENABLE) |
@@ -760,7 +763,7 @@ nvswitch_apply_prod_nxbar_ls10
DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_PARITY_ERROR, __PROD) |
DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, __PROD) |
DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _PRI_NXBAR_TILE_CG,
DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _DI_DT_SKEW_VAL, __PROD) |
DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _HALT_CG_EN, __PROD) |
@@ -801,7 +804,8 @@ nvswitch_nvs_top_prod_ls10
NvU32 i;
// .NVS_TOP PROD application
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, CLKS_P0, , 0, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG,
DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD));
@@ -813,7 +817,7 @@ nvswitch_nvs_top_prod_ls10
NVSWITCH_ENG_WR32(device, CLKS_P0, , 3, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG,
DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _PRI_CTRL_CG1,
DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_CTRLPRI, __PROD) |
DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_MSIX, __PROD));
@@ -855,16 +859,21 @@ nvswitch_nvs_top_prod_ls10
NVSWITCH_ENG_WR32(device, PTIMER, , 0, _PTIMER, _PRI_TMR_CG1,
DRF_DEF(_PTIMER, _PRI_TMR_CG1, _MONITOR_CG_EN, __PROD) |
DRF_DEF(_PTIMER, _PRI_TMR_CG1, _SLCG, __PROD));
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _CTRL_CLOCK_GATING,
DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_PCIE, __PROD) |
DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_SAW, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _GLBLLATENCYTIMERCTRL,
DRF_DEF(_NVLSAW, _GLBLLATENCYTIMERCTRL, _ENABLE, __PROD));
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _PCIE_PRI_CLOCK_GATING,
DRF_DEF(_NVLSAW, _PCIE_PRI_CLOCK_GATING, _CG1_SLCG, __PROD));
#endif // 0
NVSWITCH_REG_WR32(device, _PSE, _CG1,
DRF_DEF(_PSE, _CG1, _SLCG, __PROD));

55
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -743,6 +743,15 @@ nvswitch_init_soe
return device->hal.nvswitch_init_soe(device);
}
void
nvswitch_soe_init_l2_state
(
nvswitch_device *device
)
{
device->hal.nvswitch_soe_init_l2_state(device);
}
static NvlStatus
_nvswitch_construct_soe
(
@@ -3217,6 +3226,22 @@ _nvswitch_ctrl_inband_pending_data_stats
return NVL_SUCCESS;
}
static NvlStatus
_nvswitch_ctrl_get_board_part_number
(
nvswitch_device *device,
NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p
)
{
if (!nvswitch_is_inforom_supported(device))
{
NVSWITCH_PRINT(device, ERROR, "InfoROM is not supported\n");
return -NVL_ERR_NOT_SUPPORTED;
}
return device->hal.nvswitch_ctrl_get_board_part_number(device, p);
}
static NvlStatus
_nvswitch_ctrl_i2c_smbus_command
(
@@ -4647,6 +4672,26 @@ nvswitch_load_link_disable_settings
device->hal.nvswitch_load_link_disable_settings(device, link);
}
static NvlStatus
_nvswitch_ctrl_set_nvlink_error_threshold
(
nvswitch_device *device,
NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams
)
{
return device->hal.nvswitch_ctrl_set_nvlink_error_threshold(device, pParams);
}
static NvlStatus
_nvswitch_ctrl_get_nvlink_error_threshold
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams
)
{
return device->hal.nvswitch_ctrl_get_nvlink_error_threshold(device, pParams);
}
NvlStatus
nvswitch_lib_ctrl
(
@@ -4952,6 +4997,9 @@ nvswitch_lib_ctrl
_nvswitch_ctrl_inband_pending_data_stats,
NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_BOARD_PART_NUMBER,
_nvswitch_ctrl_get_board_part_number,
NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_SW_INFO,
_nvswitch_ctrl_get_sw_info,
@@ -4973,6 +5021,13 @@ nvswitch_lib_ctrl
_nvswitch_ctrl_clear_counters,
NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD,
_nvswitch_ctrl_set_nvlink_error_threshold,
NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD,
_nvswitch_ctrl_get_nvlink_error_threshold,
NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS);
default:
nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd);