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This commit is contained in:
Andy Ritger
2023-01-05 10:40:27 -08:00
parent 9594cc0169
commit dac2350c7f
180 changed files with 9465 additions and 4853 deletions
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49
src/common/nvswitch/kernel/ls10/discovery_ls10.c
View File

@@ -1316,6 +1316,30 @@ nvswitch_process_discovery_ls10
NVSWITCH_ENG_VALID_LS10(device, NVLIPT, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT));
}
//
// Process common engine information
//
// Mark all entries as invalid
for (i = 0; i < NVSWITCH_ENGINE_ID_SIZE; i++)
{
chip_device->io.common[i].eng_name = "";
chip_device->io.common[i].eng_id = NVSWITCH_ENGINE_ID_SIZE; // Out of range
chip_device->io.common[i].eng_count = 0;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE; j++)
{
chip_device->io.common[i].uc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].bc_addr = NVSWITCH_BASE_ADDR_INVALID;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE; j++)
{
chip_device->io.common[i].mc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].mc_addr_count = 0;
}
NVSWITCH_LIST_LS10_ENGINES(NVSWITCH_PROCESS_COMMON)
//
// Disable engines requested by regkey "LinkEnableMask".
// All the links are enabled by default.
@@ -1330,6 +1354,7 @@ nvswitch_process_discovery_ls10
NVSWITCH_PRINT(device, SETUP,
"%s: Disable link #%d\n",
__FUNCTION__, i);
nvswitch_link_disable_interrupts_ls10(device, i);
device->link[i].valid = NV_FALSE;
chip_device->engNPORT[i].valid = NV_FALSE;
chip_device->engNPORT_PERFMON[i].valid = NV_FALSE;
@@ -1362,30 +1387,6 @@ nvswitch_process_discovery_ls10
}
}
//
// Process common engine information
//
// Mark all entries as invalid
for (i = 0; i < NVSWITCH_ENGINE_ID_SIZE; i++)
{
chip_device->io.common[i].eng_name = "";
chip_device->io.common[i].eng_id = NVSWITCH_ENGINE_ID_SIZE; // Out of range
chip_device->io.common[i].eng_count = 0;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE; j++)
{
chip_device->io.common[i].uc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].bc_addr = NVSWITCH_BASE_ADDR_INVALID;
for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE; j++)
{
chip_device->io.common[i].mc_addr[j] = NVSWITCH_BASE_ADDR_INVALID;
}
chip_device->io.common[i].mc_addr_count = 0;
}
NVSWITCH_LIST_LS10_ENGINES(NVSWITCH_PROCESS_COMMON)
return retval;
}

72
src/common/nvswitch/kernel/ls10/flcn_ls10.c
View File

@@ -277,8 +277,8 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
PFLCN pFlcn
)
{
NvU32 ctl, ridx, widx, count, bufferSize;
NvBool full;
NvU32 ctl, ridx, widx, bufferSize;
NvBool bWasFull;
// Only supported on riscv
if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn))
@@ -290,23 +290,22 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
return;
}
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL,
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MMODE_ENABLE, _TRUE) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _INTR_ENABLE, _FALSE) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _HIGH_THSHD, _INIT));
ctl = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL);
if (ctl == 0)
{
NVSWITCH_PRINT(device, ERROR, "Trace buffer is disabled.\n");
return;
}
full = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl);
if (full)
bWasFull = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl);
if (bWasFull)
{
NVSWITCH_PRINT(device, INFO, "%s: Trace buffer full. Entries may have been lost.\n", __FUNCTION__);
}
// Reset and disable buffer, we don't need it during dump
// Reset and disable buffer, we don't need it during dump (and if core is running)
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, 0);
widx = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_WTIDX);
@@ -316,35 +315,48 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
bufferSize = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _MAXIDX, ridx);
ridx = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx);
count = widx > ridx ? widx - ridx : bufferSize + widx - ridx;
//
// Trace buffer is full when write idx == read idx and full is set,
// otherwise it is empty.
//
if (widx == ridx && !full)
count = 0;
if (count)
if (bufferSize > 0)
{
NvU32 entry;
NVSWITCH_PRINT(device, INFO, "%s: Tracebuffer has %d entries. Starting with latest.\n", __FUNCTION__, count);
switch (DRF_VAL(_PRISCV_RISCV, _TRACECTL, _MODE, ctl))
{
case NV_PRISCV_RISCV_TRACECTL_MODE_FULL:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in full mode.\n");
break;
case NV_PRISCV_RISCV_TRACECTL_MODE_REDUCED:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in reduced mode.\n");
break;
case NV_PRISCV_RISCV_TRACECTL_MODE_STACK:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in stack mode.\n");
break;
default:
NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in unknown mode.\n");
}
NVSWITCH_PRINT(device, ERROR, "Entries (most recent first):\n");
ridx = widx;
for (entry = 0; entry < count; ++entry)
for (entry = 0; entry < bufferSize; entry++)
{
NvU64 pc;
ridx = ridx > 0 ? ridx - 1 : bufferSize - 1;
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx));
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX,
DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx));
pc = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_HI);
pc = (pc << 32) | flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_LO);
NVSWITCH_PRINT(device, INFO, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc);
// Non-mod2 values are invalid here, so stop (this likely indicates an init-marker val)
if (NvU64_LO32(pc) % 2U != 0U)
{
break;
}
NVSWITCH_PRINT(device, ERROR, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc);
}
}
else
{
NVSWITCH_PRINT(device, INFO, "%s: Trace buffer is empty.\n", __FUNCTION__);
}
// reset trace buffer
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, 0);

24
src/common/nvswitch/kernel/ls10/inforom_ls10.c
View File

@@ -108,6 +108,25 @@ nvswitch_inforom_ecc_get_total_errors_ls10
return;
}
NvlStatus
nvswitch_inforom_load_obd_ls10
(
nvswitch_device *device
)
{
struct inforom *pInforom = device->pInforom;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
return nvswitch_inforom_load_object(device, pInforom, "OBD",
INFOROM_OBD_OBJECT_V2_XX_FMT,
pInforom->OBD.packedObject.v2,
&pInforom->OBD.object.v2);
}
NvlStatus
nvswitch_bbx_add_sxid_ls10
(
@@ -178,7 +197,7 @@ nvswitch_bbx_unload_ls10
NVSWITCH_TIMEOUT timeout;
pFlcn = device->pSoe->pFlcn;
nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
@@ -217,7 +236,7 @@ nvswitch_bbx_load_ls10
NVSWITCH_TIMEOUT timeout;
pFlcn = device->pSoe->pFlcn;
nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
@@ -254,4 +273,3 @@ nvswitch_bbx_get_sxid_ls10
{
return -NVL_ERR_NOT_SUPPORTED;
}

25
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -455,6 +455,8 @@ _nvswitch_initialize_nport_interrupts_ls10
nvswitch_device *device
)
{
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NvU32 val;
val =
@@ -462,6 +464,7 @@ _nvswitch_initialize_nport_interrupts_ls10
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 1) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 1);
NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _ERR_CONTROL_COMMON_NPORT, val);
#endif // 0
_nvswitch_initialize_route_interrupts(device);
_nvswitch_initialize_ingress_interrupts(device);
@@ -494,7 +497,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10
DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, 1) |
DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, 1);
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILE, _ERR_FATAL_INTR_EN, report_fatal);
#endif // 0
chip_device->intr_mask.tile.fatal = report_fatal;
chip_device->intr_mask.tile.nonfatal = 0;
@@ -509,7 +515,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10
DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1) |
DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, 1);
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, report_fatal);
#endif // 0
chip_device->intr_mask.tileout.fatal = report_fatal;
chip_device->intr_mask.tileout.nonfatal = 0;
@@ -5341,6 +5350,10 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10
bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1);
if (nvswitch_test_flags(pending, bit))
{
// Disable further interrupts
nvlink_link *nvlink = nvswitch_get_link(device, link);
nvlink->errorThreshold.bInterruptTrigerred = NV_TRUE;
nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE);
NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate");
}
}
@@ -6295,18 +6308,24 @@ _nvswitch_service_nvlipt_link_nonfatal_ls10
NvU32 interruptingLinks = 0;
NvU32 lnkStatusChangeLinks = 0;
NvlStatus status;
NvU64 link_enable_mask;
link_enable_mask = ((NvU64)device->regkeys.link_enable_mask2 << 32 |
(NvU64)device->regkeys.link_enable_mask);
for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i)
{
globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i;
if ((NVBIT64(globalLink) & link_enable_mask) == 0)
{
continue;
}
intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
if(intrLink)
{
interruptingLinks |= NVBIT(i);
}
intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS);
if(intrLink)

179
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@@ -1070,17 +1070,16 @@ nvswitch_store_topology_information_ls10
}
void
nvswitch_init_dlpl_interrupts_ls10
nvswitch_set_error_rate_threshold_ls10
(
nvlink_link *link
nvlink_link *link,
NvBool bSetDefault
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 intrRegVal;
NvU32 crcRegVal;
NvU32 shortRateMask;
NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short;
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short;
NvU32 crcRegVal;
ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) ==
DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN));
@@ -1099,6 +1098,124 @@ nvswitch_init_dlpl_interrupts_ls10
ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP) ==
DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP));
crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL);
//
// Case 1: When a Regkey is provided. We use it to calculate crcRegVal.
//
// Case 2: When the bSetDefault variable is set to NV_FALSE. This can happen
// when any client/application like NSCQ would provide specific values for
// the error threshold. In this case we use those values to calculate crcRegVal.
//
// Case 3: In all other cases, we want the default values to be used, which are
// provided in Bug 3365481.
//
if(crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT)
{
NvU32 shortRateMask;
shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
crcRegVal &= ~shortRateMask;
crcRegVal |= crcShortRegkeyVal;
link->errorThreshold.bUserConfig = NV_FALSE;
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
}
else if (!bSetDefault)
{
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN,
link->errorThreshold.thresholdMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP,
link->errorThreshold.thresholdExp,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN,
link->errorThreshold.timescaleMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP,
link->errorThreshold.timescaleExp,
crcRegVal);
}
else
{
//
// Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT
// default values used below.
//
link->errorThreshold.thresholdMan =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT;
link->errorThreshold.thresholdExp =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT;
link->errorThreshold.timescaleMan =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT;
link->errorThreshold.timescaleExp =
NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT;
link->errorThreshold.bUserConfig = NV_FALSE;
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN,
link->errorThreshold.thresholdMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP,
link->errorThreshold.thresholdExp,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN,
link->errorThreshold.timescaleMan,
crcRegVal);
crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP,
link->errorThreshold.timescaleExp,
crcRegVal);
}
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal);
}
void
nvswitch_configure_error_rate_threshold_interrupt_ls10
(
nvlink_link *link,
NvBool bEnable
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 intrRegVal;
link->errorThreshold.bInterruptEn = bEnable;
intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN);
if (bEnable)
{
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 1,
intrRegVal);
}
else
{
intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0,
intrRegVal);
}
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal);
}
void
nvswitch_init_dlpl_interrupts_ls10
(
nvlink_link *link
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
// W1C any stale state.
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR, 0xffffffff);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_SW2, 0xffffffff);
@@ -1136,44 +1253,8 @@ nvswitch_init_dlpl_interrupts_ls10
DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_PROTOCOL, _DISABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _MINION_REQUEST, _DISABLE));
intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN);
crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL);
//
// Enable RX error rate short interrupt.
// Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT
// values used below.
//
// Enable RX error rate short interrupt if the regkey is set
if (crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT)
{
shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE);
crcRegVal &= ~shortRateMask;
crcRegVal |= crcShortRegkeyVal;
}
else
{
shortRateMask = DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE);
crcRegVal &= ~shortRateMask;
}
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal);
nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE);
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE);
}
static NvU32
@@ -1318,12 +1399,12 @@ nvswitch_execute_unilateral_link_shutdown_ls10
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvlStatus status = NVL_SUCCESS;
NvlStatus status = NVL_SUCCESS;
NvU32 retry_count = 3;
NvU32 link_state_request;
NvU32 link_state;
NvU32 stat_data;
NvU32 link_intr_subcode;
NvU32 stat_data = 0;
NvU32 link_intr_subcode = 0;
if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber))
{

183
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -65,7 +65,7 @@
#include "ls10/minion_nvlink_defines_public_ls10.h"
#define NVSWITCH_IFR_MIN_BIOS_VER_LS10 0x9610170000ull
#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610170000ull
#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610220000ull
void *
nvswitch_alloc_chipdevice_ls10
@@ -1091,8 +1091,8 @@ _nvswitch_portstat_reset_latency_counters_ls10
/*
* Disable interrupts comming from NPG & NVLW blocks.
*/
static void
_nvswitch_link_disable_interrupts_ls10
void
nvswitch_link_disable_interrupts_ls10
(
nvswitch_device *device,
NvU32 link
@@ -1434,7 +1434,7 @@ nvswitch_reset_and_drain_links_ls10
//
// Step 2.0 : Disable NPG & NVLW interrupts
//
_nvswitch_link_disable_interrupts_ls10(device, link);
nvswitch_link_disable_interrupts_ls10(device, link);
//
// Step 3.0 :
@@ -1575,6 +1575,7 @@ nvswitch_set_nport_port_config_ls10
)
{
NvU32 val;
NvlStatus status = NVL_SUCCESS;
if (p->requesterLinkID >= NVBIT(
DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID) +
@@ -1624,7 +1625,7 @@ nvswitch_set_nport_port_config_ls10
if (p->type == CONNECT_TRUNK_SWITCH)
{
if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device))
if (!nvswitch_is_soe_supported(device))
{
// Set trunk specific settings (TPROD) on PRE-SILION
@@ -1773,7 +1774,13 @@ nvswitch_set_nport_port_config_ls10
else
{
// Set trunk specific settings (TPROD) in SOE
// nvswitch_set_nport_tprod_state_ls10(device, p->portNum);
status = nvswitch_set_nport_tprod_state_ls10(device, p->portNum);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to set NPORT TPROD state\n",
__FUNCTION__);
}
}
}
else
@@ -1784,7 +1791,7 @@ nvswitch_set_nport_port_config_ls10
NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE0, NvU64_LO32(p->trunkSrcMask));
NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE1, NvU64_HI32(p->trunkSrcMask));
return NVL_SUCCESS;
return status;
}
/*
@@ -4216,6 +4223,8 @@ _nvswitch_init_nport_ecc_control_ls10
nvswitch_device *device
)
{
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
// Set ingress ECC error limits
NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER,
DRF_NUM(_INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0));
@@ -4274,6 +4283,7 @@ _nvswitch_init_nport_ecc_control_ls10
NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_ECC_CTRL,
DRF_DEF(_SOURCETRACK, _ERR_ECC_CTRL, _CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE, __PROD));
#endif // 0
}
NvlStatus
@@ -4306,6 +4316,8 @@ nvswitch_init_nport_ls10
_nvswitch_init_nport_ecc_control_ls10(device);
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
if (DRF_VAL(_SWITCH_REGKEY, _ATO_CONTROL, _DISABLE, device->regkeys.ato_control) ==
NV_SWITCH_REGKEY_ATO_CONTROL_DISABLE_TRUE)
{
@@ -4329,7 +4341,7 @@ nvswitch_init_nport_ls10
DRF_NUM(_TSTATE, _ATO_TIMER_LIMIT, _LIMIT, timeout));
}
}
#endif // 0
if (DRF_VAL(_SWITCH_REGKEY, _STO_CONTROL, _DISABLE, device->regkeys.sto_control) ==
NV_SWITCH_REGKEY_STO_CONTROL_DISABLE_TRUE)
{
@@ -4366,17 +4378,7 @@ nvswitch_init_nxbar_ls10
nvswitch_device *device
)
{
NvlStatus status = NVL_SUCCESS;
status = nvswitch_apply_prod_nxbar_ls10(device);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: NXBAR PRODs failed\n",
__FUNCTION__);
return status;
}
NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__);
return NVL_SUCCESS;
}
@@ -5314,6 +5316,52 @@ nvswitch_ctrl_inband_read_data_ls10
return nvswitch_inband_read_data(device, p->buffer, p->linkId, &p->dataSize);
}
/*
* CTRL_NVSWITCH_GET_BOARD_PART_NUMBER
*/
NvlStatus
nvswitch_ctrl_get_board_part_number_ls10
(
nvswitch_device *device,
NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p
)
{
struct inforom *pInforom = device->pInforom;
INFOROM_OBD_OBJECT_V2_XX *pOBDObj;
int byteIdx;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (!pInforom->OBD.bValid)
{
NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n");
return -NVL_ERR_GENERIC;
}
pOBDObj = &pInforom->OBD.object.v2;
if (sizeof(p->data) != sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008))
{
NVSWITCH_PRINT(device, ERROR,
"board part number available size %lu is not same as the request size %lu\n",
sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008), sizeof(p->data));
return -NVL_ERR_GENERIC;
}
nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR));
/* Copy board type data */
for (byteIdx = 0; byteIdx < NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES; byteIdx++)
{
p->data[byteIdx] =(NvU8)(pOBDObj->productPartNumber[byteIdx] & 0xFF);
}
return NVL_SUCCESS;
}
NvlStatus
nvswitch_ctrl_get_nvlink_lp_counters_ls10
(
@@ -5466,6 +5514,103 @@ nvswitch_ctrl_clear_counters_ls10
return status;
}
NvlStatus
nvswitch_ctrl_set_nvlink_error_threshold_ls10
(
nvswitch_device *device,
NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams
)
{
nvlink_link *link;
NvU8 i;
FOR_EACH_INDEX_IN_MASK(64, i, pParams->link_mask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
{
continue;
}
if (pParams->errorThreshold[link->linkNumber].flags & NVSWITCH_NVLINK_ERROR_THRESHOLD_RESET)
{
link->errorThreshold.bUserConfig = NV_FALSE;
// Disable the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_FALSE);
// Set to default value
nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE);
// Enable the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE);
}
else
{
link->errorThreshold.thresholdMan =
pParams->errorThreshold[link->linkNumber].thresholdMan;
link->errorThreshold.thresholdExp =
pParams->errorThreshold[link->linkNumber].thresholdExp;
link->errorThreshold.timescaleMan =
pParams->errorThreshold[link->linkNumber].timescaleMan;
link->errorThreshold.timescaleExp =
pParams->errorThreshold[link->linkNumber].timescaleExp;
link->errorThreshold.bInterruptEn =
pParams->errorThreshold[link->linkNumber].bInterruptEn;
link->errorThreshold.bUserConfig = NV_TRUE;
// Disable the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_FALSE);
// Set the Error threshold
nvswitch_set_error_rate_threshold_ls10(link, NV_FALSE);
// Configure the interrupt
nvswitch_configure_error_rate_threshold_interrupt_ls10(link,
link->errorThreshold.bInterruptEn);
}
}
FOR_EACH_INDEX_IN_MASK_END;
return NVL_SUCCESS;
}
NvlStatus
nvswitch_ctrl_get_nvlink_error_threshold_ls10
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams
)
{
nvlink_link *link;
NvU8 i;
FOR_EACH_INDEX_IN_MASK(64, i, pParams->link_mask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
{
continue;
}
pParams->errorThreshold[link->linkNumber].thresholdMan =
link->errorThreshold.thresholdMan;
pParams->errorThreshold[link->linkNumber].thresholdExp =
link->errorThreshold.thresholdExp;
pParams->errorThreshold[link->linkNumber].timescaleMan =
link->errorThreshold.timescaleMan;
pParams->errorThreshold[link->linkNumber].timescaleExp =
link->errorThreshold.timescaleExp;
pParams->errorThreshold[link->linkNumber].bInterruptEn =
link->errorThreshold.bInterruptEn;
pParams->errorThreshold[link->linkNumber].bInterruptTrigerred =
link->errorThreshold.bInterruptTrigerred;
}
FOR_EACH_INDEX_IN_MASK_END;
return NVL_SUCCESS;
}
NvlStatus
nvswitch_read_vbios_link_entries_ls10
(

65
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -337,6 +337,13 @@ nvswitch_set_nport_tprod_state_ls10
NVSWITCH_TIMEOUT timeout;
RM_SOE_CORE_CMD_NPORT_TPROD_STATE *nportTprodState;
if (!NVSWITCH_ENG_IS_VALID(device, NPORT, nport))
{
NVSWITCH_PRINT(device, ERROR, "%s: NPORT #%d invalid\n",
__FUNCTION__, nport);
return -NVL_BAD_ARGS;
}
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
@@ -364,6 +371,56 @@ nvswitch_set_nport_tprod_state_ls10
return NVL_SUCCESS;
}
/*
* @Brief : INIT L2 register state in SOE
*
* @param[in] device
* @param[in] nport
*/
void
nvswitch_soe_init_l2_state_ls10
(
nvswitch_device *device
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_CORE_CMD_L2_STATE *pL2State;
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported. skipping!\n",
__FUNCTION__);
return;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
cmd.hdr.size = sizeof(cmd);
pL2State = &cmd.cmd.core.l2State;
pL2State->cmdType = RM_SOE_CORE_CMD_INIT_L2_STATE;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to send INIT_L2_STATE command to SOE, status 0x%x\n",
__FUNCTION__, status);
}
}
/*
* @Brief : Init sequence for SOE FSP RISCV image
*
@@ -424,6 +481,14 @@ nvswitch_init_soe_ls10
return status;
}
//
// Set TRACEPC to stack mode for better ucode trace
// In Vulcan CR firmware, this is set to reduced mode in the SOE's manifest
//
data = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL);
data = FLD_SET_DRF(_PRISCV, _RISCV_TRACECTL, _MODE, _STACK, data);
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, data);
// Sanity the command and message queues as a final check
if (_nvswitch_soe_send_test_cmd(device) != NV_OK)
{

27
src/common/nvswitch/kernel/ls10/sugen_ls10.c
View File

@@ -706,8 +706,8 @@ nvswitch_apply_prod_nxbar_ls10
nvswitch_device *device
)
{
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
// .NXBAR PROD value application
NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _CTRL0,
@@ -724,6 +724,7 @@ nvswitch_apply_prod_nxbar_ls10
DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, __PROD) |
DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, __PROD) |
DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG,
DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _DI_DT_SKEW_VAL, __PROD) |
@@ -742,7 +743,9 @@ nvswitch_apply_prod_nxbar_ls10
NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1,
DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1, _MONITOR_CG_EN, __PROD));
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _CTRL0,
DRF_DEF(_NXBAR_TILE, _CTRL0, _MULTI_VALID_XFN_CTRL, _ENABLE) |
DRF_DEF(_NXBAR_TILE, _CTRL0, _PARTIAL_RAM_WR_CTRL, _ENABLE) |
@@ -760,7 +763,7 @@ nvswitch_apply_prod_nxbar_ls10
DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_PARITY_ERROR, __PROD) |
DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, __PROD) |
DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _PRI_NXBAR_TILE_CG,
DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _DI_DT_SKEW_VAL, __PROD) |
DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _HALT_CG_EN, __PROD) |
@@ -801,7 +804,8 @@ nvswitch_nvs_top_prod_ls10
NvU32 i;
// .NVS_TOP PROD application
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, CLKS_P0, , 0, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG,
DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD));
@@ -813,7 +817,7 @@ nvswitch_nvs_top_prod_ls10
NVSWITCH_ENG_WR32(device, CLKS_P0, , 3, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG,
DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _PRI_CTRL_CG1,
DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_CTRLPRI, __PROD) |
DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_MSIX, __PROD));
@@ -855,16 +859,21 @@ nvswitch_nvs_top_prod_ls10
NVSWITCH_ENG_WR32(device, PTIMER, , 0, _PTIMER, _PRI_TMR_CG1,
DRF_DEF(_PTIMER, _PRI_TMR_CG1, _MONITOR_CG_EN, __PROD) |
DRF_DEF(_PTIMER, _PRI_TMR_CG1, _SLCG, __PROD));
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _CTRL_CLOCK_GATING,
DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_PCIE, __PROD) |
DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_SAW, __PROD));
#endif // 0
NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _GLBLLATENCYTIMERCTRL,
DRF_DEF(_NVLSAW, _GLBLLATENCYTIMERCTRL, _ENABLE, __PROD));
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _PCIE_PRI_CLOCK_GATING,
DRF_DEF(_NVLSAW, _PCIE_PRI_CLOCK_GATING, _CG1_SLCG, __PROD));
#endif // 0
NVSWITCH_REG_WR32(device, _PSE, _CG1,
DRF_DEF(_PSE, _CG1, _SLCG, __PROD));