mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-04-23 07:49:08 +00:00
525.78.01
This commit is contained in:
Andy Ritger
@@ -1070,17 +1070,16 @@ nvswitch_store_topology_information_ls10
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}
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void
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nvswitch_init_dlpl_interrupts_ls10
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nvswitch_set_error_rate_threshold_ls10
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(
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nvlink_link *link
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nvlink_link *link,
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NvBool bSetDefault
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)
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{
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nvswitch_device *device = link->dev->pDevInfo;
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NvU32 linkNumber = link->linkNumber;
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NvU32 intrRegVal;
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NvU32 crcRegVal;
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NvU32 shortRateMask;
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NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short;
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nvswitch_device *device = link->dev->pDevInfo;
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NvU32 linkNumber = link->linkNumber;
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NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short;
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NvU32 crcRegVal;
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ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) ==
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DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN));
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@@ -1099,6 +1098,124 @@ nvswitch_init_dlpl_interrupts_ls10
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ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP) ==
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DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP));
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crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
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_NVLDL_RX, _ERROR_RATE_CTRL);
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//
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// Case 1: When a Regkey is provided. We use it to calculate crcRegVal.
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//
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// Case 2: When the bSetDefault variable is set to NV_FALSE. This can happen
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// when any client/application like NSCQ would provide specific values for
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// the error threshold. In this case we use those values to calculate crcRegVal.
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//
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// Case 3: In all other cases, we want the default values to be used, which are
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// provided in Bug 3365481.
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//
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if(crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT)
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{
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NvU32 shortRateMask;
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shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
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DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
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DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
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DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
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crcRegVal &= ~shortRateMask;
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crcRegVal |= crcShortRegkeyVal;
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link->errorThreshold.bUserConfig = NV_FALSE;
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link->errorThreshold.bInterruptTrigerred = NV_FALSE;
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}
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else if (!bSetDefault)
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{
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN,
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link->errorThreshold.thresholdMan,
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crcRegVal);
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP,
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link->errorThreshold.thresholdExp,
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crcRegVal);
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN,
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link->errorThreshold.timescaleMan,
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crcRegVal);
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP,
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link->errorThreshold.timescaleExp,
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crcRegVal);
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}
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else
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{
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//
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// Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT
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// default values used below.
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//
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link->errorThreshold.thresholdMan =
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NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT;
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link->errorThreshold.thresholdExp =
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NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT;
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link->errorThreshold.timescaleMan =
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NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT;
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link->errorThreshold.timescaleExp =
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NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT;
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link->errorThreshold.bUserConfig = NV_FALSE;
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link->errorThreshold.bInterruptTrigerred = NV_FALSE;
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN,
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link->errorThreshold.thresholdMan,
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crcRegVal);
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP,
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link->errorThreshold.thresholdExp,
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crcRegVal);
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN,
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link->errorThreshold.timescaleMan,
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crcRegVal);
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crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP,
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link->errorThreshold.timescaleExp,
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crcRegVal);
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}
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
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_NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal);
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}
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void
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nvswitch_configure_error_rate_threshold_interrupt_ls10
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(
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nvlink_link *link,
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NvBool bEnable
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)
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{
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nvswitch_device *device = link->dev->pDevInfo;
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NvU32 linkNumber = link->linkNumber;
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NvU32 intrRegVal;
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link->errorThreshold.bInterruptEn = bEnable;
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intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
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_NVLDL_TOP, _INTR_NONSTALL_EN);
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if (bEnable)
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{
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link->errorThreshold.bInterruptTrigerred = NV_FALSE;
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intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 1,
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intrRegVal);
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}
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else
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{
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intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0,
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intrRegVal);
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}
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
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_NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal);
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}
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void
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nvswitch_init_dlpl_interrupts_ls10
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(
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nvlink_link *link
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)
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{
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nvswitch_device *device = link->dev->pDevInfo;
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NvU32 linkNumber = link->linkNumber;
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// W1C any stale state.
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR, 0xffffffff);
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_SW2, 0xffffffff);
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@@ -1136,44 +1253,8 @@ nvswitch_init_dlpl_interrupts_ls10
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DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_PROTOCOL, _DISABLE) |
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DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _MINION_REQUEST, _DISABLE));
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intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
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_NVLDL_TOP, _INTR_NONSTALL_EN);
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crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
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_NVLDL_RX, _ERROR_RATE_CTRL);
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//
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// Enable RX error rate short interrupt.
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// Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT
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// values used below.
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//
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// Enable RX error rate short interrupt if the regkey is set
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if (crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT)
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{
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shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
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DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
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DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
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DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
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intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE);
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crcRegVal &= ~shortRateMask;
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crcRegVal |= crcShortRegkeyVal;
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}
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else
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{
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shortRateMask = DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) |
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DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) |
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DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) |
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DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP);
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intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE);
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crcRegVal &= ~shortRateMask;
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}
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
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_NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal);
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
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_NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal);
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nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE);
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nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE);
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}
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static NvU32
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@@ -1318,12 +1399,12 @@ nvswitch_execute_unilateral_link_shutdown_ls10
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)
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{
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nvswitch_device *device = link->dev->pDevInfo;
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NvlStatus status = NVL_SUCCESS;
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NvlStatus status = NVL_SUCCESS;
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NvU32 retry_count = 3;
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NvU32 link_state_request;
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NvU32 link_state;
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NvU32 stat_data;
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NvU32 link_intr_subcode;
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NvU32 stat_data = 0;
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NvU32 link_intr_subcode = 0;
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if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber))
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{
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