mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-07 00:29:58 +00:00
525.78.01
This commit is contained in:
@@ -958,7 +958,6 @@ NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *);
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void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd);
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NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id);
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NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *);
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NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked(nvidia_stack_t *, nv_state_t *, NvU32 *);
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NV_STATUS NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *);
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NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *);
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NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *);
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@@ -1221,12 +1221,11 @@ static void postEvent(
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NvBool dataValid
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)
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{
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nv_state_t *nv = nv_get_ctl_state();
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portSyncSpinlockAcquire(nv->event_spinlock);
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if (event->active)
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nv_post_event(event, hEvent, notifyIndex,
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info32, info16, dataValid);
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portSyncSpinlockRelease(nv->event_spinlock);
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if (osReferenceObjectCount(event) != NV_OK)
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return;
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nv_post_event(event, hEvent, notifyIndex,
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info32, info16, dataValid);
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osDereferenceObjectCount(event);
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}
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NvU32 osSetEvent
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@@ -1445,6 +1444,12 @@ NV_STATUS osReferenceObjectCount(void *pEvent)
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nv_event_t *event = pEvent;
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portSyncSpinlockAcquire(nv->event_spinlock);
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// If event->active is false, don't allow any more reference
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if (!event->active)
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{
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portSyncSpinlockRelease(nv->event_spinlock);
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return NV_ERR_INVALID_EVENT;
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}
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++event->refcount;
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portSyncSpinlockRelease(nv->event_spinlock);
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return NV_OK;
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@@ -1457,11 +1462,10 @@ NV_STATUS osDereferenceObjectCount(void *pOSEvent)
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portSyncSpinlockAcquire(nv->event_spinlock);
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NV_ASSERT(event->refcount > 0);
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--event->refcount;
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// If event->refcount == 0 but event->active is true, the client
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// has not yet freed the OS event. free_os_event will free its
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// memory when they do, or else when the client itself is freed.
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if (event->refcount == 0 && !event->active)
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if (--event->refcount == 0 && !event->active)
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portMemFree(event);
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portSyncSpinlockRelease(nv->event_spinlock);
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@@ -354,9 +354,7 @@ static void free_os_event_under_lock(nv_event_t *event)
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// If refcount > 0, event will be freed by osDereferenceObjectCount
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// when the last associated RM event is freed.
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if (event->refcount == 0)
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{
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portMemFree(event);
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}
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}
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static void free_os_events(
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@@ -2910,23 +2908,21 @@ static NV_STATUS RmRunNanoTimerCallback(
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void *pTmrEvent
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)
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{
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OBJSYS *pSys = SYS_GET_INSTANCE();
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POBJTMR pTmr = GPU_GET_TIMER(pGpu);
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THREAD_STATE_NODE threadState;
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NV_STATUS status = NV_OK;
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// LOCK: try to acquire GPUs lock
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if ((status = rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR)) != NV_OK)
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{
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PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT) pTmrEvent;
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// We failed to acquire the lock; schedule a timer to try again.
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return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, 1000);
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}
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TMR_EVENT *pEvent = (TMR_EVENT *)pTmrEvent;
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if ((status = osCondAcquireRmSema(pSys->pSema)) != NV_OK)
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{
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// UNLOCK: release GPUs lock
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rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
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return status;
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//
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// We failed to acquire the lock - depending on what's holding it,
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// the lock could be held for a while, so try again soon, but not too
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// soon to prevent the owner from making forward progress indefinitely.
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//
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return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->pOSTmrCBdata,
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osGetTickResolution());
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}
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threadStateInitISRAndDeferredIntHandler(&threadState, pGpu,
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@@ -2939,7 +2935,6 @@ static NV_STATUS RmRunNanoTimerCallback(
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threadStateFreeISRAndDeferredIntHandler(&threadState,
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pGpu, THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER);
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osReleaseRmSema(pSys->pSema, NULL);
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// UNLOCK: release GPUs lock
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rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, pGpu);
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@@ -608,36 +608,19 @@ done:
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// Use this call when MMU faults needs to be copied
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// outisde of RM lock.
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//
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NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked(
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nvidia_stack_t *sp,
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nv_state_t *nv,
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NvU32 *faultsCopied
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static NV_STATUS _rm_gpu_copy_mmu_faults_unlocked(
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OBJGPU *pGpu,
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NvU32 *pFaultsCopied,
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THREAD_STATE_NODE *pThreadState
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)
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{
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OBJGPU *pGpu;
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void *fp;
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NV_STATUS status = NV_OK;
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NV_ENTER_RM_RUNTIME(sp,fp);
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pGpu = NV_GET_NV_PRIV_PGPU(nv);
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if (pGpu == NULL || faultsCopied == NULL)
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{
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status = NV_ERR_OBJECT_NOT_FOUND;
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goto done;
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}
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// Non-replayable faults are copied to the client shadow buffer by GSP-RM.
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if (IS_GSP_CLIENT(pGpu))
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{
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status = NV_ERR_NOT_SUPPORTED;
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goto done;
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return NV_ERR_NOT_SUPPORTED;
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}
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done:
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NV_EXIT_RM_RUNTIME(sp,fp);
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return status;
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return NV_OK;
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}
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//
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@@ -650,10 +633,12 @@ NV_STATUS rm_gpu_handle_mmu_faults(
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)
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{
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NvU32 status = NV_OK;
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OBJGPU *pGpu;
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void *fp;
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NV_ENTER_RM_RUNTIME(sp,fp);
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*faultsCopied = 0;
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OBJGPU *pGpu;
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pGpu = NV_GET_NV_PRIV_PGPU(nv);
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if (pGpu == NULL)
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@@ -661,40 +646,50 @@ NV_STATUS rm_gpu_handle_mmu_faults(
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return NV_ERR_OBJECT_NOT_FOUND;
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}
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if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu))
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{
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KernelGmmu *pKernelGmmu;
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PORT_MEM_ALLOCATOR *pIsrAllocator;
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THREAD_STATE_NODE threadState;
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NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer
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KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu);
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Intr *pIntr = GPU_GET_INTR(pGpu);
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NvU32 hw_put = 0;
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NvU32 hw_get = 0;
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pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator));
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tlsIsrInit(pIsrAllocator);
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threadStateInitISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS);
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kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER,
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&hw_put, &threadState);
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pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu);
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kgmmuReadFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER,
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&hw_get, &threadState);
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if(hw_get != hw_put)
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if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu))
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{
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// We have to clear the top level interrupt bit here since otherwise
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// the bottom half will attempt to service the interrupt on the CPU
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// side before GSP recieves the notification and services it
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kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, &threadState);
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status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE);
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Intr *pIntr = GPU_GET_INTR(pGpu);
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if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, &threadState))
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{
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// We have to clear the top level interrupt bit here since otherwise
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// the bottom half will attempt to service the interrupt on the CPU
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// side before GSP recieves the notification and services it
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kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, &threadState);
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status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE);
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}
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}
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else if (IS_VIRTUAL_WITH_SRIOV(pGpu))
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{
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if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, &threadState))
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{
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status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState);
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}
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}
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else
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{
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status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState);
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}
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threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS);
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tlsIsrDestroy(pIsrAllocator);
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portMemAllocatorRelease(pIsrAllocator);
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}
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else
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{
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status = rm_gpu_copy_mmu_faults_unlocked(sp, nv, faultsCopied);
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}
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NV_EXIT_RM_RUNTIME(sp,fp);
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return status;
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}
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