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This commit is contained in:
Andy Ritger
2023-01-05 10:40:27 -08:00
parent 9594cc0169
commit dac2350c7f
180 changed files with 9465 additions and 4853 deletions
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4
src/nvidia/generated/g_bindata.c
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@@ -69,6 +69,7 @@ struct BINDATA_STORAGE_PVT_ALL
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c"
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c"
#include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c"
#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c"
#undef BINDATA_INCLUDE_STORAGE_PVT_DECL
#undef BINDATA_NO_SEGMENTS
@@ -97,6 +98,7 @@ struct BINDATA_STORAGE_PVT_ALL
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c"
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c"
#include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c"
#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c"
#undef BINDATA_INCLUDE_DATA
@@ -123,6 +125,7 @@ BINDATA_CONST struct BINDATA_STORAGE_PVT_ALL g_bindata_pvt =
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c"
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c"
#include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c"
#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c"
#undef BINDATA_INCLUDE_STORAGE_PVT_DEFN
#undef BINDATA_NO_SEGMENTS
@@ -152,6 +155,7 @@ const NvU32 g_bindata_pvt_count = sizeof(g_bindata_pvt) / sizeof(BINDATA_STORAGE
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c"
#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c"
#include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c"
#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c"
#undef BINDATA_INCLUDE_FUNCTION
#undef BINDATA_INCLUDE_ARCHIVE

7406
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c
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1281
src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c Normal file
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5
src/nvidia/generated/g_event_nvoc.h
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@@ -538,6 +538,11 @@ NV_STATUS engineNonStallIntrNotify(OBJGPU *, RM_ENGINE_TYPE);
NV_STATUS notifyEvents(OBJGPU*, EVENTNOTIFICATION*, NvU32, NvU32, NvU32, NV_STATUS, NvU32);
NV_STATUS engineNonStallIntrNotifyEvent(OBJGPU *, RM_ENGINE_TYPE, NvHandle);
typedef struct GpuEngineEventNotificationList GpuEngineEventNotificationList;
NV_STATUS gpuEngineEventNotificationListCreate(OBJGPU *, GpuEngineEventNotificationList **);
void gpuEngineEventNotificationListDestroy(OBJGPU *, GpuEngineEventNotificationList *);
#endif // _EVENT_H_
#ifdef __cplusplus

12
src/nvidia/generated/g_gpu_nvoc.c
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@@ -126,7 +126,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
}
// NVOC Property Hal field -- PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 == 0)));
}
@@ -199,7 +199,15 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
}
// NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE
pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0)));
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0)));
}
// default
else
{
pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0)));
}
// NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */

17
src/nvidia/generated/g_gpu_nvoc.h
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@@ -609,21 +609,6 @@ typedef struct // GPU specific data for core logic object, stored in GPU object
#define GPU_STATE_DEFAULT 0 // Default flags for destructive state loads
// and unloads
typedef struct engine_event_node
{
PEVENTNOTIFICATION pEventNotify;
struct Memory *pMemory;
struct engine_event_node *pNext;
} ENGINE_EVENT_NODE;
// Linked list of per engine non-stall event nodes
typedef struct
{
ENGINE_EVENT_NODE *pEventNode;
// lock to protect above list
PORT_SPINLOCK *pSpinlock;
} ENGINE_EVENT_LIST;
struct OBJHWBC;
typedef struct hwbc_list
{
@@ -936,7 +921,7 @@ struct OBJGPU {
OS_RM_CAPS *pOsRmCaps;
NvU32 halImpl;
void *hPci;
ENGINE_EVENT_LIST engineNonstallIntr[62];
GpuEngineEventNotificationList *engineNonstallIntrEventNotifications[62];
NvBool bIsSOC;
NvU32 gpuInstance;
NvU32 gpuDisabled;

8
src/nvidia/generated/g_kern_gmmu_nvoc.h
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@@ -874,19 +874,19 @@ static inline void kgmmuWriteMmuFaultStatus(OBJGPU *pGpu, struct KernelGmmu *pKe
#define kgmmuWriteMmuFaultStatus_HAL(pGpu, pKernelGmmu, arg0) kgmmuWriteMmuFaultStatus(pGpu, pKernelGmmu, arg0)
NvBool kgmmuIsNonReplayableFaultPending_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu);
NvBool kgmmuIsNonReplayableFaultPending_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0);
#ifdef __nvoc_kern_gmmu_h_disabled
static inline NvBool kgmmuIsNonReplayableFaultPending(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) {
static inline NvBool kgmmuIsNonReplayableFaultPending(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0) {
NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!");
return NV_FALSE;
}
#else //__nvoc_kern_gmmu_h_disabled
#define kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu) kgmmuIsNonReplayableFaultPending_TU102(pGpu, pKernelGmmu)
#define kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu, arg0) kgmmuIsNonReplayableFaultPending_TU102(pGpu, pKernelGmmu, arg0)
#endif //__nvoc_kern_gmmu_h_disabled
#define kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu) kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu)
#define kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, arg0) kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu, arg0)
NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu);

10
src/nvidia/generated/g_kernel_ce_nvoc.h
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@@ -673,6 +673,16 @@ NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size);
NV_STATUS kceGetAvailableHubPceMask_IMPL(OBJGPU *pGpu, NVLINK_TOPOLOGY_PARAMS *pTopoParams);
#define kceGetAvailableHubPceMask(pGpu, pTopoParams) kceGetAvailableHubPceMask_IMPL(pGpu, pTopoParams)
void kceGetNvlinkCaps_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NvU8 *pKCeCaps);
#ifdef __nvoc_kernel_ce_h_disabled
static inline void kceGetNvlinkCaps(OBJGPU *pGpu, struct KernelCE *pKCe, NvU8 *pKCeCaps) {
NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!");
}
#else //__nvoc_kernel_ce_h_disabled
#define kceGetNvlinkCaps(pGpu, pKCe, pKCeCaps) kceGetNvlinkCaps_IMPL(pGpu, pKCe, pKCeCaps)
#endif //__nvoc_kernel_ce_h_disabled
NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *gpu, struct KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, NvU8 *ceCaps);
#ifdef __nvoc_kernel_ce_h_disabled

16
src/nvidia/generated/g_kernel_channel_nvoc.c
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@@ -740,12 +740,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh
#endif
},
{ /* [34] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) kchannelCtrlCmdSetChannelHwState_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
/*flags=*/ 0x102204u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
/*flags=*/ 0x142204u,
/*accessRight=*/0x0u,
/*methodId=*/ 0xb06f0110u,
/*paramSize=*/ sizeof(NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS),
@@ -770,12 +770,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh
#endif
},
{ /* [36] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) kchannelCtrlCmdRestoreEngineCtxData_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
/*flags=*/ 0x102204u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
/*flags=*/ 0x142204u,
/*accessRight=*/0x0u,
/*methodId=*/ 0xb06f0112u,
/*paramSize=*/ sizeof(NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS),
@@ -1166,7 +1166,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe
pThis->__kchannelCtrlCmdGetChannelHwState__ = &kchannelCtrlCmdGetChannelHwState_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
pThis->__kchannelCtrlCmdSetChannelHwState__ = &kchannelCtrlCmdSetChannelHwState_IMPL;
#endif
@@ -1174,7 +1174,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe
pThis->__kchannelCtrlCmdSaveEngineCtxData__ = &kchannelCtrlCmdSaveEngineCtxData_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
pThis->__kchannelCtrlCmdRestoreEngineCtxData__ = &kchannelCtrlCmdRestoreEngineCtxData_IMPL;
#endif

2
src/nvidia/generated/g_kernel_fifo_nvoc.h
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@@ -268,6 +268,7 @@ struct channel_iterator
NvU32 numRunlists;
NvU32 physicalChannelID;
NvU32 runlistId;
EMEMBLOCK *pFifoDataBlock;
CHANNEL_NODE channelNode;
};
@@ -455,6 +456,7 @@ struct KernelFifo {
FifoSchedulingHandlerEntryList preSchedulingDisableHandlerList;
NvBool bUseChidHeap;
NvBool bUsePerRunlistChram;
NvBool bDisableChidIsolation;
NvBool bIsPerRunlistChramSupportedInHw;
NvBool bHostEngineExpansion;
NvBool bHostHasLbOverflow;

62
src/nvidia/generated/g_kernel_gsp_nvoc.c
View File

@@ -497,6 +497,19 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner *
}
}
// Hal function -- kgspGetPrescrubbedTopFbSize
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */
{
pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_dd2c0b;
}
}
// Hal function -- kgspExtractVbiosFromRom
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
@@ -536,6 +549,19 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner *
}
}
// Hal function -- kgspExecuteScrubberIfNeeded
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */
{
pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9;
}
}
// Hal function -- kgspExecuteBooterLoad
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
@@ -653,13 +679,43 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner *
// Hal function -- kgspGetWprHeapSize
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */
{
pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_e77d51;
pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_5661b8;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */
{
pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_15390a;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_38f3bc;
pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_AD102;
}
}
// Hal function -- kgspInitVgpuPartitionLogging
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */
{
pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL;
}
}
// Hal function -- kgspFreeVgpuPartitionLogging
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */
{
pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL;
}
}

83
src/nvidia/generated/g_kernel_gsp_nvoc.h
View File

@@ -49,6 +49,7 @@ extern "C" {
#include "gpu/gsp/gsp_static_config.h"
#include "gpu/gsp/gsp_init_args.h"
#include "nv-firmware.h"
#include "nv_sriov_defines.h"
#include "rmRiscvUcode.h"
#include "libos_init_args.h"
@@ -213,7 +214,7 @@ typedef struct GSP_FIRMWARE
enum
{
LOGIDX_INIT,
LOGIDX_VGPU,
LOGIDX_INTR,
LOGIDX_RM,
LOGIDX_SIZE
};
@@ -267,9 +268,11 @@ struct KernelGsp {
NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp *);
NvBool (*__kgspIsEngineInReset__)(struct OBJGPU *, struct KernelGsp *);
NvU32 (*__kgspGetFrtsSize__)(struct OBJGPU *, struct KernelGsp *);
NvU64 (*__kgspGetPrescrubbedTopFbSize__)(struct OBJGPU *, struct KernelGsp *);
NV_STATUS (*__kgspExtractVbiosFromRom__)(struct OBJGPU *, struct KernelGsp *, KernelGspVbiosImg **);
NV_STATUS (*__kgspExecuteFwsecFrts__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, const NvU64);
NV_STATUS (*__kgspExecuteFwsecSb__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *);
NV_STATUS (*__kgspExecuteScrubberIfNeeded__)(struct OBJGPU *, struct KernelGsp *);
NV_STATUS (*__kgspExecuteBooterLoad__)(struct OBJGPU *, struct KernelGsp *, const NvU64);
NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *);
NV_STATUS (*__kgspExecuteHsFalcon__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, struct KernelFalcon *, NvU32 *, NvU32 *);
@@ -277,6 +280,8 @@ struct KernelGsp {
const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *);
const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *);
NvU64 (*__kgspGetWprHeapSize__)(struct OBJGPU *, struct KernelGsp *);
NV_STATUS (*__kgspInitVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU64, NvU64, NvU64, NvU64);
NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32);
const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *);
NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *);
void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *);
@@ -302,6 +307,7 @@ struct KernelGsp {
NV_STATUS (*__kgspSetTunableState__)(POBJGPU, struct KernelGsp *, void *);
struct OBJRPC *pRpc;
KernelGspFlcnUcode *pFwsecUcode;
KernelGspFlcnUcode *pScrubberUcode;
KernelGspFlcnUcode *pBooterLoadUcode;
KernelGspFlcnUcode *pBooterUnloadUcode;
MEMORY_DESCRIPTOR *pWprMetaDescriptor;
@@ -324,8 +330,12 @@ struct KernelGsp {
MEMORY_DESCRIPTOR *pGspUCodeRadix3Descriptor;
MEMORY_DESCRIPTOR *pSignatureMemdesc;
LIBOS_LOG_DECODE logDecode;
LIBOS_LOG_DECODE logDecodeVgpuPartition[32];
RM_LIBOS_LOG_MEM rmLibosLogMem[3];
RM_LIBOS_LOG_MEM gspPluginInitTaskLogMem[32];
RM_LIBOS_LOG_MEM gspPluginVgpuTaskLogMem[32];
void *pLogElf;
NvU64 logElfDataSize;
NvBool bLibosLogsPollingEnabled;
NvBool bInInit;
NvBool bPollingForRpcResponse;
@@ -402,12 +412,16 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32);
#define kgspIsEngineInReset_HAL(pGpu, pKernelGsp) kgspIsEngineInReset_DISPATCH(pGpu, pKernelGsp)
#define kgspGetFrtsSize(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp)
#define kgspGetFrtsSize_HAL(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp)
#define kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp) kgspGetPrescrubbedTopFbSize_DISPATCH(pGpu, pKernelGsp)
#define kgspGetPrescrubbedTopFbSize_HAL(pGpu, pKernelGsp) kgspGetPrescrubbedTopFbSize_DISPATCH(pGpu, pKernelGsp)
#define kgspExtractVbiosFromRom(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg)
#define kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg)
#define kgspExecuteFwsecFrts(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset)
#define kgspExecuteFwsecFrts_HAL(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset)
#define kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode)
#define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode)
#define kgspExecuteScrubberIfNeeded(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp)
#define kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp)
#define kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset)
#define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset)
#define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp)
@@ -422,6 +436,10 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32);
#define kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp)
#define kgspGetWprHeapSize(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp)
#define kgspGetWprHeapSize_HAL(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp)
#define kgspInitVgpuPartitionLogging(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize)
#define kgspInitVgpuPartitionLogging_HAL(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize)
#define kgspFreeVgpuPartitionLogging(pGpu, pKernelGsp, gfid) kgspFreeVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid)
#define kgspFreeVgpuPartitionLogging_HAL(pGpu, pKernelGsp, gfid) kgspFreeVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid)
#define kgspGetSignatureSectionNamePrefix(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp)
#define kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp)
#define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw)
@@ -681,6 +699,18 @@ static inline NvU32 kgspGetFrtsSize_DISPATCH(struct OBJGPU *pGpu, struct KernelG
return pKernelGsp->__kgspGetFrtsSize__(pGpu, pKernelGsp);
}
static inline NvU64 kgspGetPrescrubbedTopFbSize_e1e623(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return 256 * 1024 * 1024;
}
static inline NvU64 kgspGetPrescrubbedTopFbSize_dd2c0b(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return (NvU64)(-1);
}
static inline NvU64 kgspGetPrescrubbedTopFbSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return pKernelGsp->__kgspGetPrescrubbedTopFbSize__(pGpu, pKernelGsp);
}
NV_STATUS kgspExtractVbiosFromRom_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg);
static inline NV_STATUS kgspExtractVbiosFromRom_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) {
@@ -711,6 +741,16 @@ static inline NV_STATUS kgspExecuteFwsecSb_DISPATCH(struct OBJGPU *pGpu, struct
return pKernelGsp->__kgspExecuteFwsecSb__(pGpu, pKernelGsp, pFwsecUcode);
}
NV_STATUS kgspExecuteScrubberIfNeeded_AD102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp);
static inline NV_STATUS kgspExecuteScrubberIfNeeded_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED);
}
static inline NV_STATUS kgspExecuteScrubberIfNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return pKernelGsp->__kgspExecuteScrubberIfNeeded__(pGpu, pKernelGsp);
}
NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset);
static inline NV_STATUS kgspExecuteBooterLoad_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) {
@@ -787,18 +827,40 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_DISPATCH
return pKernelGsp->__kgspGetBinArchiveBooterUnloadUcode__(pKernelGsp);
}
static inline NvU64 kgspGetWprHeapSize_e77d51(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return (64 * 1024 * 1024);
static inline NvU64 kgspGetWprHeapSize_5661b8(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return 64 * 1024 * 1024;
}
static inline NvU64 kgspGetWprHeapSize_38f3bc(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return (80 * 1024 * 1024);
static inline NvU64 kgspGetWprHeapSize_15390a(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return 80 * 1024 * 1024;
}
NvU64 kgspGetWprHeapSize_AD102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp);
static inline NvU64 kgspGetWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return pKernelGsp->__kgspGetWprHeapSize__(pGpu, pKernelGsp);
}
static inline NV_STATUS kgspInitVgpuPartitionLogging_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kgspInitVgpuPartitionLogging_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize);
static inline NV_STATUS kgspInitVgpuPartitionLogging_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize) {
return pKernelGsp->__kgspInitVgpuPartitionLogging__(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize);
}
static inline NV_STATUS kgspFreeVgpuPartitionLogging_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kgspFreeVgpuPartitionLogging_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid);
static inline NV_STATUS kgspFreeVgpuPartitionLogging_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid) {
return pKernelGsp->__kgspFreeVgpuPartitionLogging__(pGpu, pKernelGsp, gfid);
}
const char *kgspGetSignatureSectionNamePrefix_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp);
static inline const char *kgspGetSignatureSectionNamePrefix_789efb(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
@@ -1034,6 +1096,17 @@ static inline NV_STATUS kgspParseFwsecUcodeFromVbiosImg(struct OBJGPU *pGpu, str
#define kgspParseFwsecUcodeFromVbiosImg(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode) kgspParseFwsecUcodeFromVbiosImg_IMPL(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode)
#endif //__nvoc_kernel_gsp_h_disabled
NV_STATUS kgspAllocateScrubberUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppScrubberUcode);
#ifdef __nvoc_kernel_gsp_h_disabled
static inline NV_STATUS kgspAllocateScrubberUcodeImage(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppScrubberUcode) {
NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else //__nvoc_kernel_gsp_h_disabled
#define kgspAllocateScrubberUcodeImage(pGpu, pKernelGsp, ppScrubberUcode) kgspAllocateScrubberUcodeImage_IMPL(pGpu, pKernelGsp, ppScrubberUcode)
#endif //__nvoc_kernel_gsp_h_disabled
NV_STATUS kgspAllocateBooterLoadUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterLoadUcode);
#ifdef __nvoc_kernel_gsp_h_disabled

2
src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h
View File

@@ -149,7 +149,7 @@ struct KernelHostVgpuDeviceApi {
NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *);
NvBool (*__kernelhostvgpudeviceapiAccessCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, void *, RsAccessRight);
struct KernelHostVgpuDeviceShr *pShared;
NvU32 notifyActions[5];
NvU32 notifyActions[6];
};
#ifndef __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__

14
src/nvidia/generated/g_kernel_nvlink_nvoc.c
View File

@@ -341,6 +341,20 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO
}
}
// Hal function -- knvlinkHandleFaultUpInterrupt
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
{
pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_GH100;
}
// default
else
{
pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_46f6a7;
}
}
// Hal function -- knvlinkValidateFabricBaseAddress
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{

30
src/nvidia/generated/g_kernel_nvlink_nvoc.h
View File

@@ -38,6 +38,7 @@ extern "C" {
#include "core/locks.h"
#include "gpu/eng_state.h"
#include "lib/ref_count.h"
#include "objtmr.h"
#include "nvCpuUuid.h"
#include "gpu/bus/kern_bus.h"
@@ -98,6 +99,9 @@ typedef struct _def_knvlink_conn_info
#define NVLINK_INITOPTIMIZE_POLL_TIMEOUT_EMU 20000000
#define NVLINK_INITOPTIMIZE_POLL_COUNT_DELAY_MS 1000
// Link Retrain after reset time = 10s
#define NVLINK_RETRAIN_TIME 10000000000
/**********************************************************/
// NvGpu identifier in nvlink core library
@@ -179,6 +183,8 @@ typedef struct _def_knvlink_link
// RXDET per-lane status
NvU32 laneRxdetStatusMask;
TMR_EVENT *pTmrEvent;
} KNVLINK_RM_LINK, *PKNVLINK_RM_LINK;
typedef struct NVLINK_INBAND_CALLBACK
@@ -189,6 +195,12 @@ typedef struct NVLINK_INBAND_CALLBACK
NvU32 wqItemFlags;
} NVLINK_INBAND_MSG_CALLBACK;
typedef struct
{
NvU8 linkId;
} NVLINK_ID, *PNVLINK_ID;
MAKE_LIST(FaultUpList, NVLINK_ID);
/*!
* KernelNvlink is a logical abstraction of the GPU Nvlink Engine. The
@@ -215,6 +227,7 @@ struct KernelNvlink {
NV_STATUS (*__knvlinkStatePostUnload__)(OBJGPU *, struct KernelNvlink *, NvU32);
NvBool (*__knvlinkIsPresent__)(OBJGPU *, struct KernelNvlink *);
NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64);
NV_STATUS (*__knvlinkHandleFaultUpInterrupt__)(OBJGPU *, struct KernelNvlink *, NvU32);
NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64);
NvU32 (*__knvlinkGetConnectedLinksMask__)(OBJGPU *, struct KernelNvlink *);
NV_STATUS (*__knvlinkEnableLinksPostTopology__)(OBJGPU *, struct KernelNvlink *, NvU32);
@@ -283,6 +296,7 @@ struct KernelNvlink {
NvU32 bridgeSensableLinks;
NvU32 bridgedLinks;
NvU32 enabledLinks;
FaultUpList faultUpLinks;
NvU32 initializedLinks;
KNVLINK_RM_LINK nvlinkLinks[18];
NvBool bIsGpuDegraded;
@@ -381,6 +395,8 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32);
#define knvlinkIsPresent(arg0, arg1) knvlinkIsPresent_DISPATCH(arg0, arg1)
#define knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0)
#define knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0)
#define knvlinkHandleFaultUpInterrupt(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0)
#define knvlinkHandleFaultUpInterrupt_HAL(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0)
#define knvlinkValidateFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0)
#define knvlinkValidateFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0)
#define knvlinkGetConnectedLinksMask(pGpu, pKernelNvlink) knvlinkGetConnectedLinksMask_DISPATCH(pGpu, pKernelNvlink)
@@ -1351,6 +1367,16 @@ static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu,
return pKernelNvlink->__knvlinkSetUniqueFabricBaseAddress__(pGpu, pKernelNvlink, arg0);
}
NV_STATUS knvlinkHandleFaultUpInterrupt_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0);
static inline NV_STATUS knvlinkHandleFaultUpInterrupt_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) {
return NV_ERR_NOT_SUPPORTED;
}
static inline NV_STATUS knvlinkHandleFaultUpInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) {
return pKernelNvlink->__knvlinkHandleFaultUpInterrupt__(pGpu, pKernelNvlink, arg0);
}
NV_STATUS knvlinkValidateFabricBaseAddress_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0);
NV_STATUS knvlinkValidateFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0);
@@ -1640,7 +1666,7 @@ NV_STATUS knvlinkRetrainLinkFromSafe(OBJGPU *pGpu, struct KernelNvlink *pKernelN
// NVLINK Callback functions from core library
//
#if defined(INCLUDE_NVLINK_LIB)
// Device callback functions
NvlStatus knvlinkCoreAddDeviceCallback (nvlink_device *dev);
@@ -1674,6 +1700,8 @@ NvlStatus knvlinkCoreAliTrainingCallback (nvlink_link *link);
// NVLINK Utility Functions
void knvlinkUtoa(NvU8 *, NvU64, NvU64);
NV_STATUS ioctrlFaultUpTmrHandler(OBJGPU *, struct OBJTMR *,TMR_EVENT *);
#endif // _KERNEL_NVLINK_H_
#ifdef __cplusplus

13
src/nvidia/generated/g_kernel_sec2_nvoc.c
View File

@@ -314,6 +314,19 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner
}
}
// Hal function -- ksec2GetBinArchiveSecurescrubUcode
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */
{
pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438;
}
}
pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine;
pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelSec2_kflcnResetHw;

13
src/nvidia/generated/g_kernel_sec2_nvoc.h
View File

@@ -64,6 +64,7 @@ struct KernelSec2 {
NvU32 (*__ksec2ReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelSec2 *, NvU32);
const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveBlUcode__)(struct OBJGPU *, struct KernelSec2 *);
NV_STATUS (*__ksec2GetGenericBlUcode__)(struct OBJGPU *, struct KernelSec2 *, const RM_FLCN_BL_DESC **, const NvU8 **);
const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveSecurescrubUcode__)(struct OBJGPU *, struct KernelSec2 *);
NV_STATUS (*__ksec2ReconcileTunableState__)(POBJGPU, struct KernelSec2 *, void *);
NV_STATUS (*__ksec2StateLoad__)(POBJGPU, struct KernelSec2 *, NvU32);
NV_STATUS (*__ksec2StateUnload__)(POBJGPU, struct KernelSec2 *, NvU32);
@@ -131,6 +132,8 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32);
#define ksec2GetBinArchiveBlUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2)
#define ksec2GetGenericBlUcode(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg)
#define ksec2GetGenericBlUcode_HAL(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg)
#define ksec2GetBinArchiveSecurescrubUcode(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2)
#define ksec2GetBinArchiveSecurescrubUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2)
#define ksec2ReconcileTunableState(pGpu, pEngstate, pTunableState) ksec2ReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState)
#define ksec2StateLoad(pGpu, pEngstate, arg0) ksec2StateLoad_DISPATCH(pGpu, pEngstate, arg0)
#define ksec2StateUnload(pGpu, pEngstate, arg0) ksec2StateUnload_DISPATCH(pGpu, pEngstate, arg0)
@@ -220,6 +223,16 @@ static inline NV_STATUS ksec2GetGenericBlUcode_DISPATCH(struct OBJGPU *pGpu, str
return pKernelSec2->__ksec2GetGenericBlUcode__(pGpu, pKernelSec2, ppDesc, ppImg);
}
const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_AD10X(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2);
static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_80f438(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0));
}
static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
return pKernelSec2->__ksec2GetBinArchiveSecurescrubUcode__(pGpu, pKernelSec2);
}
static inline NV_STATUS ksec2ReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) {
return pEngstate->__ksec2ReconcileTunableState__(pGpu, pEngstate, pTunableState);
}

349
src/nvidia/generated/g_nv_name_released.h
View File

@@ -808,8 +808,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x20B2, 0x147f, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x1622, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x1623, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B3, 0x14a7, 0x10de, "NVIDIA PG506-242" },
{ 0x20B3, 0x14a8, 0x10de, "NVIDIA PG506-243" },
{ 0x20B3, 0x14a7, 0x10de, "NVIDIA A100-SXM-64GB" },
{ 0x20B3, 0x14a8, 0x10de, "NVIDIA A100-SXM-64GB" },
{ 0x20B5, 0x1533, 0x10de, "NVIDIA A100 80GB PCIe" },
{ 0x20B5, 0x1642, 0x10de, "NVIDIA A100 80GB PCIe" },
{ 0x20B6, 0x1492, 0x10de, "NVIDIA PG506-232" },
@@ -935,6 +935,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2571, 0x1611, 0x103c, "NVIDIA RTX A2000 12GB" },
{ 0x2571, 0x1611, 0x10de, "NVIDIA RTX A2000 12GB" },
{ 0x2571, 0x1611, 0x17aa, "NVIDIA RTX A2000 12GB" },
{ 0x2582, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050" },
{ 0x25A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Ti Laptop GPU" },
{ 0x25A0, 0x8928, 0x103c, "NVIDIA GeForce RTX 3050Ti Laptop GPU" },
{ 0x25A0, 0x89f9, 0x103c, "NVIDIA GeForce RTX 3050Ti Laptop GPU" },
@@ -960,9 +961,13 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x25FA, 0x0000, 0x0000, "NVIDIA RTX A2000 Embedded GPU" },
{ 0x25FB, 0x0000, 0x0000, "NVIDIA RTX A500 Embedded GPU" },
{ 0x2684, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090" },
{ 0x26B1, 0x16a1, 0x1028, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B1, 0x16a1, 0x103c, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B1, 0x16a1, 0x17aa, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B5, 0x169d, 0x10de, "NVIDIA L40" },
{ 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
{ 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" },
{ 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" },
{ 0x13BD, 0x11cd, 0x10DE, "GRID M10-1B" },
{ 0x13BD, 0x11ce, 0x10DE, "GRID M10-0Q" },
@@ -970,6 +975,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x13BD, 0x11d0, 0x10DE, "GRID M10-2Q" },
{ 0x13BD, 0x11d1, 0x10DE, "GRID M10-4Q" },
{ 0x13BD, 0x11d2, 0x10DE, "GRID M10-8Q" },
{ 0x13BD, 0x11d3, 0x10DE, "GRID M10-1A" },
{ 0x13BD, 0x11d4, 0x10DE, "GRID M10-2A" },
{ 0x13BD, 0x11d5, 0x10DE, "GRID M10-4A" },
{ 0x13BD, 0x11d6, 0x10DE, "GRID M10-8A" },
{ 0x13BD, 0x1286, 0x10DE, "GRID M10-2B" },
{ 0x13BD, 0x12ee, 0x10DE, "GRID M10-2B4" },
{ 0x13BD, 0x1339, 0x10DE, "GRID M10-1B4" },
@@ -981,6 +990,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x13F2, 0x1176, 0x10DE, "GRID M60-0B" },
{ 0x13F2, 0x1177, 0x10DE, "GRID M60-1B" },
{ 0x13F2, 0x117d, 0x10DE, "GRID M60-2B" },
{ 0x13F2, 0x11ae, 0x10DE, "GRID M60-1A" },
{ 0x13F2, 0x11af, 0x10DE, "GRID M60-2A" },
{ 0x13F2, 0x11b0, 0x10DE, "GRID M60-4A" },
{ 0x13F2, 0x11b1, 0x10DE, "GRID M60-8A" },
{ 0x13F2, 0x12ec, 0x10DE, "GRID M60-2B4" },
{ 0x13F2, 0x1337, 0x10DE, "GRID M60-1B4" },
{ 0x13F3, 0x117c, 0x10DE, "GRID M6-2B" },
@@ -991,6 +1004,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x13F3, 0x1182, 0x10DE, "GRID M6-2Q" },
{ 0x13F3, 0x1183, 0x10DE, "GRID M6-4Q" },
{ 0x13F3, 0x1184, 0x10DE, "GRID M6-8Q" },
{ 0x13F3, 0x11aa, 0x10DE, "GRID M6-1A" },
{ 0x13F3, 0x11ab, 0x10DE, "GRID M6-2A" },
{ 0x13F3, 0x11ac, 0x10DE, "GRID M6-4A" },
{ 0x13F3, 0x11ad, 0x10DE, "GRID M6-8A" },
{ 0x13F3, 0x12ed, 0x10DE, "GRID M6-2B4" },
{ 0x13F3, 0x1338, 0x10DE, "GRID M6-1B4" },
{ 0x15F7, 0x1265, 0x10DE, "GRID P100C-1B" },
@@ -999,6 +1016,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x15F7, 0x1268, 0x10DE, "GRID P100C-4Q" },
{ 0x15F7, 0x1269, 0x10DE, "GRID P100C-6Q" },
{ 0x15F7, 0x126a, 0x10DE, "GRID P100C-12Q" },
{ 0x15F7, 0x126b, 0x10DE, "GRID P100C-1A" },
{ 0x15F7, 0x126c, 0x10DE, "GRID P100C-2A" },
{ 0x15F7, 0x126d, 0x10DE, "GRID P100C-4A" },
{ 0x15F7, 0x126e, 0x10DE, "GRID P100C-6A" },
{ 0x15F7, 0x126f, 0x10DE, "GRID P100C-12A" },
{ 0x15F7, 0x128d, 0x10DE, "GRID P100C-2B" },
{ 0x15F7, 0x12f4, 0x10DE, "GRID P100C-2B4" },
{ 0x15F7, 0x133f, 0x10DE, "GRID P100C-1B4" },
@@ -1011,6 +1033,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x15F8, 0x1224, 0x10DE, "GRID P100-4Q" },
{ 0x15F8, 0x1225, 0x10DE, "GRID P100-8Q" },
{ 0x15F8, 0x1226, 0x10DE, "GRID P100-16Q" },
{ 0x15F8, 0x1227, 0x10DE, "GRID P100-1A" },
{ 0x15F8, 0x1228, 0x10DE, "GRID P100-2A" },
{ 0x15F8, 0x1229, 0x10DE, "GRID P100-4A" },
{ 0x15F8, 0x122a, 0x10DE, "GRID P100-8A" },
{ 0x15F8, 0x122b, 0x10DE, "GRID P100-16A" },
{ 0x15F8, 0x128c, 0x10DE, "GRID P100-2B" },
{ 0x15F8, 0x12f2, 0x10DE, "GRID P100-2B4" },
{ 0x15F8, 0x133d, 0x10DE, "GRID P100-1B4" },
@@ -1023,6 +1050,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x15F9, 0x122f, 0x10DE, "GRID P100X-4Q" },
{ 0x15F9, 0x1230, 0x10DE, "GRID P100X-8Q" },
{ 0x15F9, 0x1231, 0x10DE, "GRID P100X-16Q" },
{ 0x15F9, 0x1232, 0x10DE, "GRID P100X-1A" },
{ 0x15F9, 0x1233, 0x10DE, "GRID P100X-2A" },
{ 0x15F9, 0x1234, 0x10DE, "GRID P100X-4A" },
{ 0x15F9, 0x1235, 0x10DE, "GRID P100X-8A" },
{ 0x15F9, 0x1236, 0x10DE, "GRID P100X-16A" },
{ 0x15F9, 0x128b, 0x10DE, "GRID P100X-2B" },
{ 0x15F9, 0x12f3, 0x10DE, "GRID P100X-2B4" },
{ 0x15F9, 0x133e, 0x10DE, "GRID P100X-1B4" },
@@ -1038,6 +1070,14 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1B38, 0x11ed, 0x10DE, "GRID P40-8Q" },
{ 0x1B38, 0x11ee, 0x10DE, "GRID P40-12Q" },
{ 0x1B38, 0x11ef, 0x10DE, "GRID P40-24Q" },
{ 0x1B38, 0x11f0, 0x10DE, "GRID P40-1A" },
{ 0x1B38, 0x11f1, 0x10DE, "GRID P40-2A" },
{ 0x1B38, 0x11f2, 0x10DE, "GRID P40-3A" },
{ 0x1B38, 0x11f3, 0x10DE, "GRID P40-4A" },
{ 0x1B38, 0x11f4, 0x10DE, "GRID P40-6A" },
{ 0x1B38, 0x11f5, 0x10DE, "GRID P40-8A" },
{ 0x1B38, 0x11f6, 0x10DE, "GRID P40-12A" },
{ 0x1B38, 0x11f7, 0x10DE, "GRID P40-24A" },
{ 0x1B38, 0x1287, 0x10DE, "GRID P40-2B" },
{ 0x1B38, 0x12b1, 0x10DE, "GeForce GTX P40-24" },
{ 0x1B38, 0x12b2, 0x10DE, "GeForce GTX P40-12" },
@@ -1058,6 +1098,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1BB3, 0x1205, 0x10DE, "GRID P4-2Q" },
{ 0x1BB3, 0x1206, 0x10DE, "GRID P4-4Q" },
{ 0x1BB3, 0x1207, 0x10DE, "GRID P4-8Q" },
{ 0x1BB3, 0x1208, 0x10DE, "GRID P4-1A" },
{ 0x1BB3, 0x1209, 0x10DE, "GRID P4-2A" },
{ 0x1BB3, 0x120a, 0x10DE, "GRID P4-4A" },
{ 0x1BB3, 0x120b, 0x10DE, "GRID P4-8A" },
{ 0x1BB3, 0x1288, 0x10DE, "GRID P4-2B" },
{ 0x1BB3, 0x12f1, 0x10DE, "GRID P4-2B4" },
{ 0x1BB3, 0x133c, 0x10DE, "GRID P4-1B4" },
@@ -1072,6 +1116,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1BB4, 0x11fb, 0x10DE, "GRID P6-4Q" },
{ 0x1BB4, 0x11fc, 0x10DE, "GRID P6-8Q" },
{ 0x1BB4, 0x11fd, 0x10DE, "GRID P6-16Q" },
{ 0x1BB4, 0x11fe, 0x10DE, "GRID P6-1A" },
{ 0x1BB4, 0x11ff, 0x10DE, "GRID P6-2A" },
{ 0x1BB4, 0x1200, 0x10DE, "GRID P6-4A" },
{ 0x1BB4, 0x1201, 0x10DE, "GRID P6-8A" },
{ 0x1BB4, 0x1202, 0x10DE, "GRID P6-16A" },
{ 0x1BB4, 0x1289, 0x10DE, "GRID P6-2B" },
{ 0x1BB4, 0x12f0, 0x10DE, "GRID P6-2B4" },
{ 0x1BB4, 0x133b, 0x10DE, "GRID P6-1B4" },
@@ -1084,6 +1133,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1DB1, 0x125c, 0x10DE, "GRID V100X-4Q" },
{ 0x1DB1, 0x125d, 0x10DE, "GRID V100X-8Q" },
{ 0x1DB1, 0x125e, 0x10DE, "GRID V100X-16Q" },
{ 0x1DB1, 0x125f, 0x10DE, "GRID V100X-1A" },
{ 0x1DB1, 0x1260, 0x10DE, "GRID V100X-2A" },
{ 0x1DB1, 0x1261, 0x10DE, "GRID V100X-4A" },
{ 0x1DB1, 0x1262, 0x10DE, "GRID V100X-8A" },
{ 0x1DB1, 0x1263, 0x10DE, "GRID V100X-16A" },
{ 0x1DB1, 0x128e, 0x10DE, "GRID V100X-2B" },
{ 0x1DB1, 0x12f6, 0x10DE, "GRID V100X-2B4" },
{ 0x1DB1, 0x1341, 0x10DE, "GRID V100X-1B4" },
@@ -1097,6 +1151,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1DB3, 0x1294, 0x10DE, "GRID V100L-4Q" },
{ 0x1DB3, 0x1295, 0x10DE, "GRID V100L-8Q" },
{ 0x1DB3, 0x1296, 0x10DE, "GRID V100L-16Q" },
{ 0x1DB3, 0x1297, 0x10DE, "GRID V100L-1A" },
{ 0x1DB3, 0x1298, 0x10DE, "GRID V100L-2A" },
{ 0x1DB3, 0x1299, 0x10DE, "GRID V100L-4A" },
{ 0x1DB3, 0x129a, 0x10DE, "GRID V100L-8A" },
{ 0x1DB3, 0x129b, 0x10DE, "GRID V100L-16A" },
{ 0x1DB3, 0x12f9, 0x10DE, "GRID V100L-2B4" },
{ 0x1DB3, 0x1344, 0x10DE, "GRID V100L-1B4" },
{ 0x1DB3, 0x137a, 0x10DE, "GRID V100L-16C" },
@@ -1108,6 +1167,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1DB4, 0x1251, 0x10DE, "GRID V100-4Q" },
{ 0x1DB4, 0x1252, 0x10DE, "GRID V100-8Q" },
{ 0x1DB4, 0x1253, 0x10DE, "GRID V100-16Q" },
{ 0x1DB4, 0x1254, 0x10DE, "GRID V100-1A" },
{ 0x1DB4, 0x1255, 0x10DE, "GRID V100-2A" },
{ 0x1DB4, 0x1256, 0x10DE, "GRID V100-4A" },
{ 0x1DB4, 0x1257, 0x10DE, "GRID V100-8A" },
{ 0x1DB4, 0x1258, 0x10DE, "GRID V100-16A" },
{ 0x1DB4, 0x128f, 0x10DE, "GRID V100-2B" },
{ 0x1DB4, 0x12f5, 0x10DE, "GRID V100-2B4" },
{ 0x1DB4, 0x1340, 0x10DE, "GRID V100-1B4" },
@@ -1122,6 +1186,12 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1DB5, 0x12d0, 0x10DE, "GRID V100DX-8Q" },
{ 0x1DB5, 0x12d1, 0x10DE, "GRID V100DX-16Q" },
{ 0x1DB5, 0x12d2, 0x10DE, "GRID V100DX-32Q" },
{ 0x1DB5, 0x12d3, 0x10DE, "GRID V100DX-1A" },
{ 0x1DB5, 0x12d4, 0x10DE, "GRID V100DX-2A" },
{ 0x1DB5, 0x12d5, 0x10DE, "GRID V100DX-4A" },
{ 0x1DB5, 0x12d6, 0x10DE, "GRID V100DX-8A" },
{ 0x1DB5, 0x12d7, 0x10DE, "GRID V100DX-16A" },
{ 0x1DB5, 0x12d8, 0x10DE, "GRID V100DX-32A" },
{ 0x1DB5, 0x12f8, 0x10DE, "GRID V100DX-2B4" },
{ 0x1DB5, 0x1343, 0x10DE, "GRID V100DX-1B4" },
{ 0x1DB5, 0x1376, 0x10DE, "GRID V100DX-32C" },
@@ -1136,6 +1206,12 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1DB6, 0x12c2, 0x10DE, "GRID V100D-8Q" },
{ 0x1DB6, 0x12c3, 0x10DE, "GRID V100D-16Q" },
{ 0x1DB6, 0x12c4, 0x10DE, "GRID V100D-32Q" },
{ 0x1DB6, 0x12c5, 0x10DE, "GRID V100D-1A" },
{ 0x1DB6, 0x12c6, 0x10DE, "GRID V100D-2A" },
{ 0x1DB6, 0x12c7, 0x10DE, "GRID V100D-4A" },
{ 0x1DB6, 0x12c8, 0x10DE, "GRID V100D-8A" },
{ 0x1DB6, 0x12c9, 0x10DE, "GRID V100D-16A" },
{ 0x1DB6, 0x12ca, 0x10DE, "GRID V100D-32A" },
{ 0x1DB6, 0x12f7, 0x10DE, "GRID V100D-2B4" },
{ 0x1DB6, 0x1342, 0x10DE, "GRID V100D-1B4" },
{ 0x1DB6, 0x1377, 0x10DE, "GRID V100D-32C" },
@@ -1153,6 +1229,12 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1DF6, 0x13e8, 0x10DE, "GRID V100S-8Q" },
{ 0x1DF6, 0x13e9, 0x10DE, "GRID V100S-16Q" },
{ 0x1DF6, 0x13ea, 0x10DE, "GRID V100S-32Q" },
{ 0x1DF6, 0x13eb, 0x10DE, "GRID V100S-1A" },
{ 0x1DF6, 0x13ec, 0x10DE, "GRID V100S-2A" },
{ 0x1DF6, 0x13ed, 0x10DE, "GRID V100S-4A" },
{ 0x1DF6, 0x13ee, 0x10DE, "GRID V100S-8A" },
{ 0x1DF6, 0x13ef, 0x10DE, "GRID V100S-16A" },
{ 0x1DF6, 0x13f0, 0x10DE, "GRID V100S-32A" },
{ 0x1DF6, 0x13f1, 0x10DE, "GRID V100S-4C" },
{ 0x1DF6, 0x13f2, 0x10DE, "GRID V100S-8C" },
{ 0x1DF6, 0x13f3, 0x10DE, "GRID V100S-16C" },
@@ -1197,8 +1279,26 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1E30, 0x13cc, 0x10DE, "GRID RTX8000-16" },
{ 0x1E30, 0x1437, 0x10DE, "GRID RTX6000-1B" },
{ 0x1E30, 0x1438, 0x10DE, "GRID RTX6000-2B" },
{ 0x1E30, 0x1439, 0x10DE, "GRID RTX6000-1A" },
{ 0x1E30, 0x143a, 0x10DE, "GRID RTX6000-2A" },
{ 0x1E30, 0x143b, 0x10DE, "GRID RTX6000-3A" },
{ 0x1E30, 0x143c, 0x10DE, "GRID RTX6000-4A" },
{ 0x1E30, 0x143d, 0x10DE, "GRID RTX6000-6A" },
{ 0x1E30, 0x143e, 0x10DE, "GRID RTX6000-8A" },
{ 0x1E30, 0x143f, 0x10DE, "GRID RTX6000-12A" },
{ 0x1E30, 0x1440, 0x10DE, "GRID RTX6000-24A" },
{ 0x1E30, 0x1441, 0x10DE, "GRID RTX8000-1B" },
{ 0x1E30, 0x1442, 0x10DE, "GRID RTX8000-2B" },
{ 0x1E30, 0x1443, 0x10DE, "GRID RTX8000-1A" },
{ 0x1E30, 0x1444, 0x10DE, "GRID RTX8000-2A" },
{ 0x1E30, 0x1445, 0x10DE, "GRID RTX8000-3A" },
{ 0x1E30, 0x1446, 0x10DE, "GRID RTX8000-4A" },
{ 0x1E30, 0x1447, 0x10DE, "GRID RTX8000-6A" },
{ 0x1E30, 0x1448, 0x10DE, "GRID RTX8000-8A" },
{ 0x1E30, 0x1449, 0x10DE, "GRID RTX8000-12A" },
{ 0x1E30, 0x144a, 0x10DE, "GRID RTX8000-16A" },
{ 0x1E30, 0x144b, 0x10DE, "GRID RTX8000-24A" },
{ 0x1E30, 0x144c, 0x10DE, "GRID RTX8000-48A" },
{ 0x1E37, 0x1347, 0x10DE, "GeForce RTX T10x-8" },
{ 0x1E37, 0x1348, 0x10DE, "GeForce RTX T10x-4" },
{ 0x1E37, 0x1349, 0x10DE, "GeForce RTX T10x-2" },
@@ -1224,6 +1324,14 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1E78, 0x13fe, 0x10DE, "GRID RTX6000P-8Q" },
{ 0x1E78, 0x13ff, 0x10DE, "GRID RTX6000P-12Q" },
{ 0x1E78, 0x1400, 0x10DE, "GRID RTX6000P-24Q" },
{ 0x1E78, 0x1401, 0x10DE, "GRID RTX6000P-1A" },
{ 0x1E78, 0x1402, 0x10DE, "GRID RTX6000P-2A" },
{ 0x1E78, 0x1403, 0x10DE, "GRID RTX6000P-3A" },
{ 0x1E78, 0x1404, 0x10DE, "GRID RTX6000P-4A" },
{ 0x1E78, 0x1405, 0x10DE, "GRID RTX6000P-6A" },
{ 0x1E78, 0x1406, 0x10DE, "GRID RTX6000P-8A" },
{ 0x1E78, 0x1407, 0x10DE, "GRID RTX6000P-12A" },
{ 0x1E78, 0x1408, 0x10DE, "GRID RTX6000P-24A" },
{ 0x1E78, 0x1409, 0x10DE, "GRID RTX6000P-6" },
{ 0x1E78, 0x140a, 0x10DE, "GRID RTX6000P-8" },
{ 0x1E78, 0x140b, 0x10DE, "GRID RTX6000P-12" },
@@ -1245,6 +1353,15 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1E78, 0x141b, 0x10DE, "GRID RTX8000P-16Q" },
{ 0x1E78, 0x141c, 0x10DE, "GRID RTX8000P-24Q" },
{ 0x1E78, 0x141d, 0x10DE, "GRID RTX8000P-48Q" },
{ 0x1E78, 0x141e, 0x10DE, "GRID RTX8000P-1A" },
{ 0x1E78, 0x141f, 0x10DE, "GRID RTX8000P-2A" },
{ 0x1E78, 0x1420, 0x10DE, "GRID RTX8000P-3A" },
{ 0x1E78, 0x1421, 0x10DE, "GRID RTX8000P-4A" },
{ 0x1E78, 0x1422, 0x10DE, "GRID RTX8000P-6A" },
{ 0x1E78, 0x1423, 0x10DE, "GRID RTX8000P-8A" },
{ 0x1E78, 0x1424, 0x10DE, "GRID RTX8000P-12A" },
{ 0x1E78, 0x1425, 0x10DE, "GRID RTX8000P-24A" },
{ 0x1E78, 0x1426, 0x10DE, "GRID RTX8000P-48A" },
{ 0x1E78, 0x1427, 0x10DE, "GRID RTX8000P-12" },
{ 0x1E78, 0x1428, 0x10DE, "GRID RTX8000P-16" },
{ 0x1E78, 0x1429, 0x10DE, "GRID RTX8000P-24" },
@@ -1256,6 +1373,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1E78, 0x142f, 0x10DE, "GRID RTX8000P-16C" },
{ 0x1E78, 0x1430, 0x10DE, "GRID RTX8000P-24C" },
{ 0x1E78, 0x1431, 0x10DE, "GRID RTX8000P-48C" },
{ 0x1E78, 0x1436, 0x10DE, "GRID RTX8000P-16A" },
{ 0x1EB8, 0x1309, 0x10DE, "GRID T4-1B" },
{ 0x1EB8, 0x130a, 0x10DE, "GRID T4-2B" },
{ 0x1EB8, 0x130b, 0x10DE, "GRID T4-2B4" },
@@ -1264,6 +1382,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1EB8, 0x130e, 0x10DE, "GRID T4-4Q" },
{ 0x1EB8, 0x130f, 0x10DE, "GRID T4-8Q" },
{ 0x1EB8, 0x1310, 0x10DE, "GRID T4-16Q" },
{ 0x1EB8, 0x1311, 0x10DE, "GRID T4-1A" },
{ 0x1EB8, 0x1312, 0x10DE, "GRID T4-2A" },
{ 0x1EB8, 0x1313, 0x10DE, "GRID T4-4A" },
{ 0x1EB8, 0x1314, 0x10DE, "GRID T4-8A" },
{ 0x1EB8, 0x1315, 0x10DE, "GRID T4-16A" },
{ 0x1EB8, 0x1345, 0x10DE, "GRID T4-1B4" },
{ 0x1EB8, 0x1367, 0x10DE, "GRID RTX T4-4" },
{ 0x1EB8, 0x1368, 0x10DE, "GRID RTX T4-8" },
@@ -1382,6 +1505,16 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2230, 0x1503, 0x10DE, "NVIDIA RTXA6000-16Q" },
{ 0x2230, 0x1504, 0x10DE, "NVIDIA RTXA6000-24Q" },
{ 0x2230, 0x1505, 0x10DE, "NVIDIA RTXA6000-48Q" },
{ 0x2230, 0x1506, 0x10DE, "NVIDIA RTXA6000-1A" },
{ 0x2230, 0x1507, 0x10DE, "NVIDIA RTXA6000-2A" },
{ 0x2230, 0x1508, 0x10DE, "NVIDIA RTXA6000-3A" },
{ 0x2230, 0x1509, 0x10DE, "NVIDIA RTXA6000-4A" },
{ 0x2230, 0x150a, 0x10DE, "NVIDIA RTXA6000-6A" },
{ 0x2230, 0x150b, 0x10DE, "NVIDIA RTXA6000-8A" },
{ 0x2230, 0x150c, 0x10DE, "NVIDIA RTXA6000-12A" },
{ 0x2230, 0x150d, 0x10DE, "NVIDIA RTXA6000-16A" },
{ 0x2230, 0x150e, 0x10DE, "NVIDIA RTXA6000-24A" },
{ 0x2230, 0x150f, 0x10DE, "NVIDIA RTXA6000-48A" },
{ 0x2230, 0x1510, 0x10DE, "NVIDIA RTXA6000-12" },
{ 0x2230, 0x1511, 0x10DE, "NVIDIA RTXA6000-16" },
{ 0x2230, 0x1512, 0x10DE, "NVIDIA RTXA6000-24" },
@@ -1403,6 +1536,14 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2231, 0x1569, 0x10DE, "NVIDIA RTXA5000-8Q" },
{ 0x2231, 0x156a, 0x10DE, "NVIDIA RTXA5000-12Q" },
{ 0x2231, 0x156b, 0x10DE, "NVIDIA RTXA5000-24Q" },
{ 0x2231, 0x156c, 0x10DE, "NVIDIA RTXA5000-1A" },
{ 0x2231, 0x156d, 0x10DE, "NVIDIA RTXA5000-2A" },
{ 0x2231, 0x156e, 0x10DE, "NVIDIA RTXA5000-3A" },
{ 0x2231, 0x156f, 0x10DE, "NVIDIA RTXA5000-4A" },
{ 0x2231, 0x1570, 0x10DE, "NVIDIA RTXA5000-6A" },
{ 0x2231, 0x1571, 0x10DE, "NVIDIA RTXA5000-8A" },
{ 0x2231, 0x1572, 0x10DE, "NVIDIA RTXA5000-12A" },
{ 0x2231, 0x1573, 0x10DE, "NVIDIA RTXA5000-24A" },
{ 0x2231, 0x1574, 0x10DE, "NVIDIA RTXA5000-6" },
{ 0x2231, 0x1575, 0x10DE, "NVIDIA RTXA5000-8" },
{ 0x2231, 0x1576, 0x10DE, "NVIDIA RTXA5000-12" },
@@ -1422,6 +1563,14 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2233, 0x1663, 0x10DE, "NVIDIA RTXA5500-8Q" },
{ 0x2233, 0x1664, 0x10DE, "NVIDIA RTXA5500-12Q" },
{ 0x2233, 0x1665, 0x10DE, "NVIDIA RTXA5500-24Q" },
{ 0x2233, 0x1666, 0x10DE, "NVIDIA RTXA5500-1A" },
{ 0x2233, 0x1667, 0x10DE, "NVIDIA RTXA5500-2A" },
{ 0x2233, 0x1668, 0x10DE, "NVIDIA RTXA5500-3A" },
{ 0x2233, 0x1669, 0x10DE, "NVIDIA RTXA5500-4A" },
{ 0x2233, 0x166a, 0x10DE, "NVIDIA RTXA5500-6A" },
{ 0x2233, 0x166b, 0x10DE, "NVIDIA RTXA5500-8A" },
{ 0x2233, 0x166c, 0x10DE, "NVIDIA RTXA5500-12A" },
{ 0x2233, 0x166d, 0x10DE, "NVIDIA RTXA5500-24A" },
{ 0x2233, 0x166e, 0x10DE, "NVIDIA RTXA5500-6" },
{ 0x2233, 0x166f, 0x10DE, "NVIDIA RTXA5500-8" },
{ 0x2233, 0x1670, 0x10DE, "NVIDIA RTXA5500-12" },
@@ -1443,6 +1592,16 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2235, 0x14de, 0x10DE, "NVIDIA A40-16Q" },
{ 0x2235, 0x14df, 0x10DE, "NVIDIA A40-24Q" },
{ 0x2235, 0x14e0, 0x10DE, "NVIDIA A40-48Q" },
{ 0x2235, 0x14e1, 0x10DE, "NVIDIA A40-1A" },
{ 0x2235, 0x14e2, 0x10DE, "NVIDIA A40-2A" },
{ 0x2235, 0x14e3, 0x10DE, "NVIDIA A40-3A" },
{ 0x2235, 0x14e4, 0x10DE, "NVIDIA A40-4A" },
{ 0x2235, 0x14e5, 0x10DE, "NVIDIA A40-6A" },
{ 0x2235, 0x14e6, 0x10DE, "NVIDIA A40-8A" },
{ 0x2235, 0x14e7, 0x10DE, "NVIDIA A40-12A" },
{ 0x2235, 0x14e8, 0x10DE, "NVIDIA A40-16A" },
{ 0x2235, 0x14e9, 0x10DE, "NVIDIA A40-24A" },
{ 0x2235, 0x14ea, 0x10DE, "NVIDIA A40-48A" },
{ 0x2235, 0x14eb, 0x10DE, "NVIDIA A40-12" },
{ 0x2235, 0x14ec, 0x10DE, "NVIDIA A40-16" },
{ 0x2235, 0x14ed, 0x10DE, "NVIDIA A40-24" },
@@ -1470,6 +1629,14 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2236, 0x14bd, 0x10DE, "NVIDIA A10-8Q" },
{ 0x2236, 0x14be, 0x10DE, "NVIDIA A10-12Q" },
{ 0x2236, 0x14bf, 0x10DE, "NVIDIA A10-24Q" },
{ 0x2236, 0x14c0, 0x10DE, "NVIDIA A10-1A" },
{ 0x2236, 0x14c1, 0x10DE, "NVIDIA A10-2A" },
{ 0x2236, 0x14c2, 0x10DE, "NVIDIA A10-3A" },
{ 0x2236, 0x14c3, 0x10DE, "NVIDIA A10-4A" },
{ 0x2236, 0x14c4, 0x10DE, "NVIDIA A10-6A" },
{ 0x2236, 0x14c5, 0x10DE, "NVIDIA A10-8A" },
{ 0x2236, 0x14c6, 0x10DE, "NVIDIA A10-12A" },
{ 0x2236, 0x14c7, 0x10DE, "NVIDIA A10-24A" },
{ 0x2236, 0x14c8, 0x10DE, "NVIDIA A10-6" },
{ 0x2236, 0x14c9, 0x10DE, "NVIDIA A10-8" },
{ 0x2236, 0x14ca, 0x10DE, "NVIDIA A10-12" },
@@ -1501,6 +1668,14 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2237, 0x1631, 0x10DE, "NVIDIA A10G-8Q" },
{ 0x2237, 0x1632, 0x10DE, "NVIDIA A10G-12Q" },
{ 0x2237, 0x1633, 0x10DE, "NVIDIA A10G-24Q" },
{ 0x2237, 0x1634, 0x10DE, "NVIDIA A10G-1A" },
{ 0x2237, 0x1635, 0x10DE, "NVIDIA A10G-2A" },
{ 0x2237, 0x1636, 0x10DE, "NVIDIA A10G-3A" },
{ 0x2237, 0x1637, 0x10DE, "NVIDIA A10G-4A" },
{ 0x2237, 0x1638, 0x10DE, "NVIDIA A10G-6A" },
{ 0x2237, 0x1639, 0x10DE, "NVIDIA A10G-8A" },
{ 0x2237, 0x163a, 0x10DE, "NVIDIA A10G-12A" },
{ 0x2237, 0x163b, 0x10DE, "NVIDIA A10G-24A" },
{ 0x2238, 0x16a3, 0x10DE, "NVIDIA A10M-1B" },
{ 0x2238, 0x16a4, 0x10DE, "NVIDIA A10M-2B" },
{ 0x2238, 0x16a5, 0x10DE, "NVIDIA A10M-1Q" },
@@ -1509,6 +1684,12 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2238, 0x16a8, 0x10DE, "NVIDIA A10M-5Q" },
{ 0x2238, 0x16a9, 0x10DE, "NVIDIA A10M-10Q" },
{ 0x2238, 0x16aa, 0x10DE, "NVIDIA A10M-20Q" },
{ 0x2238, 0x16ab, 0x10DE, "NVIDIA A10M-1A" },
{ 0x2238, 0x16ac, 0x10DE, "NVIDIA A10M-2A" },
{ 0x2238, 0x16ad, 0x10DE, "NVIDIA A10M-4A" },
{ 0x2238, 0x16ae, 0x10DE, "NVIDIA A10M-5A" },
{ 0x2238, 0x16af, 0x10DE, "NVIDIA A10M-10A" },
{ 0x2238, 0x16b0, 0x10DE, "NVIDIA A10M-20A" },
{ 0x2238, 0x16b1, 0x10DE, "NVIDIA A10M-2" },
{ 0x2238, 0x16b2, 0x10DE, "NVIDIA A10M-4" },
{ 0x2238, 0x16b3, 0x10DE, "NVIDIA A10M-5" },
@@ -1519,6 +1700,20 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" },
{ 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" },
{ 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" },
{ 0x2322, 0x17e2, 0x10DE, "NVIDIA H800-1-10CME" },
{ 0x2322, 0x17e3, 0x10DE, "NVIDIA H800-1-10C" },
{ 0x2322, 0x17e4, 0x10DE, "NVIDIA H800-2-20C" },
{ 0x2322, 0x17e5, 0x10DE, "NVIDIA H800-3-40C" },
{ 0x2322, 0x17e6, 0x10DE, "NVIDIA H800-4-40C" },
{ 0x2322, 0x17e7, 0x10DE, "NVIDIA H800-7-80C" },
{ 0x2322, 0x17e8, 0x10DE, "NVIDIA H800-4C" },
{ 0x2322, 0x17e9, 0x10DE, "NVIDIA H800-5C" },
{ 0x2322, 0x17ea, 0x10DE, "NVIDIA H800-8C" },
{ 0x2322, 0x17eb, 0x10DE, "NVIDIA H800-10C" },
{ 0x2322, 0x17ec, 0x10DE, "NVIDIA H800-16C" },
{ 0x2322, 0x17ed, 0x10DE, "NVIDIA H800-20C" },
{ 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" },
{ 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" },
{ 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" },
{ 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" },
{ 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" },
@@ -1540,6 +1735,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x25B6, 0x1601, 0x10DE, "NVIDIA A16-4Q" },
{ 0x25B6, 0x1602, 0x10DE, "NVIDIA A16-8Q" },
{ 0x25B6, 0x1603, 0x10DE, "NVIDIA A16-16Q" },
{ 0x25B6, 0x1604, 0x10DE, "NVIDIA A16-1A" },
{ 0x25B6, 0x1605, 0x10DE, "NVIDIA A16-2A" },
{ 0x25B6, 0x1606, 0x10DE, "NVIDIA A16-4A" },
{ 0x25B6, 0x1607, 0x10DE, "NVIDIA A16-8A" },
{ 0x25B6, 0x1608, 0x10DE, "NVIDIA A16-16A" },
{ 0x25B6, 0x1609, 0x10DE, "NVIDIA A16-4C" },
{ 0x25B6, 0x160a, 0x10DE, "NVIDIA A16-8C" },
{ 0x25B6, 0x160b, 0x10DE, "NVIDIA A16-16C" },
@@ -1550,12 +1750,157 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x25B6, 0x164a, 0x10DE, "NVIDIA A2-4Q" },
{ 0x25B6, 0x164b, 0x10DE, "NVIDIA A2-8Q" },
{ 0x25B6, 0x164c, 0x10DE, "NVIDIA A2-16Q" },
{ 0x25B6, 0x164d, 0x10DE, "NVIDIA A2-1A" },
{ 0x25B6, 0x164e, 0x10DE, "NVIDIA A2-2A" },
{ 0x25B6, 0x164f, 0x10DE, "NVIDIA A2-4A" },
{ 0x25B6, 0x1650, 0x10DE, "NVIDIA A2-8A" },
{ 0x25B6, 0x1651, 0x10DE, "NVIDIA A2-16A" },
{ 0x25B6, 0x1652, 0x10DE, "NVIDIA A2-4" },
{ 0x25B6, 0x1653, 0x10DE, "NVIDIA A2-8" },
{ 0x25B6, 0x1654, 0x10DE, "NVIDIA A2-16" },
{ 0x25B6, 0x1655, 0x10DE, "NVIDIA A2-4C" },
{ 0x25B6, 0x1656, 0x10DE, "NVIDIA A2-8C" },
{ 0x25B6, 0x1657, 0x10DE, "NVIDIA A2-16C" },
{ 0x26B1, 0x1708, 0x10DE, "NVIDIA RTX 6000 Ada-1B" },
{ 0x26B1, 0x1709, 0x10DE, "NVIDIA RTX 6000 Ada-2B" },
{ 0x26B1, 0x170a, 0x10DE, "NVIDIA RTX 6000 Ada-1Q" },
{ 0x26B1, 0x170b, 0x10DE, "NVIDIA RTX 6000 Ada-2Q" },
{ 0x26B1, 0x170c, 0x10DE, "NVIDIA RTX 6000 Ada-3Q" },
{ 0x26B1, 0x170d, 0x10DE, "NVIDIA RTX 6000 Ada-4Q" },
{ 0x26B1, 0x170e, 0x10DE, "NVIDIA RTX 6000 Ada-6Q" },
{ 0x26B1, 0x170f, 0x10DE, "NVIDIA RTX 6000 Ada-8Q" },
{ 0x26B1, 0x1710, 0x10DE, "NVIDIA RTX 6000 Ada-12Q" },
{ 0x26B1, 0x1711, 0x10DE, "NVIDIA RTX 6000 Ada-16Q" },
{ 0x26B1, 0x1712, 0x10DE, "NVIDIA RTX 6000 Ada-24Q" },
{ 0x26B1, 0x1713, 0x10DE, "NVIDIA RTX 6000 Ada-48Q" },
{ 0x26B1, 0x1714, 0x10DE, "NVIDIA RTX 6000 Ada-1A" },
{ 0x26B1, 0x1715, 0x10DE, "NVIDIA RTX 6000 Ada-2A" },
{ 0x26B1, 0x1716, 0x10DE, "NVIDIA RTX 6000 Ada-3A" },
{ 0x26B1, 0x1717, 0x10DE, "NVIDIA RTX 6000 Ada-4A" },
{ 0x26B1, 0x1718, 0x10DE, "NVIDIA RTX 6000 Ada-6A" },
{ 0x26B1, 0x1719, 0x10DE, "NVIDIA RTX 6000 Ada-8A" },
{ 0x26B1, 0x171a, 0x10DE, "NVIDIA RTX 6000 Ada-12A" },
{ 0x26B1, 0x171b, 0x10DE, "NVIDIA RTX 6000 Ada-16A" },
{ 0x26B1, 0x171c, 0x10DE, "NVIDIA RTX 6000 Ada-24A" },
{ 0x26B1, 0x171d, 0x10DE, "NVIDIA RTX 6000 Ada-48A" },
{ 0x26B1, 0x171e, 0x10DE, "NVIDIA RTX 6000 Ada-1" },
{ 0x26B1, 0x171f, 0x10DE, "NVIDIA RTX 6000 Ada-2" },
{ 0x26B1, 0x1720, 0x10DE, "NVIDIA RTX 6000 Ada-3" },
{ 0x26B1, 0x1721, 0x10DE, "NVIDIA RTX 6000 Ada-4" },
{ 0x26B1, 0x1722, 0x10DE, "NVIDIA RTX 6000 Ada-6" },
{ 0x26B1, 0x1723, 0x10DE, "NVIDIA RTX 6000 Ada-8" },
{ 0x26B1, 0x1724, 0x10DE, "NVIDIA RTX 6000 Ada-12" },
{ 0x26B1, 0x1725, 0x10DE, "NVIDIA RTX 6000 Ada-16" },
{ 0x26B1, 0x1726, 0x10DE, "NVIDIA RTX 6000 Ada-24" },
{ 0x26B1, 0x1727, 0x10DE, "NVIDIA RTX 6000 Ada-48" },
{ 0x26B1, 0x1728, 0x10DE, "NVIDIA RTX 6000 Ada-4C" },
{ 0x26B1, 0x1729, 0x10DE, "NVIDIA RTX 6000 Ada-6C" },
{ 0x26B1, 0x172a, 0x10DE, "NVIDIA RTX 6000 Ada-8C" },
{ 0x26B1, 0x172b, 0x10DE, "NVIDIA RTX 6000 Ada-12C" },
{ 0x26B1, 0x172c, 0x10DE, "NVIDIA RTX 6000 Ada-16C" },
{ 0x26B1, 0x172d, 0x10DE, "NVIDIA RTX 6000 Ada-24C" },
{ 0x26B1, 0x172e, 0x10DE, "NVIDIA RTX 6000 Ada-48C" },
{ 0x26B5, 0x176d, 0x10DE, "NVIDIA L40-1B" },
{ 0x26B5, 0x176e, 0x10DE, "NVIDIA L40-2B" },
{ 0x26B5, 0x176f, 0x10DE, "NVIDIA L40-1Q" },
{ 0x26B5, 0x1770, 0x10DE, "NVIDIA L40-2Q" },
{ 0x26B5, 0x1771, 0x10DE, "NVIDIA L40-3Q" },
{ 0x26B5, 0x1772, 0x10DE, "NVIDIA L40-4Q" },
{ 0x26B5, 0x1773, 0x10DE, "NVIDIA L40-6Q" },
{ 0x26B5, 0x1774, 0x10DE, "NVIDIA L40-8Q" },
{ 0x26B5, 0x1775, 0x10DE, "NVIDIA L40-12Q" },
{ 0x26B5, 0x1776, 0x10DE, "NVIDIA L40-16Q" },
{ 0x26B5, 0x1777, 0x10DE, "NVIDIA L40-24Q" },
{ 0x26B5, 0x1778, 0x10DE, "NVIDIA L40-48Q" },
{ 0x26B5, 0x1779, 0x10DE, "NVIDIA L40-1A" },
{ 0x26B5, 0x177a, 0x10DE, "NVIDIA L40-2A" },
{ 0x26B5, 0x177b, 0x10DE, "NVIDIA L40-3A" },
{ 0x26B5, 0x177c, 0x10DE, "NVIDIA L40-4A" },
{ 0x26B5, 0x177d, 0x10DE, "NVIDIA L40-6A" },
{ 0x26B5, 0x177e, 0x10DE, "NVIDIA L40-8A" },
{ 0x26B5, 0x177f, 0x10DE, "NVIDIA L40-12A" },
{ 0x26B5, 0x1780, 0x10DE, "NVIDIA L40-16A" },
{ 0x26B5, 0x1781, 0x10DE, "NVIDIA L40-24A" },
{ 0x26B5, 0x1782, 0x10DE, "NVIDIA L40-48A" },
{ 0x26B5, 0x1783, 0x10DE, "NVIDIA L40-1" },
{ 0x26B5, 0x1784, 0x10DE, "NVIDIA L40-2" },
{ 0x26B5, 0x1785, 0x10DE, "NVIDIA L40-3" },
{ 0x26B5, 0x1786, 0x10DE, "NVIDIA L40-4" },
{ 0x26B5, 0x1787, 0x10DE, "NVIDIA L40-6" },
{ 0x26B5, 0x1788, 0x10DE, "NVIDIA L40-8" },
{ 0x26B5, 0x1789, 0x10DE, "NVIDIA L40-12" },
{ 0x26B5, 0x178a, 0x10DE, "NVIDIA L40-16" },
{ 0x26B5, 0x178b, 0x10DE, "NVIDIA L40-24" },
{ 0x26B5, 0x178c, 0x10DE, "NVIDIA L40-48" },
{ 0x26B5, 0x178d, 0x10DE, "NVIDIA L40-4C" },
{ 0x26B5, 0x178e, 0x10DE, "NVIDIA L40-6C" },
{ 0x26B5, 0x178f, 0x10DE, "NVIDIA L40-8C" },
{ 0x26B5, 0x1790, 0x10DE, "NVIDIA L40-12C" },
{ 0x26B5, 0x1791, 0x10DE, "NVIDIA L40-16C" },
{ 0x26B5, 0x1792, 0x10DE, "NVIDIA L40-24C" },
{ 0x26B5, 0x1793, 0x10DE, "NVIDIA L40-48C" },
{ 0x26B8, 0x174e, 0x10DE, "NVIDIA L40G-1B" },
{ 0x26B8, 0x174f, 0x10DE, "NVIDIA L40G-2B" },
{ 0x26B8, 0x1750, 0x10DE, "NVIDIA L40G-1Q" },
{ 0x26B8, 0x1751, 0x10DE, "NVIDIA L40G-2Q" },
{ 0x26B8, 0x1752, 0x10DE, "NVIDIA L40G-3Q" },
{ 0x26B8, 0x1753, 0x10DE, "NVIDIA L40G-4Q" },
{ 0x26B8, 0x1754, 0x10DE, "NVIDIA L40G-6Q" },
{ 0x26B8, 0x1755, 0x10DE, "NVIDIA L40G-8Q" },
{ 0x26B8, 0x1756, 0x10DE, "NVIDIA L40G-12Q" },
{ 0x26B8, 0x1757, 0x10DE, "NVIDIA L40G-24Q" },
{ 0x26B8, 0x1758, 0x10DE, "NVIDIA L40G-1A" },
{ 0x26B8, 0x1759, 0x10DE, "NVIDIA L40G-2A" },
{ 0x26B8, 0x175a, 0x10DE, "NVIDIA L40G-3A" },
{ 0x26B8, 0x175b, 0x10DE, "NVIDIA L40G-4A" },
{ 0x26B8, 0x175c, 0x10DE, "NVIDIA L40G-6A" },
{ 0x26B8, 0x175d, 0x10DE, "NVIDIA L40G-8A" },
{ 0x26B8, 0x175e, 0x10DE, "NVIDIA L40G-12A" },
{ 0x26B8, 0x175f, 0x10DE, "NVIDIA L40G-24A" },
{ 0x26B8, 0x1760, 0x10DE, "NVIDIA L40G-1" },
{ 0x26B8, 0x1761, 0x10DE, "NVIDIA L40G-2" },
{ 0x26B8, 0x1762, 0x10DE, "NVIDIA L40G-3" },
{ 0x26B8, 0x1763, 0x10DE, "NVIDIA L40G-4" },
{ 0x26B8, 0x1764, 0x10DE, "NVIDIA L40G-6" },
{ 0x26B8, 0x1765, 0x10DE, "NVIDIA L40G-8" },
{ 0x26B8, 0x1766, 0x10DE, "NVIDIA L40G-12" },
{ 0x26B8, 0x1767, 0x10DE, "NVIDIA L40G-24" },
{ 0x26B8, 0x1768, 0x10DE, "NVIDIA L40G-4C" },
{ 0x26B8, 0x1769, 0x10DE, "NVIDIA L40G-6C" },
{ 0x26B8, 0x176a, 0x10DE, "NVIDIA L40G-8C" },
{ 0x26B8, 0x176b, 0x10DE, "NVIDIA L40G-12C" },
{ 0x26B8, 0x176c, 0x10DE, "NVIDIA L40G-24C" },
{ 0x27B8, 0x172f, 0x10DE, "NVIDIA GPU 27B8-172F" },
{ 0x27B8, 0x1730, 0x10DE, "NVIDIA GPU 27B8-1730" },
{ 0x27B8, 0x1731, 0x10DE, "NVIDIA GPU 27B8-1731" },
{ 0x27B8, 0x1732, 0x10DE, "NVIDIA GPU 27B8-1732" },
{ 0x27B8, 0x1733, 0x10DE, "NVIDIA GPU 27B8-1733" },
{ 0x27B8, 0x1734, 0x10DE, "NVIDIA GPU 27B8-1734" },
{ 0x27B8, 0x1735, 0x10DE, "NVIDIA GPU 27B8-1735" },
{ 0x27B8, 0x1736, 0x10DE, "NVIDIA GPU 27B8-1736" },
{ 0x27B8, 0x1737, 0x10DE, "NVIDIA GPU 27B8-1737" },
{ 0x27B8, 0x1738, 0x10DE, "NVIDIA GPU 27B8-1738" },
{ 0x27B8, 0x1739, 0x10DE, "NVIDIA GPU 27B8-1739" },
{ 0x27B8, 0x173a, 0x10DE, "NVIDIA GPU 27B8-173A" },
{ 0x27B8, 0x173b, 0x10DE, "NVIDIA GPU 27B8-173B" },
{ 0x27B8, 0x173c, 0x10DE, "NVIDIA GPU 27B8-173C" },
{ 0x27B8, 0x173d, 0x10DE, "NVIDIA GPU 27B8-173D" },
{ 0x27B8, 0x173e, 0x10DE, "NVIDIA GPU 27B8-173E" },
{ 0x27B8, 0x173f, 0x10DE, "NVIDIA GPU 27B8-173F" },
{ 0x27B8, 0x1740, 0x10DE, "NVIDIA GPU 27B8-1740" },
{ 0x27B8, 0x1741, 0x10DE, "NVIDIA GPU 27B8-1741" },
{ 0x27B8, 0x1742, 0x10DE, "NVIDIA GPU 27B8-1742" },
{ 0x27B8, 0x1743, 0x10DE, "NVIDIA GPU 27B8-1743" },
{ 0x27B8, 0x1744, 0x10DE, "NVIDIA GPU 27B8-1744" },
{ 0x27B8, 0x1745, 0x10DE, "NVIDIA GPU 27B8-1745" },
{ 0x27B8, 0x1746, 0x10DE, "NVIDIA GPU 27B8-1746" },
{ 0x27B8, 0x1747, 0x10DE, "NVIDIA GPU 27B8-1747" },
{ 0x27B8, 0x1748, 0x10DE, "NVIDIA GPU 27B8-1748" },
{ 0x27B8, 0x1749, 0x10DE, "NVIDIA GPU 27B8-1749" },
{ 0x27B8, 0x174a, 0x10DE, "NVIDIA GPU 27B8-174A" },
{ 0x27B8, 0x174b, 0x10DE, "NVIDIA GPU 27B8-174B" },
{ 0x27B8, 0x174c, 0x10DE, "NVIDIA GPU 27B8-174C" },
{ 0x27B8, 0x174d, 0x10DE, "NVIDIA GPU 27B8-174D" },
};
#endif // G_NV_NAME_RELEASED_H

9
src/nvidia/generated/g_objgpumon_nvoc.h
View File

@@ -42,6 +42,7 @@ extern "C" {
#include "gpu/gpu.h"
#include "gpu/eng_state.h"
#include "kernel/gpu/fifo/kernel_fifo.h"
#include "ctrl/ctrl2080/ctrl2080perf.h"
@@ -130,18 +131,18 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON**, Dynamic*, NvU32);
#define gpumonSetTunableState(pGpu, pEngstate, pTunableState) gpumonSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState)
#define gpumonConstructEngine(pGpu, pEngstate, arg0) gpumonConstructEngine_DISPATCH(pGpu, pEngstate, arg0)
#define gpumonIsPresent(pGpu, pEngstate) gpumonIsPresent_DISPATCH(pGpu, pEngstate)
void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3);
void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName);
#ifdef __nvoc_objgpumon_h_disabled
static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3) {
static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName) {
NV_ASSERT_FAILED_PRECOMP("OBJGPUMON was disabled!");
}
#else //__nvoc_objgpumon_h_disabled
#define gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, arg0, arg1, arg2, arg3)
#define gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName)
#endif //__nvoc_objgpumon_h_disabled
#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3)
#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName)
static inline NV_STATUS gpumonReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) {
return pEngstate->__gpumonReconcileTunableState__(pGpu, pEngstate, pTunableState);

1
src/nvidia/generated/g_os_nvoc.h
View File

@@ -749,6 +749,7 @@ NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo,
NvU32 averageBandwidthKBPS,
NvU32 floorBandwidthKBPS);
NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid);
NvBool osIsAdministrator(void);
NvBool osAllowPriorityOverride(void);
NV_STATUS osGetCurrentTime(NvU32 *pSec,NvU32 *puSec);

6
src/nvidia/generated/g_resserv_nvoc.h
View File

@@ -180,6 +180,12 @@ typedef void *PUID_TOKEN;
/// Internal Client handles start at this base value
#define RS_CLIENT_INTERNAL_HANDLE_BASE 0xC1E00000
/// VF Client handles start at this base value
#define RS_CLIENT_VF_HANDLE_BASE 0xE0000000
/// Get the VF client handle range for gfid
#define RS_CLIENT_GET_VF_HANDLE_BASE(gfid) (RS_CLIENT_VF_HANDLE_BASE + ((gfid) - 1) * RS_CLIENT_HANDLE_MAX)
//
// Print a warning if any client's resource count exceeds this
// threshold. Unless this was intentional, this is likely a client bug.

35
src/nvidia/generated/g_rpc-structures.h
View File

@@ -431,6 +431,13 @@ typedef struct rpc_perf_bridgeless_info_update_v17_00
typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v;
typedef struct rpc_nvlink_fault_up_v17_00
{
NvU32 linkId;
} rpc_nvlink_fault_up_v17_00;
typedef rpc_nvlink_fault_up_v17_00 rpc_nvlink_fault_up_v;
typedef struct rpc_nvlink_inband_received_data_256_v17_00
{
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 params;
@@ -1911,6 +1918,25 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = {
};
#endif
#ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00[] = {
{
.vtype = vtype_NvU32,
.offset = NV_OFFSETOF(rpc_nvlink_fault_up_v17_00, linkId),
.name = "linkId"
},
{
.vtype = vt_end
}
};
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00 = {
.name = "rpc_nvlink_fault_up",
.header_length = NV_SIZEOF32(rpc_nvlink_fault_up_v17_00),
.fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00
};
#endif
#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[] = {
{
@@ -2450,6 +2476,13 @@ vmiopd_mdesc_t *rpcdebugPerfBridgelessInfoUpdate_v17_00(void)
}
#endif
#ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00
vmiopd_mdesc_t *rpcdebugNvlinkFaultUp_v17_00(void)
{
return &vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00;
}
#endif
#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00
vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData256_v17_00(void)
{
@@ -2603,6 +2636,8 @@ typedef union rpc_generic_union {
rpc_perf_gpu_boost_sync_limits_callback_v perf_gpu_boost_sync_limits_callback_v;
rpc_perf_bridgeless_info_update_v17_00 perf_bridgeless_info_update_v17_00;
rpc_perf_bridgeless_info_update_v perf_bridgeless_info_update_v;
rpc_nvlink_fault_up_v17_00 nvlink_fault_up_v17_00;
rpc_nvlink_fault_up_v nvlink_fault_up_v;
rpc_nvlink_inband_received_data_256_v17_00 nvlink_inband_received_data_256_v17_00;
rpc_nvlink_inband_received_data_256_v nvlink_inband_received_data_256_v;
rpc_nvlink_inband_received_data_512_v17_00 nvlink_inband_received_data_512_v17_00;

9
src/nvidia/generated/g_rs_server_nvoc.h
View File

@@ -491,6 +491,15 @@ NvBool serverShareIterNext(RS_SHARE_ITERATOR*);
NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase);
/**
* Return an available client handle for new client allocation
*
* @param[in] pServer This server instance
* @param[in] bInternalHandle Client is an RM internal client
* @param[in] pSecInfo Security context of this client allocation
*/
extern NvU32 serverAllocClientHandleBase(RsServer *pServer, NvBool bInternalHandle, API_SECURITY_INFO *pSecInfo);
/**
* Allocate a resource. Assumes top-level lock has been taken.
*

2
src/nvidia/generated/g_sdk-structures.h
View File

@@ -409,7 +409,7 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08
{
NvU8 chipletType;
NvU8 chipletIndex;
NvU8 numCredits;
NvU16 numCredits;
} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08;
typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v;

115
src/nvidia/generated/g_subdevice_nvoc.c
View File

@@ -6545,6 +6545,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
#endif
},
{ /* [421] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPostFaultUp_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u)
/*flags=*/ 0x200u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803042u,
/*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "subdeviceCtrlCmdNvlinkPostFaultUp"
#endif
},
{ /* [422] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6559,7 +6574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage"
#endif
},
{ /* [422] */
{ /* [423] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6574,7 +6589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch"
#endif
},
{ /* [423] */
{ /* [424] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6589,7 +6604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo"
#endif
},
{ /* [424] */
{ /* [425] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6604,7 +6619,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet"
#endif
},
{ /* [425] */
{ /* [426] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6619,7 +6634,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet"
#endif
},
{ /* [426] */
{ /* [427] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6634,7 +6649,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo"
#endif
},
{ /* [427] */
{ /* [428] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6649,7 +6664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize"
#endif
},
{ /* [428] */
{ /* [429] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6664,7 +6679,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters"
#endif
},
{ /* [429] */
{ /* [430] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6679,13 +6694,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaRange"
#endif
},
{ /* [430] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u)
{ /* [431] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlaSetupInstanceMemBlock_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u)
/*flags=*/ 0x2204u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
/*flags=*/ 0x102204u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803502u,
/*paramSize=*/ sizeof(NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS),
@@ -6694,13 +6709,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock"
#endif
},
{ /* [431] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
{ /* [432] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlaGetRange_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
/*flags=*/ 0x4u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u)
/*flags=*/ 0x100004u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803503u,
/*paramSize=*/ sizeof(NV2080_CTRL_FLA_GET_RANGE_PARAMS),
@@ -6709,7 +6724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaGetRange"
#endif
},
{ /* [432] */
{ /* [433] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6724,7 +6739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats"
#endif
},
{ /* [433] */
{ /* [434] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6739,7 +6754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGspGetFeatures"
#endif
},
{ /* [434] */
{ /* [435] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6754,7 +6769,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo"
#endif
},
{ /* [435] */
{ /* [436] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6769,7 +6784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt"
#endif
},
{ /* [436] */
{ /* [437] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6784,7 +6799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff"
#endif
},
{ /* [437] */
{ /* [438] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6799,7 +6814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower"
#endif
},
{ /* [438] */
{ /* [439] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6814,7 +6829,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus"
#endif
},
{ /* [439] */
{ /* [440] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6829,7 +6844,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus"
#endif
},
{ /* [440] */
{ /* [441] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6844,7 +6859,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask"
#endif
},
{ /* [441] */
{ /* [442] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6859,7 +6874,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask"
#endif
},
{ /* [442] */
{ /* [443] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6874,7 +6889,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType"
#endif
},
{ /* [443] */
{ /* [444] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6889,7 +6904,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu"
#endif
},
{ /* [444] */
{ /* [445] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6904,7 +6919,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo"
#endif
},
{ /* [445] */
{ /* [446] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6919,7 +6934,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage"
#endif
},
{ /* [446] */
{ /* [447] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6934,7 +6949,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity"
#endif
},
{ /* [447] */
{ /* [448] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6949,7 +6964,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources"
#endif
},
{ /* [448] */
{ /* [449] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6964,7 +6979,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding"
#endif
},
{ /* [449] */
{ /* [450] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6979,7 +6994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport"
#endif
},
{ /* [450] */
{ /* [451] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -6994,7 +7009,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig"
#endif
},
{ /* [451] */
{ /* [452] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -7009,7 +7024,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask"
#endif
},
{ /* [452] */
{ /* [453] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -7029,7 +7044,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice =
{
/*numEntries=*/ 453,
/*numEntries=*/ 454,
/*pExportEntries=*/ __nvoc_exported_method_def_Subdevice
};
@@ -7465,6 +7480,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
pThis->__subdeviceCtrlCmdNvlinkInbandSendData__ = &subdeviceCtrlCmdNvlinkInbandSendData_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u)
pThis->__subdeviceCtrlCmdNvlinkPostFaultUp__ = &subdeviceCtrlCmdNvlinkPostFaultUp_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u)
pThis->__subdeviceCtrlCmdNvlinkEomControl__ = &subdeviceCtrlCmdNvlinkEomControl_IMPL;
#endif
@@ -8136,10 +8155,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
pThis->__subdeviceCtrlCmdGpuQueryComputeModeRules__ = &subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
pThis->__subdeviceCtrlCmdGpuAcquireComputeModeReservation__ = &subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL;
#endif
}
static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
@@ -8150,6 +8165,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
pThis->__subdeviceCtrlCmdGpuAcquireComputeModeReservation__ = &subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
pThis->__subdeviceCtrlCmdGpuReleaseComputeModeReservation__ = &subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL;
#endif
@@ -8402,10 +8421,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
pThis->__subdeviceCtrlCmdCeGetCaps__ = &subdeviceCtrlCmdCeGetCaps_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u)
pThis->__subdeviceCtrlCmdCeGetAllCaps__ = &subdeviceCtrlCmdCeGetAllCaps_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u)
pThis->__subdeviceCtrlCmdCeGetCePceMask__ = &subdeviceCtrlCmdCeGetCePceMask_IMPL;
#endif
@@ -8418,6 +8433,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
pThis->__subdeviceCtrlCmdCeGetCapsV2__ = &subdeviceCtrlCmdCeGetCapsV2_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u)
pThis->__subdeviceCtrlCmdCeGetAllCaps__ = &subdeviceCtrlCmdCeGetAllCaps_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
pThis->__subdeviceCtrlCmdFlcnGetDmemUsage__ = &subdeviceCtrlCmdFlcnGetDmemUsage_IMPL;
#endif
@@ -8466,11 +8485,11 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
pThis->__subdeviceCtrlCmdFlaRange__ = &subdeviceCtrlCmdFlaRange_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
pThis->__subdeviceCtrlCmdFlaSetupInstanceMemBlock__ = &subdeviceCtrlCmdFlaSetupInstanceMemBlock_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u)
pThis->__subdeviceCtrlCmdFlaGetRange__ = &subdeviceCtrlCmdFlaGetRange_IMPL;
#endif

24
src/nvidia/generated/g_subdevice_nvoc.h
View File

@@ -213,6 +213,7 @@ struct Subdevice {
NV_STATUS (*__subdeviceCtrlCmdNvlinkEnableLinks__)(struct Subdevice *);
NV_STATUS (*__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__)(struct Subdevice *, NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdNvlinkInbandSendData__)(struct Subdevice *, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdNvlinkPostFaultUp__)(struct Subdevice *, NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdNvlinkEomControl__)(struct Subdevice *, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdNvlinkL1Threshold__)(struct Subdevice *, NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdNvlinkDirectConnectCheck__)(struct Subdevice *, NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS *);
@@ -443,10 +444,10 @@ struct Subdevice {
NV_STATUS (*__subdeviceCtrlCmdLpwrDifrPrefetchResponse__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdLpwrDifrCtrl__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdCeGetCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdCeGetAllCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdCeGetCePceMask__)(struct Subdevice *, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdCeUpdatePceLceMappings__)(struct Subdevice *, NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdCeGetCapsV2__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdCeGetAllCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdFlcnGetDmemUsage__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdFlcnGetEngineArch__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdFlcnUstreamerQueueInfo__)(struct Subdevice *, NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS *);
@@ -752,6 +753,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
#define subdeviceCtrlCmdNvlinkEnableLinks(pSubdevice) subdeviceCtrlCmdNvlinkEnableLinks_DISPATCH(pSubdevice)
#define subdeviceCtrlCmdNvlinkProcessInitDisabledLinks(pSubdevice, pParams) subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdNvlinkInbandSendData(pSubdevice, pParams) subdeviceCtrlCmdNvlinkInbandSendData_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdNvlinkPostFaultUp(pSubdevice, pParams) subdeviceCtrlCmdNvlinkPostFaultUp_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdNvlinkEomControl(pSubdevice, pParams) subdeviceCtrlCmdNvlinkEomControl_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdNvlinkL1Threshold(pSubdevice, pParams) subdeviceCtrlCmdNvlinkL1Threshold_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdNvlinkDirectConnectCheck(pSubdevice, pParams) subdeviceCtrlCmdNvlinkDirectConnectCheck_DISPATCH(pSubdevice, pParams)
@@ -986,10 +988,10 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
#define subdeviceCtrlCmdLpwrDifrPrefetchResponse(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrPrefetchResponse_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdLpwrDifrCtrl(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrCtrl_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdCeGetCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCaps_DISPATCH(pSubdevice, pCeCapsParams)
#define subdeviceCtrlCmdCeGetAllCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllCaps_DISPATCH(pSubdevice, pCeCapsParams)
#define subdeviceCtrlCmdCeGetCePceMask(pSubdevice, pCePceMaskParams) subdeviceCtrlCmdCeGetCePceMask_DISPATCH(pSubdevice, pCePceMaskParams)
#define subdeviceCtrlCmdCeUpdatePceLceMappings(pSubdevice, pCeUpdatePceLceMappingsParams) subdeviceCtrlCmdCeUpdatePceLceMappings_DISPATCH(pSubdevice, pCeUpdatePceLceMappingsParams)
#define subdeviceCtrlCmdCeGetCapsV2(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCapsV2_DISPATCH(pSubdevice, pCeCapsParams)
#define subdeviceCtrlCmdCeGetAllCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllCaps_DISPATCH(pSubdevice, pCeCapsParams)
#define subdeviceCtrlCmdFlcnGetDmemUsage(pSubdevice, pFlcnDmemUsageParams) subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(pSubdevice, pFlcnDmemUsageParams)
#define subdeviceCtrlCmdFlcnGetEngineArch(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetEngineArch_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdFlcnUstreamerQueueInfo(pSubdevice, pParams) subdeviceCtrlCmdFlcnUstreamerQueueInfo_DISPATCH(pSubdevice, pParams)
@@ -1722,6 +1724,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkInbandSendData_DISPATCH(struct Sub
return pSubdevice->__subdeviceCtrlCmdNvlinkInbandSendData__(pSubdevice, pParams);
}
NV_STATUS subdeviceCtrlCmdNvlinkPostFaultUp_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS *pParams);
static inline NV_STATUS subdeviceCtrlCmdNvlinkPostFaultUp_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS *pParams) {
return pSubdevice->__subdeviceCtrlCmdNvlinkPostFaultUp__(pSubdevice, pParams);
}
NV_STATUS subdeviceCtrlCmdNvlinkEomControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams);
static inline NV_STATUS subdeviceCtrlCmdNvlinkEomControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams) {
@@ -3104,12 +3112,6 @@ static inline NV_STATUS subdeviceCtrlCmdCeGetCaps_DISPATCH(struct Subdevice *pSu
return pSubdevice->__subdeviceCtrlCmdCeGetCaps__(pSubdevice, pCeCapsParams);
}
NV_STATUS subdeviceCtrlCmdCeGetAllCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams);
static inline NV_STATUS subdeviceCtrlCmdCeGetAllCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams) {
return pSubdevice->__subdeviceCtrlCmdCeGetAllCaps__(pSubdevice, pCeCapsParams);
}
NV_STATUS subdeviceCtrlCmdCeGetCePceMask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pCePceMaskParams);
static inline NV_STATUS subdeviceCtrlCmdCeGetCePceMask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pCePceMaskParams) {
@@ -3128,6 +3130,12 @@ static inline NV_STATUS subdeviceCtrlCmdCeGetCapsV2_DISPATCH(struct Subdevice *p
return pSubdevice->__subdeviceCtrlCmdCeGetCapsV2__(pSubdevice, pCeCapsParams);
}
NV_STATUS subdeviceCtrlCmdCeGetAllCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams);
static inline NV_STATUS subdeviceCtrlCmdCeGetAllCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams) {
return pSubdevice->__subdeviceCtrlCmdCeGetAllCaps__(pSubdevice, pCeCapsParams);
}
NV_STATUS subdeviceCtrlCmdFlcnGetDmemUsage_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *pFlcnDmemUsageParams);
static inline NV_STATUS subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *pFlcnDmemUsageParams) {

1
src/nvidia/generated/rmconfig.h
View File

@@ -242,6 +242,7 @@
#define RMCFG_FEATURE_RMCORE_BASE 1 // RMCORE Base
#define RMCFG_FEATURE_KERNEL_RM 1 // Kernel layer of RM
#define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin
#define RMCFG_FEATURE_VGPU_GSP_PLUGIN_OFFLOAD 1 // vGPU GSP plugin offload
#define RMCFG_FEATURE_LIBOS_3_X 1 // Enable Libos-3.x feature
#define RMCFG_FEATURE_NOTEBOOK 1 // Notebook support
#define RMCFG_FEATURE_EXTDEV 1 // Daughter boards connected to Quadro GPUs