595.58.03

kernel-open/nvidia/nv-mmap.c

@@ -957,15 +957,22 @@ void NV_API_CALL nv_set_safe_to_mmap_locked(
 }
 
 #if !NV_CAN_CALL_VMA_START_WRITE
+
+#if defined(VM_REFCNT_EXCLUDE_READERS_FLAG)
+#define NV_VMA_LOCK_OFFSET VM_REFCNT_EXCLUDE_READERS_FLAG
+#else
+#define NV_VMA_LOCK_OFFSET VMA_LOCK_OFFSET
+#endif
+
 static NvBool nv_vma_enter_locked(struct vm_area_struct *vma, NvBool detaching)
 {
-    NvU32 tgt_refcnt = VMA_LOCK_OFFSET;
+    NvU32 tgt_refcnt = NV_VMA_LOCK_OFFSET;
     NvBool interrupted = NV_FALSE;
     if (!detaching)
     {
         tgt_refcnt++;
     }
-    if (!refcount_add_not_zero(VMA_LOCK_OFFSET, &vma->vm_refcnt))
+    if (!refcount_add_not_zero(NV_VMA_LOCK_OFFSET, &vma->vm_refcnt))
     {
         return NV_FALSE;
     }
@@ -995,7 +1002,7 @@ static NvBool nv_vma_enter_locked(struct vm_area_struct *vma, NvBool detaching)
     if (interrupted)
     {
         // Clean up on error: release refcount and dep_map
-        refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
+        refcount_sub_and_test(NV_VMA_LOCK_OFFSET, &vma->vm_refcnt);
         rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
         return NV_FALSE;
     }
@@ -1011,7 +1018,7 @@ void nv_vma_start_write(struct vm_area_struct *vma)
 {
     NvU32 mm_lock_seq;
     NvBool locked;
-    if (__is_vma_write_locked(vma, &mm_lock_seq))
+    if (nv_is_vma_write_locked(vma, &mm_lock_seq))
         return;
 
     locked = nv_vma_enter_locked(vma, NV_FALSE);
@@ -1020,7 +1027,7 @@ void nv_vma_start_write(struct vm_area_struct *vma)
     if (locked)
     {
         NvBool detached;
-        detached = refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
+        detached = refcount_sub_and_test(NV_VMA_LOCK_OFFSET, &vma->vm_refcnt);
         rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
         WARN_ON_ONCE(detached);
     }

kernel-open/nvidia/nv-platform.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -497,26 +497,6 @@ NV_STATUS NV_API_CALL nv_soc_device_reset(nv_state_t *nv)
                 goto out;
             }
         }
-
-        if (nvl->hdacodec_reset != NULL)
-        {
-            /*
-             * HDACODEC reset control is shared between display driver and audio driver.
-             * Since reset_control_reset toggles the reset signal, we prefer to use
-             * reset_control_deassert. Additionally, since Audio driver uses
-             * reset_control_bulk_deassert() which internally calls reset_control_deassert,
-             * we must use reset_control_deassert, because consumers must not use
-             * reset_control_reset on shared reset lines when reset_control_deassert has
-             * been used.
-             */
-            rc = reset_control_deassert(nvl->hdacodec_reset);
-            if (rc != 0)
-            {
-                status = NV_ERR_GENERIC;
-                nv_printf(NV_DBG_ERRORS, "NVRM: hdacodec reset_control_deassert failed, rc: %d\n", rc);
-                goto out;
-            }
-        }
     }
 out:
     return status;
@@ -1078,26 +1058,6 @@ static int nv_platform_device_display_probe(struct platform_device *plat_dev)
             nv_printf(NV_DBG_ERRORS, "NVRM: mipi_cal devm_reset_control_get failed, err: %ld\n",  PTR_ERR(nvl->mipi_cal_reset));
             nvl->mipi_cal_reset = NULL;
         }
-
-        /*
-         * In T23x, HDACODEC is part of the same power domain as NVDisplay, so
-         * unpowergating the DISP domain also results in the HDACODEC reset
-         * being de-asserted. However, in T26x, HDACODEC is being moved
-         * out to a separate always-on domain, so we need to explicitly de-assert
-         * the HDACODEC reset in RM. We don't have good way to differentiate
-         * between T23x vs T264x at this place. So if there is failure to read
-         * "hdacodec_reset" from DT silently ignore it for now. In long term we
-         * should really look into using the devm_reset_control_bulk* APIs and
-         * see if this is feasible if we're ultimately just getting and
-         * asserting/deasserting all of the resets specified in DT together all of
-         * the time, and if there's no scenarios in which we need to only use a 
-         * specific set of reset(s) at a given point.
-         */
-        nvl->hdacodec_reset = devm_reset_control_get(nvl->dev, "hdacodec_reset");
-        if (IS_ERR(nvl->hdacodec_reset))
-        {
-            nvl->hdacodec_reset = NULL;
-        }
     }
 
     status = nv_imp_icc_get(nv);

kernel-open/nvidia/nvidia.Kbuild

@@ -226,6 +226,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += has_enum_pidtype_tgid
 NV_CONFTEST_TYPE_COMPILE_TESTS += bpmp_mrq_has_strap_set
 NV_CONFTEST_TYPE_COMPILE_TESTS += register_shrinker_has_format_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += pci_resize_resource_has_exclude_bars_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += is_vma_write_locked_has_mm_lock_seq_arg
 
 NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present
 NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build