580.94.06

kernel-open/nvidia-uvm/uvm_ats_sva.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2018-2023 NVIDIA Corporation
+    Copyright (c) 2018-2025 NVIDIA Corporation
 
     Permission is hereby granted, free of charge, to any person obtaining a copy
     of this software and associated documentation files (the "Software"), to
@@ -43,8 +43,11 @@
 // commit cb4789b0d19ff231ce9f73376a023341300aed96 (11/23/2020). Commit
 // 701fac40384f07197b106136012804c3cae0b3de (02/15/2022) removed ioasid_get()
 // and added mm_pasid_drop().
+//
+// CONFIG_IOMMU_SVA_LIB was renamed to CONFIG_IOMMU_SVA with commit 7ba5647
+// (02/07/2022).
     #if UVM_CAN_USE_MMU_NOTIFIERS() && (defined(NV_IOASID_GET_PRESENT) || defined(NV_MM_PASID_DROP_PRESENT))
-        #if defined(CONFIG_IOMMU_SVA)
+        #if defined(CONFIG_IOMMU_SVA) || defined(CONFIG_IOMMU_SVA_LIB)
             #define UVM_ATS_SVA_SUPPORTED() 1
         #else
             #define UVM_ATS_SVA_SUPPORTED() 0

kernel-open/nvidia-uvm/uvm_get_rm_ptes_test.c

@@ -144,10 +144,13 @@ static NV_STATUS verify_mapping_info(uvm_va_space_t *va_space,
 
     phys_offset = mapping_offset;
 
-    // Add the physical offset for nvswitch connected peer mappings
-    if (uvm_aperture_is_peer(aperture) &&
-        uvm_parent_gpus_are_nvswitch_connected(memory_mapping_gpu->parent, memory_owning_gpu->parent))
-        phys_offset += memory_owning_gpu->parent->nvswitch_info.fabric_memory_window_start;
+    // Add the physical offset for peer mappings
+    if (uvm_aperture_is_peer(aperture)) {
+        if (uvm_parent_gpus_are_direct_connected(memory_mapping_gpu->parent, memory_owning_gpu->parent))
+            phys_offset += memory_owning_gpu->parent->peer_address_info.peer_gpa_memory_window_start;
+        else if (uvm_parent_gpus_are_nvswitch_connected(memory_mapping_gpu->parent, memory_owning_gpu->parent))
+            phys_offset += memory_owning_gpu->parent->nvswitch_info.fabric_memory_window_start;
+    }
 
     for (index = 0; index < ext_mapping_info->numWrittenPtes; index++) {
 

kernel-open/nvidia-uvm/uvm_gpu.c

@@ -107,6 +107,7 @@ static void fill_parent_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo
     }
 
     parent_gpu->nvswitch_info.is_nvswitch_connected = gpu_info->connectedToSwitch;
+    parent_gpu->peer_address_info.is_direct_connected = gpu_info->nvlDirectConnect;
 
     // nvswitch is routed via physical pages, where the upper 13-bits of the
     // 47-bit address space holds the routing information for each peer.
@@ -115,6 +116,9 @@ static void fill_parent_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo
         parent_gpu->nvswitch_info.fabric_memory_window_start = gpu_info->nvswitchMemoryWindowStart;
         parent_gpu->nvswitch_info.egm_fabric_memory_window_start = gpu_info->nvswitchEgmMemoryWindowStart;
     }
+    else if (parent_gpu->peer_address_info.is_direct_connected) {
+        parent_gpu->peer_address_info.peer_gpa_memory_window_start = gpu_info->nvlDirectConnectMemoryWindowStart;
+    }
 
     parent_gpu->ats.non_pasid_ats_enabled = gpu_info->nonPasidAtsSupport;
 
@@ -2110,6 +2114,16 @@ bool uvm_parent_gpus_are_nvswitch_connected(const uvm_parent_gpu_t *parent_gpu0,
     return false;
 }
 
+bool uvm_parent_gpus_are_direct_connected(const uvm_parent_gpu_t *parent_gpu0, const uvm_parent_gpu_t *parent_gpu1)
+{
+    if (parent_gpu0 != parent_gpu1 &&
+        parent_gpu0->peer_address_info.is_direct_connected &&
+        parent_gpu1->peer_address_info.is_direct_connected)
+        return true;
+
+    return false;
+}
+
 NV_STATUS uvm_gpu_check_ecc_error_no_rm(uvm_gpu_t *gpu)
 {
     // We may need to call service_interrupts() which cannot be done in the top
@@ -3068,7 +3082,9 @@ uvm_gpu_phys_address_t uvm_gpu_peer_phys_address(uvm_gpu_t *owning_gpu, NvU64 ad
 {
     uvm_aperture_t aperture = uvm_gpu_peer_aperture(accessing_gpu, owning_gpu);
 
-    if (uvm_parent_gpus_are_nvswitch_connected(accessing_gpu->parent, owning_gpu->parent))
+    if (uvm_parent_gpus_are_direct_connected(accessing_gpu->parent, owning_gpu->parent))
+        address += owning_gpu->parent->peer_address_info.peer_gpa_memory_window_start;
+    else if (uvm_parent_gpus_are_nvswitch_connected(accessing_gpu->parent, owning_gpu->parent))
         address += owning_gpu->parent->nvswitch_info.fabric_memory_window_start;
 
     return uvm_gpu_phys_address(aperture, address);

kernel-open/nvidia-uvm/uvm_gpu.h

@@ -1365,6 +1365,20 @@ struct uvm_parent_gpu_struct
         NvU64 base_address;
     } egm;
 
+    // Peer VIDMEM base offset used when creating GPA PTEs for
+    // peer mappings. RM will set this offset on systems where
+    // peer accesses are not zero-based (NVLINK 5+).
+    struct
+    {
+        // Is the GPU directly connected to peer GPUs.
+        bool is_direct_connected;
+
+        // 48-bit fabric memory physical offset that peer gpus need in order
+        // access to be rounted to the correct peer.
+        // Each memory window is 4TB, so the upper 6 bits are used for rounting.
+        NvU64 peer_gpa_memory_window_start;
+    } peer_address_info;
+
     uvm_test_parent_gpu_inject_error_t test;
 
     // PASID ATS
@@ -1619,6 +1633,8 @@ uvm_aperture_t uvm_gpu_egm_peer_aperture(uvm_parent_gpu_t *local_gpu, uvm_parent
 
 bool uvm_parent_gpus_are_nvswitch_connected(const uvm_parent_gpu_t *parent_gpu0, const uvm_parent_gpu_t *parent_gpu1);
 
+bool uvm_parent_gpus_are_direct_connected(const uvm_parent_gpu_t *parent_gpu0, const uvm_parent_gpu_t *parent_gpu1);
+
 static bool uvm_gpus_are_smc_peers(const uvm_gpu_t *gpu0, const uvm_gpu_t *gpu1)
 {
     UVM_ASSERT(gpu0 != gpu1);