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russellcnv
2025-10-27 13:41:40 -07:00
parent 1babfa3dab
commit e2dbb3d99c
74 changed files with 55029 additions and 53585 deletions
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16
kernel-open/nvidia-uvm/uvm_gpu.h
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@@ -1365,6 +1365,20 @@ struct uvm_parent_gpu_struct
NvU64 base_address;
} egm;
// Peer VIDMEM base offset used when creating GPA PTEs for
// peer mappings. RM will set this offset on systems where
// peer accesses are not zero-based (NVLINK 5+).
struct
{
// Is the GPU directly connected to peer GPUs.
bool is_direct_connected;
// 48-bit fabric memory physical offset that peer gpus need in order
// access to be rounted to the correct peer.
// Each memory window is 4TB, so the upper 6 bits are used for rounting.
NvU64 peer_gpa_memory_window_start;
} peer_address_info;
uvm_test_parent_gpu_inject_error_t test;
// PASID ATS
@@ -1619,6 +1633,8 @@ uvm_aperture_t uvm_gpu_egm_peer_aperture(uvm_parent_gpu_t *local_gpu, uvm_parent
bool uvm_parent_gpus_are_nvswitch_connected(const uvm_parent_gpu_t *parent_gpu0, const uvm_parent_gpu_t *parent_gpu1);
bool uvm_parent_gpus_are_direct_connected(const uvm_parent_gpu_t *parent_gpu0, const uvm_parent_gpu_t *parent_gpu1);
static bool uvm_gpus_are_smc_peers(const uvm_gpu_t *gpu0, const uvm_gpu_t *gpu1)
{
UVM_ASSERT(gpu0 != gpu1);