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580.94.06

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This commit is contained in:
russellcnv
2025-10-27 13:41:40 -07:00
parent 1babfa3dab
commit e2dbb3d99c
74 changed files with 55029 additions and 53585 deletions
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6
src/common/displayport/inc/dp_connectorimpl.h
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@@ -265,6 +265,12 @@ namespace DisplayPort
//
bool bHDMIOnDPPlusPlus;
//
// Flag to enable accounting available DP tunnelling BW while generating PPS
// for the mode
//
bool bOptimizeDscBppForTunnellingBw;
bool bSkipResetLinkStateDuringPlug;
// Flag to check if LT should be skipped.

4
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -106,6 +106,9 @@
// This regkey ensures DPLib takes into account Displayport++ supports HDMI.
#define NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS "HDMI_ON_DP_PLUS_PLUS"
// This regkey ensures DP IMP takes DP tunnelling BW into account while calculating DSC BPP
#define NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW "OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW"
#define NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC "DP_IGNORE_CAPS_AND_FORCE_HIGHEST_LC_WAR"
//
@@ -153,6 +156,7 @@ struct DP_REGKEY_DATABASE
bool bEnableDevId;
bool bHDMIOnDPPlusPlus;
bool bIgnoreCapsAndForceHighestLc;
bool bOptimizeDscBppForTunnellingBw;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

22
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -199,6 +199,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
this->bHDMIOnDPPlusPlus = dpRegkeyDatabase.bHDMIOnDPPlusPlus;
this->bOptimizeDscBppForTunnellingBw = dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -1201,12 +1202,14 @@ bool ConnectorImpl::compoundQueryAttachTunneling(const DpModesetParams &modesetP
}
NvU64 bpp = modesetParams.modesetInfo.depth;
NvU32 dscFactor = 1U;
if (pDscParams->bEnableDsc)
{
bpp = divide_ceil(pDscParams->bitsPerPixelX16, 16);
dscFactor = 16U;
}
NvU64 modeBwRequired = modesetParams.modesetInfo.pixelClockHz * bpp;
NvU64 modeBwRequired = (modesetParams.modesetInfo.pixelClockHz * bpp)/dscFactor;
NvU64 freeTunnelingBw = allocatedDpTunnelBw - compoundQueryUsedTunnelingBw;
if (modeBwRequired > freeTunnelingBw)
@@ -1895,6 +1898,15 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
availableBandwidthBitsPerSecond = lc.convertMinRateToDataRate() * 8 * lc.lanes;
if (this-> bOptimizeDscBppForTunnellingBw && hal->isDpTunnelBwAllocationEnabled())
{
NvU64 freeTunnelingBw = allocatedDpTunnelBw - compoundQueryUsedTunnelingBw;
if (freeTunnelingBw < availableBandwidthBitsPerSecond)
{
availableBandwidthBitsPerSecond = freeTunnelingBw;
}
}
warData.dpData.linkRateHz = lc.peakRate;
warData.dpData.bIs128b132bChannelCoding = lc.bIs128b132bChannelCoding;
warData.dpData.bDisableEffBppSST8b10b = this->bDisableEffBppSST8b10b;
@@ -1960,6 +1972,7 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
{
pDscParams->bEnableDsc = true;
result = true;
pDscParams->bitsPerPixelX16 = bitsPerPixelX16;
if (pDscParams->pDscOutParams != NULL)
{
@@ -1968,7 +1981,6 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
// possible with DSC and calculated PPS and bits per pixel.
//
dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
pDscParams->bitsPerPixelX16 = bitsPerPixelX16;
}
else
{
@@ -6793,7 +6805,9 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
// Some panels whose TCON erroneously sets DPCD 0x200 SINK_COUNT=0.
if (main->isEDP() && hal->getSinkCount() == 0)
{
hal->setSinkCount(1);
}
// disconnect all devices
for (ListElement * i = activeGroups.begin(); i != activeGroups.end(); i = i->next) {
@@ -7510,7 +7524,7 @@ void ConnectorImpl::notifyShortPulse()
bool ConnectorImpl::detectSinkCountChange()
{
if (this->linkUseMultistream())
if (this->linkUseMultistream() || main->isEDP())
return false;
DeviceImpl * existingDev = findDeviceInList(Address());

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -109,7 +109,8 @@ const struct
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS, &dpRegkeyDatabase.bHDMIOnDPPlusPlus, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW, &dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

44
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -125,7 +125,7 @@ void ConnectorImpl2x::applyOuiWARs()
bStuffDummySymbolsFor8b10b = true;
}
break;
}
}
@@ -513,16 +513,25 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
// LG
case 0xE430:
if (ProductID == 0x0469)
switch (ProductID)
{
//
// The LG display can't be driven at FHD with 2*RBR.
// Force max link config
//
this->WARFlags.forceMaxLinkConfig = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force maximum link config WAR required on LG panel.");
DP_PRINTF(DP_NOTICE, "DP-WAR> bug 1649626");
break;
case 0x0469:
{
//
// The LG display can't be driven at FHD with 2*RBR.
// Force max link config
//
this->WARFlags.forceMaxLinkConfig = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force maximum link config WAR required on LG panel.");
DP_PRINTF(DP_NOTICE, "DP-WAR> bug 1649626");
break;
}
case 0x06DB:
{
this->WARFlags.useLegacyAddress = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> LG eDP implements only Legacy interrupt address range");
break;
}
}
break;
case 0x8F34:
@@ -675,11 +684,18 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
}
break;
case 0xAC10:
if (ProductID == 0x42AD || ProductID == 0x42AC)
switch (ProductID)
{
this->WARFlags.bApplyStuffDummySymbolsWAR = true;
this->WARData.bStuffDummySymbolsFor128b132b = true;
this->WARData.bStuffDummySymbolsFor8b10b = false;
case 0x42AD:
case 0x42AC:
this->WARFlags.bApplyStuffDummySymbolsWAR = true;
this->WARData.bStuffDummySymbolsFor128b132b = true;
this->WARData.bStuffDummySymbolsFor8b10b = false;
break;
case 0xA21F:
this->WARFlags.bForceHeadShutdown = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown for Dell AW2524H.");
break;
}
break;
default:

16
src/common/inc/nvBldVer.h
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@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/VK580_65-179"
#define NV_BUILD_CHANGELIST_NUM (36666396)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/VK580_65-182"
#define NV_BUILD_CHANGELIST_NUM (36741708)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/VK580_65-179"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36666396)
#define NV_BUILD_NAME "rel/gpu_drv/r580/VK580_65-182"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36741708)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "VK580_65-6"
#define NV_BUILD_CHANGELIST_NUM (36666396)
#define NV_BUILD_BRANCH_VERSION "VK580_65-9"
#define NV_BUILD_CHANGELIST_NUM (36741708)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "581.58"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36666396)
#define NV_BUILD_NAME "581.71"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36741708)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.94.03"
#define NV_VERSION_STRING "580.94.06"
#else

25
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -564,6 +564,31 @@ typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS {
/*
* NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT
*
* This command can be used to enable and set the engine
* context switch timeout
*
* timeout: Timeout in number of microsec PTIMER ticks
* 1 microsec PTIMER tick = 1024 PTIMER nanoseconds
* bEnable: TRUE/FALSE
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT (0x20801110) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS {
NvU32 timeout;
NvBool bEnable;
} NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
*

3
src/common/shared/inc/detect-self-hosted.h
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@@ -32,7 +32,8 @@ static inline int pci_devid_is_self_hosted_hopper(unsigned short devid)
static inline int pci_devid_is_self_hosted_blackwell(unsigned short devid)
{
return (devid >= 0x2940 && devid <= 0x297f) // GB100 Self-Hosted
|| (devid >= 0x31c0 && devid <= 0x31ff); // GB110 Self-Hosted
|| (devid >= 0x31c0 && devid <= 0x31ff) // GB110 Self-Hosted
|| (devid == 0x31a1); //
}
static inline int pci_devid_is_self_hosted(unsigned short devid)

19
src/common/shared/inc/g_vgpu_chip_flags.h
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@@ -621,6 +621,25 @@ ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
ENTRY(0x2238, 0x2208, 0x10de, "NVIDIA A10M-3B"),
ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),

8
src/common/shared/inc/g_vgpu_resman_specific.h
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@@ -17,6 +17,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B7, 0x1804, 0x20B7, 0x1532 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x230E, 0x20DF, 0x230E, 0x20DF },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -121,6 +122,13 @@ static const struct {
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1499}, // NVIDIA H20L-1-15CME
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1500}, // NVIDIA H20L-1-15C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1501}, // NVIDIA H20L-1-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1502}, // NVIDIA H20L-2-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1503}, // NVIDIA H20L-3-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1504}, // NVIDIA H20L-4-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1505}, // NVIDIA H20L-7-120C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C