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550.90.07

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This commit is contained in:
Bernhard Stoeckner
2024-06-04 13:48:03 +02:00
parent 083cd9cf17
commit e45d91de02
180 changed files with 43467 additions and 38127 deletions
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1
src/common/displayport/inc/dp_connectorimpl.h
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@@ -313,6 +313,7 @@ namespace DisplayPort
bool bDisableSSC;
bool bEnableFastLT;
NvU32 maxLinkRateFromRegkey;
bool bFlushTimeslotWhenDirty;
//
// Latency(ms) to apply between link-train and FEC enable for bug

9
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -74,14 +74,14 @@
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
//
// Bug 4426624: Flush timeslot change to HW when dirty bit is set.
#define NV_DP_REGKEY_FLUSH_TIMESLOT_INFO_WHEN_DIRTY "DP_BUG_4426624_WAR"
// Bug 4459839 : This regkey will enable DSC irrespective of LT status.
//
#define NV_DP_REGKEY_FORCE_DSC_ON_SINK "DP_FORCE_DSC_ON_SINK"
#define NV_DP_REGKEY_ENABLE_SKIP_DPCD_READS_WAR "DP_BUG_4478047_WAR"
@@ -121,6 +121,7 @@ struct DP_REGKEY_DATABASE
bool bMSTPCONCapsReadDisabled;
bool bForceDscOnSink;
bool bSkipFakeDeviceDpcdAccess;
bool bFlushTimeslotWhenDirty;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H