mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-19 22:44:19 +00:00
550.90.07
This commit is contained in:
Bernhard Stoeckner
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -57,13 +57,14 @@ typedef enum ROTATE_IV_TYPE {
|
||||
|
||||
// Status value written into NvNotification.Info16
|
||||
typedef enum KEY_ROTATION_STATUS {
|
||||
KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress
|
||||
KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation
|
||||
KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress
|
||||
KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels
|
||||
KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
|
||||
KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel.
|
||||
KEY_ROTATION_STATUS_MAX_COUNT = 6,
|
||||
KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress
|
||||
KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation
|
||||
KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress
|
||||
KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels
|
||||
KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
|
||||
KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel
|
||||
KEY_ROTATION_STATUS_PENDING_TIMER_SUSPENDED = 6, // Key rotation timer suspended waiting for kernel key rotation to complete
|
||||
KEY_ROTATION_STATUS_MAX_COUNT = 7,
|
||||
} KEY_ROTATION_STATUS;
|
||||
|
||||
typedef struct CC_AES_CRYPTOBUNDLE {
|
||||
|
||||
@@ -31,7 +31,7 @@ extern "C" {
|
||||
/*event values*/
|
||||
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
|
||||
#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1)
|
||||
#define NV0000_NOTIFIERS_VM_START (2)
|
||||
#define NV0000_NOTIFIERS_GPU_UNBIND_EVENT (2)
|
||||
#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3)
|
||||
#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4)
|
||||
#define NV0000_NOTIFIERS_MAXCOUNT (5)
|
||||
|
||||
@@ -77,6 +77,7 @@ typedef struct NVA084_ALLOC_PARAMETERS {
|
||||
NvHandle hPluginClient;
|
||||
NvU32 numGuestFbHandles;
|
||||
NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS];
|
||||
NvU8 vgpuDevName[VM_UUID_SIZE];
|
||||
NvHandle hPluginHeapMemory;
|
||||
NvHandle hMigRmHeapMemory;
|
||||
NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -36,24 +36,27 @@
|
||||
#include "ctrl/ctrla081.h"
|
||||
#include "class/cl0000.h"
|
||||
#include "nv_vgpu_types.h"
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_VGPU_GET_START_DATA
|
||||
* NV0000_CTRL_CMD_VGPU_CREATE_DEVICE
|
||||
*
|
||||
* This command gets data associated with NV0000_NOTIFIERS_VGPU_MGR_START to
|
||||
* start VGPU process.
|
||||
* This command informs RM to create a vGPU device on KVM.
|
||||
*
|
||||
* mdevUuid
|
||||
* This parameter gives mdev device UUID for which nvidia-vgpu-mgr should
|
||||
* init process.
|
||||
* vgpuName [IN]
|
||||
* This parameter provides the MDEV UUID or VF BDF depending on whether MDEV
|
||||
* or vfio-pci-core framework is used.
|
||||
*
|
||||
* qemuPid
|
||||
* This parameter specifies the QEMU process ID of the VM.
|
||||
*
|
||||
* gpuPciId
|
||||
* gpuPciId [IN]
|
||||
* This parameter provides gpuId of GPU on which vgpu device is created.
|
||||
*
|
||||
* configParams
|
||||
* This parameter specifies the configuration parameters for vGPU
|
||||
* gpuPciBdf
|
||||
* This parameter specifies the BDF of the VF. (Same as PF for non-sriov)
|
||||
*
|
||||
* vgpuTypeId [IN]
|
||||
* This parameter specifies the vGPU type ID for the device to be created.
|
||||
*
|
||||
* vgpuId [OUT]
|
||||
* This parameter returns the vgpu id allocated by RM for the device
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
@@ -62,17 +65,114 @@
|
||||
* NV_ERR_INVALID_CLIENT
|
||||
*
|
||||
*/
|
||||
#define NV0000_CTRL_CMD_VGPU_GET_START_DATA (0xc01) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID (0x1U)
|
||||
#define NV0000_CTRL_CMD_VGPU_CREATE_DEVICE (0xc02) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0000_CTRL_VGPU_GET_START_DATA_PARAMS {
|
||||
NvU8 mdevUuid[VM_UUID_SIZE];
|
||||
NvU8 configParams[1024];
|
||||
NvU32 qemuPid;
|
||||
#define NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID (0x2U)
|
||||
|
||||
typedef struct NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS {
|
||||
NvU8 vgpuName[VM_UUID_SIZE];
|
||||
NvU32 gpuPciId;
|
||||
NvU16 vgpuId;
|
||||
NvU32 gpuPciBdf;
|
||||
} NV0000_CTRL_VGPU_GET_START_DATA_PARAMS;
|
||||
NvU32 vgpuTypeId;
|
||||
NvU16 vgpuId;
|
||||
} NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_VGPU_GET_INSTANCES
|
||||
*
|
||||
* This command queries RM for available instances for a particular vGPU type ID
|
||||
* on KVM.
|
||||
*
|
||||
* gpuPciId [IN]
|
||||
* This parameter specifies gpuId of GPU on which vGPU instances are being
|
||||
* queried.
|
||||
*
|
||||
* gpuPciBdf [IN]
|
||||
* This parameter specifies the BDF of the VF. (Same as PF for non-sriov)
|
||||
*
|
||||
* numVgpuTypes [IN]
|
||||
* This parameter specifies the count of vgpuTypeIds supplied and the
|
||||
* count of availableInstances values to be returned.
|
||||
*
|
||||
* vgpuTypeIds [IN]
|
||||
* This parameter specifies a total of numVgpuTypes vGPU type IDs for which
|
||||
* the available instances are to be queried.
|
||||
*
|
||||
* availableInstances [OUT]
|
||||
* This parameter returns a total of numVgpuTypes available instances for
|
||||
* the respective vGPU type IDs supplied in vgpuTypeIds input parameter.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_EVENT
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
* NV_ERR_INVALID_CLIENT
|
||||
* NV_ERR_INVALID_STATE
|
||||
*
|
||||
*/
|
||||
|
||||
#define NV0000_CTRL_CMD_VGPU_GET_INSTANCES (0xc03) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID (0x3U)
|
||||
|
||||
typedef struct NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS {
|
||||
NvU32 gpuPciId;
|
||||
NvU32 gpuPciBdf;
|
||||
NvU32 numVgpuTypes;
|
||||
NvU32 vgpuTypeIds[NVA081_MAX_VGPU_TYPES_PER_PGPU];
|
||||
NvU32 availableInstances[NVA081_MAX_VGPU_TYPES_PER_PGPU];
|
||||
} NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS;
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_VGPU_DELETE_DEVICE
|
||||
*
|
||||
* This command informs RM to delete a vGPU device on KVM.
|
||||
*
|
||||
* vgpuName [IN]
|
||||
* This parameter provides the MDEV UUID or VF BDF depending on whether MDEV
|
||||
* or vfio-pci-core framework is used.
|
||||
*
|
||||
* vgpuId [IN]
|
||||
* This parameter provides the vgpu id allocated by RM for the device to be
|
||||
* deleted.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_EVENT
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
* NV_ERR_INVALID_CLIENT
|
||||
*
|
||||
*/
|
||||
|
||||
#define NV0000_CTRL_CMD_VGPU_DELETE_DEVICE (0xc04) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID (0x4U)
|
||||
|
||||
typedef struct NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS {
|
||||
NvU8 vgpuName[VM_UUID_SIZE];
|
||||
NvU16 vgpuId;
|
||||
} NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_VGPU_VFIO_UNREGISTER_STATUS
|
||||
*
|
||||
* This command informs RM the status vgpu-vfio unregister for a GPU.
|
||||
*
|
||||
* returnStatus [IN]
|
||||
* This parameter provides the status vgpu-vfio unregister operation.
|
||||
*
|
||||
* gpuPciId [IN]
|
||||
* This parameter provides the gpu id of the GPU
|
||||
*/
|
||||
|
||||
#define NV0000_CTRL_CMD_VGPU_VFIO_UNREGISTER_STATUS (0xc05) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS_MESSAGE_ID (0x5U)
|
||||
|
||||
typedef struct NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS {
|
||||
NvU32 returnStatus;
|
||||
NvU32 gpuId;
|
||||
} NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS;
|
||||
|
||||
/* _ctrl0000vgpu_h_ */
|
||||
|
||||
@@ -905,6 +905,34 @@ typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
|
||||
NvBool bEnableAfterKeyRotation;
|
||||
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2
|
||||
*
|
||||
* This command does the same thing as @ref NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION.
|
||||
* The difference is that it doesn't take a list of clients and instead all channels belong
|
||||
* to the client on which this control call is made.
|
||||
*
|
||||
* numChannels
|
||||
* The number of valid entries in hChannelList array.
|
||||
* hChannelList
|
||||
* An array of NvHandle listing the channel handles
|
||||
* to be stopped.
|
||||
* bEnableAfterKeyRotation
|
||||
* This determines if channel is enabled by RM after it completes key rotation.
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NVOS_INVALID_STATE
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 (0x2080111b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID (0x1BU)
|
||||
|
||||
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS {
|
||||
NvU32 numChannels;
|
||||
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
|
||||
NvBool bEnableAfterKeyRotation;
|
||||
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
@@ -3741,7 +3741,8 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {
|
||||
|
||||
@@ -34,6 +34,8 @@
|
||||
|
||||
/*************************** SPDM COMMANDS ************************************/
|
||||
|
||||
#include "cc_drv.h"
|
||||
|
||||
/*!
|
||||
* @brief SPDM Command Types
|
||||
*
|
||||
@@ -43,6 +45,7 @@
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
|
||||
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
|
||||
|
||||
|
||||
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
|
||||
@@ -114,6 +117,25 @@ typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
|
||||
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* HCC FIPS Self-test.
|
||||
*/
|
||||
#define CE_FIPS_SELF_TEST_DATA_SIZE 16
|
||||
#define CE_FIPS_SELF_TEST_AUTH_TAG_SIZE 16
|
||||
#define CE_FIPS_SELF_TEST_IV_SIZE 12
|
||||
|
||||
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST {
|
||||
NvU8 cmdType;
|
||||
NvU8 isEnc;
|
||||
CC_KMB kmb;
|
||||
NvU8 text[CE_FIPS_SELF_TEST_DATA_SIZE];
|
||||
NvU8 authTag[CE_FIPS_SELF_TEST_AUTH_TAG_SIZE];
|
||||
} RM_GSP_SPDM_CMD_FIPS_SELFTEST;
|
||||
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST *PRM_GSP_SPDM_CMD_FIPS_SELFTEST;
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
|
||||
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
|
||||
@@ -132,6 +154,9 @@ typedef union RM_GSP_SPDM_CMD {
|
||||
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
|
||||
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
|
||||
|
||||
|
||||
RM_GSP_SPDM_CMD_FIPS_SELFTEST ccFipsTest;
|
||||
|
||||
} RM_GSP_SPDM_CMD;
|
||||
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
|
||||
|
||||
@@ -149,6 +174,7 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
|
||||
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
|
||||
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
|
||||
#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
|
||||
#define RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST (0x6)
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -52,6 +52,10 @@
|
||||
#define NVA081_PGPU_METADATA_STRING_SIZE 256
|
||||
#define NVA081_EXTRA_PARAMETERS_SIZE 1024
|
||||
#define NVA081_PLACEMENT_ID_INVALID 0xFFFFU
|
||||
#define NVA081_CONFIG_PARAMS_MAX_LENGTH 1024
|
||||
|
||||
#define NVA081_MAX_BAR_REGION_COUNT 4
|
||||
#define NVA081_MAX_SPARSE_REGION_COUNT 5
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO
|
||||
@@ -430,45 +434,9 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS {
|
||||
|
||||
|
||||
/* valid event action values */
|
||||
#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
|
||||
#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
|
||||
#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START
|
||||
*
|
||||
* This command notifies the nvidia-vgpu-vfio module with start status.
|
||||
* It notifies whether start has been successful or not.
|
||||
*
|
||||
* mdevUuid
|
||||
* This parameter specifies the uuid of the mdev device for which start has
|
||||
* been called.
|
||||
* vmUuid
|
||||
* The UUID of VM for which vGPU has been created.
|
||||
* vmName
|
||||
* The name of VM for which vGPU has been created.
|
||||
* returnStatus
|
||||
* This parameter species whether the vGPU plugin is initialized or not.
|
||||
* it specifies the error code in case plugin initialization has failed
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
*/
|
||||
#define NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START (0xa0810107) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS
|
||||
* This structure represents information of plugin init status.
|
||||
*/
|
||||
#define NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID (0x7U)
|
||||
|
||||
typedef struct NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS {
|
||||
NvU8 mdevUuid[VM_UUID_SIZE];
|
||||
NvU8 vmUuid[VM_UUID_SIZE];
|
||||
NvU8 vmName[NVA081_VM_NAME_SIZE];
|
||||
NvU32 returnStatus;
|
||||
} NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS;
|
||||
#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
|
||||
#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
|
||||
#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO
|
||||
@@ -908,4 +876,102 @@ typedef struct NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS {
|
||||
NvBool state;
|
||||
} NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS;
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_SET_VM_NAME
|
||||
*
|
||||
* This command is to set VM name for KVM.
|
||||
*
|
||||
* vgpuName [IN]
|
||||
* This param provides the vGPU device name to RM.
|
||||
*
|
||||
* vmName [IN]
|
||||
* This param provides the VM name of the vGPU device attached.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
|
||||
#define NVA081_CTRL_CMD_VGPU_SET_VM_NAME (0xa0810120) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS_MESSAGE_ID (0x20U)
|
||||
|
||||
typedef struct NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS {
|
||||
NvU8 vgpuName[VM_UUID_SIZE];
|
||||
NvU8 vmName[NVA081_VM_NAME_SIZE];
|
||||
} NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS;
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_GET_BAR_INFO
|
||||
*
|
||||
* This command is to get the bar info for a vGPU.
|
||||
*
|
||||
* gpuPciId [IN]
|
||||
* This param specifies the PCI device ID of VF on which VM is running
|
||||
*
|
||||
* vgpuName [IN]
|
||||
* This param provides the vGPU device name to RM.
|
||||
*
|
||||
* configParams [IN]
|
||||
* This param provides the vGPU config params to RM
|
||||
*
|
||||
* barSizes [OUT]
|
||||
* This param provides the BAR size for each region index of the device
|
||||
*
|
||||
* sparseOffsets [OUT]
|
||||
* This param provides the offset of each sparse mmap region in BAR0
|
||||
*
|
||||
* sparseSizes [OUT]
|
||||
* This param provides the size of each sparse mmap region in BAR0
|
||||
*
|
||||
* sparseCount [OUT]
|
||||
* This param provides the number of sparse mmap regions in BAR0
|
||||
*
|
||||
* isBar064bit [OUT]
|
||||
* This param provides whether the BAR0 is 64bit of the vGPU device
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
|
||||
#define NVA081_CTRL_CMD_VGPU_GET_BAR_INFO (0xa0810121) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS_MESSAGE_ID (0x21U)
|
||||
|
||||
typedef struct NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS {
|
||||
NvU32 gpuPciId;
|
||||
NvU8 vgpuName[VM_UUID_SIZE];
|
||||
NvU8 configParams[NVA081_CONFIG_PARAMS_MAX_LENGTH];
|
||||
NV_DECLARE_ALIGNED(NvU64 barSizes[NVA081_MAX_BAR_REGION_COUNT], 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 sparseOffsets[NVA081_MAX_SPARSE_REGION_COUNT], 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 sparseSizes[NVA081_MAX_SPARSE_REGION_COUNT], 8);
|
||||
NvU32 sparseCount;
|
||||
NvBool isBar064bit;
|
||||
} NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS;
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH
|
||||
*
|
||||
* This command is to get the migration bandwidth of the physical GPU.
|
||||
*
|
||||
* migrationBandwidth [OUT]
|
||||
* This param specifies the migration bandwidth of GPU
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_REQUEST
|
||||
* NV_ERR_INVALID_STATE
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH (0xa0810122) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID (0x22U)
|
||||
|
||||
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS {
|
||||
NvU32 migrationBandwidth;
|
||||
} NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS;
|
||||
|
||||
/* _ctrlA081vgpuconfig_h_ */
|
||||
|
||||
@@ -245,7 +245,7 @@ typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS {
|
||||
*/
|
||||
#define SECURITY_POLICY_ATTACKER_ADVANTAGE_DEFAULT (60)
|
||||
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MIN (50)
|
||||
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (75)
|
||||
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (65)
|
||||
|
||||
#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY (0xc56f010d) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -387,5 +387,36 @@ typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS {
|
||||
NvU32 maxCeChannels;
|
||||
} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE
|
||||
* This control call returns if key rotation is enabled.
|
||||
*
|
||||
* hSubDevice: [IN]
|
||||
* subdevice handle for the GPU queried
|
||||
* keyRotationState: [OUT]
|
||||
* NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_* value
|
||||
*
|
||||
* Possible return values:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_INVALID_OBJECT_HANDLE
|
||||
* NV_ERR_INVALID_CLIENT
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
*/
|
||||
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE (0xcb33010c) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xC" */
|
||||
|
||||
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED 0 // key rotation is disabled
|
||||
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED 1 // key rotation enabled for kernel keys
|
||||
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED 2 // key rotation enabled for user keys
|
||||
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED 3 // key rotation enabled for both keys
|
||||
|
||||
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID (0xCU)
|
||||
|
||||
typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS {
|
||||
NvHandle hSubDevice;
|
||||
NvU32 keyRotationState;
|
||||
} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS;
|
||||
|
||||
/* _ctrlcb33_h_ */
|
||||
|
||||
|
||||
@@ -37,13 +37,11 @@ typedef enum _HYPERVISOR_TYPE
|
||||
OS_HYPERVISOR_UNKNOWN
|
||||
} HYPERVISOR_TYPE;
|
||||
|
||||
#define CMD_VGPU_VFIO_WAKE_WAIT_QUEUE 0
|
||||
#define CMD_VGPU_VFIO_INJECT_INTERRUPT 1
|
||||
#define CMD_VGPU_VFIO_REGISTER_MDEV 2
|
||||
#define CMD_VGPU_VFIO_PRESENT 3
|
||||
#define CMD_VFIO_PCI_CORE_PRESENT 4
|
||||
#define CMD_VFIO_WAKE_REMOVE_GPU 1
|
||||
#define CMD_VGPU_VFIO_PRESENT 2
|
||||
#define CMD_VFIO_PCI_CORE_PRESENT 3
|
||||
|
||||
#define MAX_VF_COUNT_PER_GPU 64
|
||||
#define MAX_VF_COUNT_PER_GPU 64
|
||||
|
||||
typedef enum _VGPU_TYPE_INFO
|
||||
{
|
||||
@@ -54,17 +52,11 @@ typedef enum _VGPU_TYPE_INFO
|
||||
|
||||
typedef struct
|
||||
{
|
||||
void *vgpuVfioRef;
|
||||
void *waitQueue;
|
||||
void *nv;
|
||||
NvU32 *vgpuTypeIds;
|
||||
NvU8 **vgpuNames;
|
||||
NvU32 numVgpuTypes;
|
||||
NvU32 domain;
|
||||
NvU8 bus;
|
||||
NvU8 slot;
|
||||
NvU8 function;
|
||||
NvBool is_virtfn;
|
||||
NvU32 domain;
|
||||
NvU32 bus;
|
||||
NvU32 device;
|
||||
NvU32 return_status;
|
||||
} vgpu_vfio_info;
|
||||
|
||||
typedef struct
|
||||
|
||||
Reference in New Issue
Block a user