NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-02-27 02:13:59 +00:00
Code Issues Packages Projects Releases Wiki Activity

550.90.07

Browse Source
This commit is contained in:
Bernhard Stoeckner
2024-06-04 13:48:03 +02:00
parent 083cd9cf17
commit e45d91de02
180 changed files with 43467 additions and 38127 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -905,6 +905,34 @@ typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2
*
* This command does the same thing as @ref NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION.
* The difference is that it doesn't take a list of clients and instead all channels belong
* to the client on which this control call is made.
*
* numChannels
* The number of valid entries in hChannelList array.
* hChannelList
* An array of NvHandle listing the channel handles
* to be stopped.
* bEnableAfterKeyRotation
* This determines if channel is enabled by RM after it completes key rotation.
* Possible status values returned are:
* NV_OK
* NVOS_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 (0x2080111b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID (0x1BU)
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS {
NvU32 numChannels;
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS;
/*

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -3741,7 +3741,8 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {

26
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -34,6 +34,8 @@
/*************************** SPDM COMMANDS ************************************/
#include "cc_drv.h"
/*!
* @brief SPDM Command Types
*
@@ -43,6 +45,7 @@
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
@@ -114,6 +117,25 @@ typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
/*!
* HCC FIPS Self-test.
*/
#define CE_FIPS_SELF_TEST_DATA_SIZE 16
#define CE_FIPS_SELF_TEST_AUTH_TAG_SIZE 16
#define CE_FIPS_SELF_TEST_IV_SIZE 12
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST {
NvU8 cmdType;
NvU8 isEnc;
CC_KMB kmb;
NvU8 text[CE_FIPS_SELF_TEST_DATA_SIZE];
NvU8 authTag[CE_FIPS_SELF_TEST_AUTH_TAG_SIZE];
} RM_GSP_SPDM_CMD_FIPS_SELFTEST;
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST *PRM_GSP_SPDM_CMD_FIPS_SELFTEST;
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
@@ -132,6 +154,9 @@ typedef union RM_GSP_SPDM_CMD {
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
RM_GSP_SPDM_CMD_FIPS_SELFTEST ccFipsTest;
} RM_GSP_SPDM_CMD;
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
@@ -149,6 +174,7 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST (0x6)