NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-02-09 17:50:00 +00:00
Code Issues Packages Projects Releases Wiki Activity

535.129.03

Browse Source
This commit is contained in:
Bernhard Stoeckner
2023-10-31 14:22:16 +01:00
parent f59818b751
commit e573018659
163 changed files with 86017 additions and 84520 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r537_41
#define NV_BUILD_BRANCH r537_68
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r537_41
#define NV_PUBLIC_BRANCH r537_68
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_41-286"
#define NV_BUILD_CHANGELIST_NUM (33292694)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_68-335"
#define NV_BUILD_CHANGELIST_NUM (33430121)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_41-286"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33292694)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_68-335"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33430121)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r537_41-1"
#define NV_BUILD_CHANGELIST_NUM (33292694)
#define NV_BUILD_BRANCH_VERSION "r537_68-2"
#define NV_BUILD_CHANGELIST_NUM (33425293)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "537.42"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33292694)
#define NV_BUILD_NAME "537.70"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33425293)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.113.01"
#define NV_VERSION_STRING "535.129.03"
#else

28
src/common/inc/swref/published/ampere/ga100/hwproject.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_hwproject_h__
#define __ga100_hwproject_h__
#define NV_SCAL_LITTER_NUM_FBPAS 24
#endif // __ga100_hwproject_h__

20
src/common/inc/swref/published/hopper/gh100/dev_fb.h
View File

@@ -30,24 +30,4 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __gh100_dev_fb_h_

18
src/common/inc/swref/published/hopper/gh100/dev_gsp.h
View File

@@ -31,4 +31,22 @@
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */
#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 8 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 8 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RWXVF */
#endif // __gh100_dev_gsp_h__

5
src/common/inc/swref/published/hopper/gh100/hwproject.h
View File

@@ -21,9 +21,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#define NV_FBPA_PRI_STRIDE 16384
#define NV_SCAL_LITTER_NUM_FBPAS 24
#define NV_XPL_BASE_ADDRESS 540672
#define NV_XTL_BASE_ADDRESS 593920
#define NV_FBPA_PRI_STRIDE 16384

28
src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_ptop_discovery_ip_h__
#define __ls10_ptop_discovery_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */
#endif // __ls10_ptop_discovery_ip_h__

21
src/common/inc/swref/published/turing/tu102/dev_fb.h
View File

@@ -38,4 +38,25 @@
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __tu102_dev_fb_h__

29
src/common/inc/swref/published/turing/tu102/dev_fbpa.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __tu102_dev_fbpa_h_
#define __tu102_dev_fbpa_h_
#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */
#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */
#endif // __tu102_dev_fbpa_h_

17
src/common/inc/swref/published/turing/tu102/dev_gsp.h
View File

@@ -38,5 +38,22 @@
#define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 4 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 4 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */
#endif // __tu102_dev_gsp_h__

6
src/common/inc/swref/published/hopper/gh100/dev_ltc.h → src/common/inc/swref/published/turing/tu102/dev_ltc.h
View File

@@ -21,8 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_ltc_h_
#define __gh100_dev_ltc_h_
#ifndef __tu102_dev_ltc_h_
#define __tu102_dev_ltc_h_
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
@@ -30,4 +30,4 @@
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __gh100_dev_ltc_h_
#endif // __tu102_dev_ltc_h_

4
src/common/inc/swref/published/turing/tu102/hwproject.h
View File

@@ -25,5 +25,9 @@
#define __tu102_hwproject_h__
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47
#define NV_SCAL_LITTER_NUM_FBPAS 16
#define NV_FBPA_PRI_STRIDE 16384
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#endif // __tu102_hwproject_h__

99
src/common/nvswitch/common/inc/soe/soeififr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -37,6 +37,17 @@ enum
RM_SOE_IFR_BBX_SHUTDOWN,
RM_SOE_IFR_BBX_SXID_ADD,
RM_SOE_IFR_BBX_SXID_GET,
RM_SOE_IFR_BBX_DATA_GET,
};
enum
{
RM_SOE_IFR_BBX_GET_NONE,
RM_SOE_IFR_BBX_GET_SXID,
RM_SOE_IFR_BBX_GET_SYS_INFO,
RM_SOE_IFR_BBX_GET_TIME_INFO,
RM_SOE_IFR_BBX_GET_TEMP_DATA,
RM_SOE_IFR_BBX_GET_TEMP_SAMPLES,
};
typedef struct
@@ -75,6 +86,14 @@ typedef struct
RM_FLCN_U64 dmaHandle;
} RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS;
typedef struct
{
NvU8 cmdType;
NvU32 sizeInBytes;
RM_FLCN_U64 dmaHandle;
NvU8 dataType;
} RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS;
typedef union
{
NvU8 cmdType;
@@ -82,6 +101,7 @@ typedef union
RM_SOE_IFR_CMD_BBX_INIT_PARAMS bbxInit;
RM_SOE_IFR_CMD_BBX_SXID_ADD_PARAMS bbxSxidAdd;
RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS bbxSxidGet;
RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS bbxDataGet;
} RM_SOE_IFR_CMD;
// entry of getSxid
@@ -99,4 +119,81 @@ typedef struct
RM_SOE_BBX_SXID_ENTRY sxidLast[INFOROM_BBX_OBJ_XID_ENTRIES];
} RM_SOE_BBX_GET_SXID_DATA;
// NVSwitch system version information returning with the command GET_SYS_INFO
typedef struct
{
NvU32 driverLo; //Driver Version Low 32 bits
NvU16 driverHi; //Driver Version High 16 bits
NvU32 vbiosVersion; //VBIOS Version
NvU8 vbiosVersionOem; //VBIOS OEM Version byte
NvU8 osType; //OS Type (UNIX/WIN/WIN2K/WIN9x/OTHER)
NvU32 osVersion; //OS Version (Build|MINOR|MAJOR)
} RM_SOE_BBX_GET_SYS_INFO_DATA;
// NVSwitch time information returning with the command GET_TIME_INFO
typedef struct
{
NvU32 timeStart; //Timestamp (EPOCH) when the driver was loaded on the GPU for the first time
NvU32 timeEnd; //Timestamp (EPOCH) when the data was last flushed
NvU32 timeRun; //Amount of time (in seconds) driver was loaded, and GPU has run
NvU32 time24Hours; //Timestamp (EPOCH) of when the first 24 operational hours is hit
NvU32 time100Hours; //Timestamp (EPOCH) of when the first 100 operational hours is hit
} RM_SOE_BBX_GET_TIME_INFO_DATA;
#define RM_SOE_BBX_TEMP_DAY_ENTRIES 5
#define RM_SOE_BBX_TEMP_WEEK_ENTRIES 5
#define RM_SOE_BBX_TEMP_MNT_ENTRIES 5
#define RM_SOE_BBX_TEMP_ALL_ENTRIES 5
#define RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES 23
#define RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES 5
#define RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES 3
#define RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES 20
#define RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES 21
#define RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES 168
#define RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES 1096
#define RM_SOE_BBX_NUM_COMPRESSION_PERIODS 8
// NVSwitch Temperature Entry
typedef struct
{
NvU16 value; //Temperature (SFXP 9.7 format in Celsius)
NvU32 timestamp; //Timestamp (EPOCH) of when the entry is recorded
} RM_SOE_BBX_TEMP_ENTRY;
// NVSwitch Temperature Data returning with the command GET_TEMP_DATA
typedef struct
{
NvU32 tempMaxDayIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxDay[RM_SOE_BBX_TEMP_DAY_ENTRIES];
NvU32 tempMaxWeekIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES];
NvU32 tempMaxMntIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES];
NvU32 tempMaxAllIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxAll[RM_SOE_BBX_TEMP_ALL_ENTRIES];
NvU32 tempMinDayIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinDay[RM_SOE_BBX_TEMP_DAY_ENTRIES];
NvU32 tempMinWeekIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES];
NvU32 tempMinMntIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES];
NvU32 tempMinAllIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinAll[RM_SOE_BBX_TEMP_ALL_ENTRIES];
NvU32 tempSumDelta;
NvU32 tempSumHour[RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES];
NvU32 tempSumDay[RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES];
NvU32 tempSumMnt[RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES];
NvU32 tempHistogramThld[RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES];
NvU32 tempHistogramTime[RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES];
RM_SOE_BBX_TEMP_ENTRY tempHourlyMaxSample[RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES];
} RM_SOE_BBX_GET_TEMP_DATA;
// NVSwitch Temperature Compressed Samples returning with the command GET_TEMP_SAMPLES
typedef struct
{
NvU32 compressionPeriodIdx;
NvU32 compressionPeriod[RM_SOE_BBX_NUM_COMPRESSION_PERIODS];
RM_SOE_BBX_TEMP_ENTRY tempCompressionBuffer[RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES];
} RM_SOE_BBX_GET_TEMP_SAMPLES;
#endif // _SOEIFIFR_H_

196
src/common/nvswitch/interface/ctrl_dev_nvswitch.h
View File

@@ -830,6 +830,7 @@ typedef enum nvswitch_err_type
NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN = 10006,
NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007,
NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008,
NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE = 10009,
NVSWITCH_ERR_HW_HOST_LAST,
@@ -2973,6 +2974,197 @@ typedef struct
NVSWITCH_SXID_ENTRY sxidLast[NVSWITCH_SXID_ENTRIES_NUM];
} NVSWITCH_GET_SXIDS_PARAMS;
/*
* CTRL_NVSWITCH_GET_SYS_INFO
*
* Control to get the NVSwitch system version information from inforom cache
*
* Parameters:
* driverLo [OUT]
* The driver version low 32 bits. Example: driverLo = 54531 (Driver 545.31)
* driverHi [OUT]
* The driver version high 16 bits
* vbiosVersion [OUT]
* The vbios version number. Example: vbiosVersion=0x96104100 (release 96.10.41.00)
* vbiosVersionOem [OUT]
* The vbios OEM version byte.
* osType [OUT]
* The OS type. Example: osType=0x05 (UNIX)
* osVersion [OUT]
* The OS version number. [BUILD[31:16]|MINOR[15:8]|MAJOR[7:0]]
*/
typedef struct
{
NvU32 driverLo;
NvU16 driverHi;
NvU32 vbiosVersion;
NvU8 vbiosVersionOem;
NvU8 osType;
NvU32 osVersion;
} NVSWITCH_GET_SYS_INFO_PARAMS;
/*
* CTRL_NVSWITCH_GET_TIME_INFO
*
* Control to get the NVSwitch time information from inforom cache
*
* Parameters:
* timeStart [OUT]
* The timestamp (EPOCH) when driver load onto the NVSwitch for the 1st time
* timeEnd [OUT]
* The timestamp (EPOCH) when the data was last flushed
* timeRun [OUT]
* The amount of time (in seconds) driver was loaded/running
* time24Hours [OUT]
* The timestamp (EPOCH) when the first 24 operational hours is hit
* time100Hours [OUT]
* The timestamp (EPOCH) when the first 100 operational hours is hit
*/
typedef struct
{
NvU32 timeStart;
NvU32 timeEnd;
NvU32 timeRun;
NvU32 time24Hours;
NvU32 time100Hours;
} NVSWITCH_GET_TIME_INFO_PARAMS;
#define NVSWITCH_TEMP_DAY_ENTRIES 5
#define NVSWITCH_TEMP_WEEK_ENTRIES 5
#define NVSWITCH_TEMP_MNT_ENTRIES 5
#define NVSWITCH_TEMP_ALL_ENTRIES 5
#define NVSWITCH_TEMP_SUM_HOUR_ENTRIES 23
#define NVSWITCH_TEMP_SUM_DAY_ENTRIES 5
#define NVSWITCH_TEMP_SUM_MNT_ENTRIES 3
#define NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES 20
#define NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES 21
#define NVSWITCH_TEMP_HOURLY_MAX_ENTRIES 168
/*
* NVSWITCH_TEMP_ENTRY
*
* This structure represents the NVSwitch TEMP with its timestamp.
*
* value
* This parameter specifies the NVSwitch Temperature
* (SFXP 9.7 format in Celsius).
*
* timestamp
* This parameter specifies the timestamp (EPOCH) of the entry.
*/
typedef struct
{
NvU16 value;
NvU32 timestamp;
} NVSWITCH_TEMP_ENTRY;
/*
* CTRL_NVSWITCH_GET_TEMP_DATA
*
* Control to get the NVSwitch device historical temperature information from inforom cache
*
* Parameters:
* tempMaxDayIdx [OUT]
* The current index to the maximum day temperature array
* tempMaxDay[] [OUT]
* The maximum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days
* tempMaxWeekIdx [OUT]
* The current index to the maximum week temperature array
* tempMaxWeek[] [OUT]
* The maximum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks
* tempMaxMntIdx [OUT]
* The current index to the maximum month temperature array
* tempMaxMnt[] [OUT]
* The maximum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months
* tempMaxAllIdx [OUT]
* The current index to the maximum temperature array
* tempMaxAll[] [OUT]
* The maximum temperature array for the device
* tempMinDayIdx [OUT]
* The current index to the minimum day temperature array
* tempMinDay[] [OUT]
* The minimum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days
* tempMinWeekIdx [OUT]
* The current index to the minimum week temperature array
* tempMinWeek[] [OUT]
* The minimum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks
* tempMinMntIdx [OUT]
* The current index to the minimum month temperature array
* tempMinMnt[] [OUT]
* The minimum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months
* tempMinAllIdx [OUT]
* The current index to the minimum temperature array
* tempMinAll[] [OUT]
* The minimum temperature array for the device
* tempSumDelta [OUT]
* The total sum of temperature change in 0.1C granularity
* tempSumHour[] [OUT]
* The moving average of temperature per hour, for last NVSWITCH_TEMP_SUM_HOUR_ENTRIES hours
* tempSumDay[] [OUT]
* The moving average of temperature per day, for last NVSWITCH_TEMP_SUM_DAY_ENTRIES days
* tempSumMnt[] [OUT]
* The moving average of temperature per month, for last NVSWITCH_TEMP_SUM_MNT_ENTRIES months
* tempHistogramThld[] [OUT]
* The histogram of temperature crossing various thresholds (5/10/15/.../95/100)
* tempHistogramTime[] [OUT]
* The histogram of time was in various temperature ranges (0..5/5..10/.../100..)
* tempHourlyMaxSample[] [OUT]
* The maximum hourly temperature array for the device
*/
typedef struct
{
NvU32 tempMaxDayIdx;
NVSWITCH_TEMP_ENTRY tempMaxDay[NVSWITCH_TEMP_DAY_ENTRIES];
NvU32 tempMaxWeekIdx;
NVSWITCH_TEMP_ENTRY tempMaxWeek[NVSWITCH_TEMP_WEEK_ENTRIES];
NvU32 tempMaxMntIdx;
NVSWITCH_TEMP_ENTRY tempMaxMnt[NVSWITCH_TEMP_MNT_ENTRIES];
NvU32 tempMaxAllIdx;
NVSWITCH_TEMP_ENTRY tempMaxAll[NVSWITCH_TEMP_ALL_ENTRIES];
NvU32 tempMinDayIdx;
NVSWITCH_TEMP_ENTRY tempMinDay[NVSWITCH_TEMP_DAY_ENTRIES];
NvU32 tempMinWeekIdx;
NVSWITCH_TEMP_ENTRY tempMinWeek[NVSWITCH_TEMP_WEEK_ENTRIES];
NvU32 tempMinMntIdx;
NVSWITCH_TEMP_ENTRY tempMinMnt[NVSWITCH_TEMP_MNT_ENTRIES];
NvU32 tempMinAllIdx;
NVSWITCH_TEMP_ENTRY tempMinAll[NVSWITCH_TEMP_ALL_ENTRIES];
NvU32 tempSumDelta;
NvU32 tempSumHour[NVSWITCH_TEMP_SUM_HOUR_ENTRIES];
NvU32 tempSumDay[NVSWITCH_TEMP_SUM_DAY_ENTRIES];
NvU32 tempSumMnt[NVSWITCH_TEMP_SUM_MNT_ENTRIES];
NvU32 tempHistogramThld[NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES];
NvU32 tempHistogramTime[NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES];
NVSWITCH_TEMP_ENTRY tempHourlyMaxSample[NVSWITCH_TEMP_HOURLY_MAX_ENTRIES];
} NVSWITCH_GET_TEMP_DATA_PARAMS;
#define NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES 1096
#define NVSWITCH_NUM_COMPRESSION_PERIODS 8
/*
* CTRL_NVSWITCH_GET_TEMP_DATA
*
* Control to get the NVSwitch device temperature information from inforom cache
*
* Parameters:
* compressionPeriodIdx [OUT]
* The current index to the sample period array
* compressionPeriod[] [OUT]
* The samples period array (seconds)
* tempCompressionBuffer[] [OUT]
* The temperature array sampling at a specific period in compressionPeriod[]
*/
typedef struct
{
NvU32 compressionPeriodIdx;
NvU32 compressionPeriod[NVSWITCH_NUM_COMPRESSION_PERIODS];
NVSWITCH_TEMP_ENTRY tempCompressionBuffer[NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES];
} NVSWITCH_GET_TEMP_SAMPLES_PARAMS;
/*
* CTRL_NVSWITCH_GET_FOM_VALUES
* This command gives the FOM values to MODS
@@ -3848,6 +4040,10 @@ typedef struct
#define CTRL_NVSWITCH_RESERVED_11 0x55
#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x56
#define CTRL_NVSWITCH_GET_POWER 0x57
#define CTRL_NVSWITCH_GET_SYS_INFO 0x58
#define CTRL_NVSWITCH_GET_TIME_INFO 0x59
#define CTRL_NVSWITCH_GET_TEMP_DATA 0x60
#define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x61
#ifdef __cplusplus
}

2
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -158,6 +158,7 @@
_op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \
_op(NvlStatus, nvswitch_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS * params), _arch) \
_op(NvlStatus, nvswitch_bbx_get_data, (nvswitch_device *device, NvU8 dataType, void * params), _arch) \
_op(NvlStatus, nvswitch_smbpbi_alloc, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_smbpbi_post_init_hal, (nvswitch_device *device), _arch) \
_op(void, nvswitch_smbpbi_destroy_hal, (nvswitch_device *device), _arch) \
@@ -235,6 +236,7 @@
_op(NvlStatus, nvswitch_ctrl_therm_read_power, (nvswitch_device *device, NVSWITCH_GET_POWER_PARAMS *info), _arch) \
_op(NvBool, nvswitch_does_link_need_termination_enabled, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvlStatus, nvswitch_link_termination_setup, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvlStatus, nvswitch_check_io_sanity, (nvswitch_device *device), _arch) \
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
_op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \

3
src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -184,6 +184,7 @@ NvlStatus nvswitch_inforom_bbx_add_sxid(nvswitch_device *device,
NvU32 data1, NvU32 data2);
NvlStatus nvswitch_inforom_bbx_get_sxid(nvswitch_device *device,
NVSWITCH_GET_SXIDS_PARAMS *params);
NvlStatus nvswitch_inforom_bbx_get_data(nvswitch_device *device, NvU8 dataType, void *params);
// InfoROM DEM APIs
NvlStatus nvswitch_inforom_dem_load(nvswitch_device *device);

10
src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -169,4 +169,12 @@ nvswitch_bbx_get_sxid_lr10
NVSWITCH_GET_SXIDS_PARAMS * params
);
NvlStatus
nvswitch_bbx_get_data_lr10
(
nvswitch_device *device,
NvU8 dataType,
void *params
);
#endif //_INFOROM_LR10_H_

9
src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -154,4 +154,11 @@ nvswitch_bbx_get_sxid_ls10
NVSWITCH_GET_SXIDS_PARAMS * params
);
NvlStatus
nvswitch_bbx_get_data_ls10
(
nvswitch_device *device,
NvU8 dataType,
void *params
);
#endif //_INFOROM_LS10_H_

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@@ -1370,7 +1370,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03,
0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf,
0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801,
0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111,
0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d,
0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28,
@@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999,
0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff,
0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c,
0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0,
0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x176bd707, 0x7693db62, 0xcee1dbf7, 0x0ec5a1fa,
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x930f31b1, 0x6ce8df20, 0xa1e5e4d9, 0xc55f48a9,
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7,
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@@ -1370,7 +1370,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03,
0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf,
0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801,
0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111,
0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d,
0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28,
@@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999,
0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff,
0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c,
0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0,
0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x176bd707, 0x7693db62, 0xcee1dbf7, 0x0ec5a1fa,
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x930f31b1, 0x6ce8df20, 0xa1e5e4d9, 0xc55f48a9,
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7,
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

20
src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -130,3 +130,21 @@ nvswitch_inforom_bbx_get_sxid
return status;
}
NvlStatus
nvswitch_inforom_bbx_get_data
(
nvswitch_device *device,
NvU8 dataType,
void *params
)
{
NvlStatus status;
status = device->hal.nvswitch_bbx_get_data(device, dataType, params);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: (type=%d) failed, status=%d\n", __FUNCTION__, dataType, status);
}
return status;
}

14
src/common/nvswitch/kernel/lr10/inforom_lr10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -32,6 +32,7 @@
#include "nvVer.h"
#include "regkey_nvswitch.h"
#include "inforom/inforom_nvl_v3_nvswitch.h"
#include "soe/soeififr.h"
//
// TODO: Split individual object hals to their own respective files
@@ -1280,3 +1281,14 @@ nvswitch_bbx_get_sxid_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_bbx_get_data_lr10
(
nvswitch_device *device,
NvU8 dataType,
void *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
}

5
src/common/nvswitch/kernel/lr10/link_lr10.c
View File

@@ -566,6 +566,11 @@ nvswitch_init_lpwr_regs_lr10
NvU8 softwareDesired, hardwareDisable;
NvBool bLpEnable;
if (nvswitch_is_link_in_reset(device, link))
{
return;
}
if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO)
{
return;

18
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -3656,6 +3656,15 @@ nvswitch_initialize_device_state_lr10
goto nvswitch_initialize_device_state_exit;
}
retval = nvswitch_check_io_sanity(device);
if (NVL_SUCCESS != retval)
{
NVSWITCH_PRINT(device, ERROR,
"%s: IO sanity test failed\n",
__FUNCTION__);
goto nvswitch_initialize_device_state_exit;
}
NVSWITCH_PRINT(device, SETUP,
"%s: MMIO discovery\n",
__FUNCTION__);
@@ -7850,6 +7859,15 @@ nvswitch_ctrl_get_nvlink_error_threshold_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_check_io_sanity_lr10
(
nvswitch_device *device
)
{
return NVL_SUCCESS;
}
//
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
// macro in haldef_nvswitch.h

173
src/common/nvswitch/kernel/ls10/inforom_ls10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -863,3 +863,174 @@ nvswitch_bbx_get_sxid_ls10_free_and_exit:
return status;
}
NvlStatus
nvswitch_bbx_get_data_ls10
(
nvswitch_device *device,
NvU8 dataType,
void *params
)
{
NvlStatus status;
void *pDmaBuf;
NvU64 dmaHandle;
FLCN *pFlcn;
RM_FLCN_CMD_SOE bbxCmd;
NvU32 cmdSeqDesc;
NVSWITCH_TIMEOUT timeout;
NvU32 transferSize;
if (!nvswitch_is_inforom_supported_ls10(device))
{
NVSWITCH_PRINT(device, ERROR, "%s: InfoROM is not supported\n", __FUNCTION__);
return -NVL_ERR_NOT_SUPPORTED;
}
if (params == NULL)
{
NVSWITCH_PRINT(device, ERROR, "%s: params is NULL\n", __FUNCTION__);
return -NVL_BAD_ARGS;
}
switch (dataType)
{
case RM_SOE_IFR_BBX_GET_SYS_INFO:
transferSize = sizeof(NVSWITCH_GET_SYS_INFO_PARAMS);
break;
case RM_SOE_IFR_BBX_GET_TIME_INFO:
transferSize = sizeof(NVSWITCH_GET_TIME_INFO_PARAMS);
break;
case RM_SOE_IFR_BBX_GET_TEMP_DATA:
transferSize = sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS);
break;
case RM_SOE_IFR_BBX_GET_TEMP_SAMPLES:
transferSize = sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS);
break;
default:
NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType);
return -NVL_BAD_ARGS;
break;
}
status = nvswitch_os_alloc_contig_memory(device->os_handle, &pDmaBuf, transferSize,
(device->dma_addr_width == 32));
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to allocate contig memory. rc:%d\n", __FUNCTION__, status);
return status;
}
status = nvswitch_os_map_dma_region(device->os_handle, pDmaBuf, &dmaHandle,
transferSize, NVSWITCH_DMA_DIR_TO_SYSMEM);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to map DMA region. rc:%d\n", __FUNCTION__, status);
goto nvswitch_bbx_get_data_ls10_free_and_exit;
}
nvswitch_os_memset(pDmaBuf, 0, transferSize);
pFlcn = device->pSoe->pFlcn;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
bbxCmd.hdr.size = sizeof(bbxCmd);
bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_DATA_GET;
bbxCmd.cmd.ifr.bbxDataGet.sizeInBytes = transferSize;
bbxCmd.cmd.ifr.bbxDataGet.dataType = dataType;
RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxDataGet.dmaHandle, &dmaHandle);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&bbxCmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: BX_GET_DATA type=%d failed. rc:%d\n",
__FUNCTION__, dataType, status);
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
status = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle,
transferSize,
NVSWITCH_DMA_DIR_TO_SYSMEM);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to sync DMA region. rc:%d\n", __FUNCTION__, status);
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
if (dataType == RM_SOE_IFR_BBX_GET_SYS_INFO)
{
NVSWITCH_GET_SYS_INFO_PARAMS bbxSysInfoData = {0};
nvswitch_os_memcpy((NvU8 *)&bbxSysInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxSysInfoData, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS));
}
else if (dataType == RM_SOE_IFR_BBX_GET_TIME_INFO)
{
NVSWITCH_GET_TIME_INFO_PARAMS bbxTimeInfoData = {0};
nvswitch_os_memcpy((NvU8 *)&bbxTimeInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxTimeInfoData, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS));
}
else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_DATA)
{
NVSWITCH_GET_TEMP_DATA_PARAMS *pBbxTempData = NULL;
pBbxTempData = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
if (pBbxTempData == NULL)
{
NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType);
status = -NVL_NO_MEM;
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
nvswitch_os_memset(pBbxTempData, 0, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
nvswitch_os_memcpy((NvU8 *)pBbxTempData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempData, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
nvswitch_os_free(pBbxTempData);
}
else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_SAMPLES)
{
NVSWITCH_GET_TEMP_SAMPLES_PARAMS *pBbxTempSamples = NULL;
pBbxTempSamples = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
if (pBbxTempSamples == NULL)
{
NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType);
status = -NVL_NO_MEM;
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
nvswitch_os_memset(pBbxTempSamples, 0, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
nvswitch_os_memcpy((NvU8 *)pBbxTempSamples, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempSamples, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
nvswitch_os_free(pBbxTempSamples);
}
else
{
NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType);
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
nvswitch_bbx_get_data_ls10_unmap_and_exit:
nvswitch_os_unmap_dma_region(device->os_handle, pDmaBuf, dmaHandle,
transferSize, NVSWITCH_DMA_DIR_FROM_SYSMEM);
nvswitch_bbx_get_data_ls10_free_and_exit:
nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize);
return status;
}

99
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -42,6 +42,7 @@
#include "ls10/gfw_ls10.h"
#include "nvswitch/ls10/dev_nvs_top.h"
#include "nvswitch/ls10/ptop_discovery_ip.h"
#include "nvswitch/ls10/dev_pri_masterstation_ip.h"
#include "nvswitch/ls10/dev_pri_hub_sys_ip.h"
#include "nvswitch/ls10/dev_nvlw_ip.h"
@@ -5839,6 +5840,104 @@ nvswitch_ctrl_get_nvlink_error_threshold_ls10
return NVL_SUCCESS;
}
NvlStatus
nvswitch_check_io_sanity_ls10
(
nvswitch_device *device
)
{
NvBool keepPolling;
NVSWITCH_TIMEOUT timeout;
NvU32 val;
NvBool error = NV_FALSE;
NvU32 sxid;
const char *sxid_desc = NULL;
//
// NOTE: MMIO discovery has not been performed so only constant BAR0 offset
// addressing can be performed.
//
// BAR0 offset 0 should always contain valid data -- unless it doesn't
val = NVSWITCH_OFF_RD32(device, 0);
if (val == 0)
{
error = NV_TRUE;
sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE;
sxid_desc = "Firmware recovery mode";
}
else if ((val == 0xFFFFFFFF) || ((val & 0xFFFF0000) == 0xBADF0000))
{
error = NV_TRUE;
sxid = NVSWITCH_ERR_HW_HOST_IO_FAILURE;
sxid_desc = "IO failure";
}
else if (!IS_FMODEL(device))
{
// check if FSP successfully started
nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
do
{
keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS);
if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val))
{
break;
}
nvswitch_os_sleep(1);
}
while (keepPolling);
if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val))
{
error = NV_TRUE;
sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE;
sxid_desc = "Firmware initialization failure";
}
}
if (error)
{
NVSWITCH_RAW_ERROR_LOG_TYPE report = { 0, { 0 } };
NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }};
NvU32 report_idx = 0;
NvU32 i;
val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS);
report.data[report_idx++] = val;
NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n",
__FUNCTION__, val);
for (i = 0; i <= 15; i++)
{
val = NVSWITCH_OFF_RD32(device,
NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 + NV_NVLSAW_SW_SCRATCH(i));
report_saw.data[i] = val;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n",
__FUNCTION__, i, val);
}
for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++)
{
val = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i));
report.data[report_idx++] = val;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
__FUNCTION__, i, val);
}
// Include useful scratch information for triage
NVSWITCH_PRINT_SXID_NO_BBX(device, sxid,
"Fatal, %s (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", sxid_desc,
report.data[0], report.data[1], report.data[2], report.data[3], report.data[4],
report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]);
return -NVL_INITIALIZATION_TOTAL_FAILURE;
}
return NVL_SUCCESS;
}
NvlStatus
nvswitch_read_vbios_link_entries_ls10
(

70
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -30,6 +30,7 @@
#include "flcn/haldefs_flcnable_nvswitch.h"
#include "flcn/flcn_nvswitch.h"
#include "soe/soe_nvswitch.h"
#include "soe/soeififr.h"
#include "nvVer.h"
#include "nvlink_inband_msg.h"
@@ -3475,6 +3476,46 @@ _nvswitch_ctrl_get_inforom_bbx_sxid
return nvswitch_inforom_bbx_get_sxid(device, params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_sys_info
(
nvswitch_device *device,
NVSWITCH_GET_SYS_INFO_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_SYS_INFO, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_time_info
(
nvswitch_device *device,
NVSWITCH_GET_TIME_INFO_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TIME_INFO, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_temp_data
(
nvswitch_device *device,
NVSWITCH_GET_TEMP_DATA_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_DATA, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_temp_samples
(
nvswitch_device *device,
NVSWITCH_GET_TEMP_SAMPLES_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_SAMPLES, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_nvlink_lp_counters
(
@@ -4666,6 +4707,15 @@ nvswitch_program_l1_scratch_reg
device->hal.nvswitch_program_l1_scratch_reg(device, linkNumber);
}
NvlStatus
nvswitch_check_io_sanity
(
nvswitch_device *device
)
{
return device->hal.nvswitch_check_io_sanity(device);
}
NvlStatus
nvswitch_launch_ALI
(
@@ -5181,6 +5231,26 @@ nvswitch_lib_ctrl
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER,
_nvswitch_ctrl_therm_read_power,
NVSWITCH_GET_POWER_PARAMS);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_SYS_INFO,
_nvswitch_ctrl_get_inforom_bbx_sys_info,
NVSWITCH_GET_SYS_INFO_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TIME_INFO,
_nvswitch_ctrl_get_inforom_bbx_time_info,
NVSWITCH_GET_TIME_INFO_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TEMP_DATA,
_nvswitch_ctrl_get_inforom_bbx_temp_data,
NVSWITCH_GET_TEMP_DATA_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TEMP_SAMPLES,
_nvswitch_ctrl_get_inforom_bbx_temp_samples,
NVSWITCH_GET_TEMP_SAMPLES_PARAMS,
osPrivate, flags);
default:
nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd);

38
src/common/sdk/nvidia/inc/class/cl90e7.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90e7_h_
#define _cl90e7_h_
#ifdef __cplusplus
extern "C" {
#endif
#define GF100_SUBDEVICE_INFOROM (0x000090e7)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl90e7_h

2
src/common/sdk/nvidia/inc/class/clcba2.h
View File

@@ -118,6 +118,7 @@ typedef volatile struct _clcba2_tag0 {
// Class definitions
#define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024)
#define NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES (1024*1024*1024)
// Errors
#define NVCBA2_ERROR_NONE (0x00000000)
@@ -149,6 +150,7 @@ typedef volatile struct _clcba2_tag0 {
#define NVCBA2_ERROR_SCRUBBER_INVALD_ADDRESS (0x0000001a)
#define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b)
#define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c)
#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d)
#ifdef __cplusplus
}; /* extern "C" */

55
src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h
View File

@@ -887,10 +887,6 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
* This parameter is set by the client to indicate the
* gpuId of the GPU to which the display to be optimized
* is attached.
* display
* This parameter is not used by RM currently.
* Clients can ignore this parameter. Note that this
* parameter will be removed in future.
* output
* This parameter is set by the client to indicate the
* output resource type of the display to be optimized.
@@ -1033,6 +1029,12 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
* optimal pixel clock to use with the adjusted mode,
* in units of Hz.
*
*
* bOptimized[out]
* This is set to NV_TRUE if the timings were successfully optimized, and
* NV_FALSE otherwise.
*
*
* Progressive Raster Structure
*
* hSyncEnd hTotal
@@ -1145,28 +1147,29 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS {
NvU32 gpuId;
NvU32 display;
NvU32 output;
NvU32 protocol;
NvU32 structure;
NvU32 adjust;
NvU32 hDeltaStep;
NvU32 hDeltaMax;
NvU32 vDeltaStep;
NvU32 vDeltaMax;
NvU32 hSyncEnd;
NvU32 hBlankEnd;
NvU32 hBlankStart;
NvU32 hTotal;
NvU32 vSyncEnd;
NvU32 vBlankEnd;
NvU32 vBlankStart;
NvU32 vInterlacedBlankEnd;
NvU32 vInterlacedBlankStart;
NvU32 vTotal;
NvU32 refreshX10K;
NvU32 pixelClockHz;
NvU32 gpuId;
NvU32 output;
NvU32 protocol;
NvU32 structure;
NvU32 adjust;
NvU32 hDeltaStep;
NvU32 hDeltaMax;
NvU32 vDeltaStep;
NvU32 vDeltaMax;
NvU32 hSyncEnd;
NvU32 hBlankEnd;
NvU32 hBlankStart;
NvU32 hTotal;
NvU32 vSyncEnd;
NvU32 vBlankEnd;
NvU32 vBlankStart;
NvU32 vInterlacedBlankEnd;
NvU32 vInterlacedBlankStart;
NvU32 vTotal;
NvU32 refreshX10K;
NvU32 pixelClockHz;
NvBool bOptimized;
} NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS;
/* output values */

72
src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h Normal file
View File

@@ -0,0 +1,72 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl90e7.finn
//
#include "nvfixedtypes.h"
#include "ctrl/ctrlxxxx.h"
/* GF100_SUBDEVICE_INFOROM control commands and parameters */
#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx)
/* Command categories (6 bits) */
#define NV90E7_CTRL_RESERVED (0x00)
#define NV90E7_CTRL_BBX (0x01)
/*
* NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME
*
* This command is used to query the last BBX flush timestamp and duration. If BBX has not yet
* been flushed, the status returned is NV_ERR_NOT_READY.
*
* timestamp
* This parameter specifies the start timestamp of the last BBX flush.
*
* durationUs
* This parameter specifies the duration (us) of the last BBX flush.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_READY
* NV_ERR_NOT_SUPPORTED
*/
#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */
#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
NvU32 durationUs;
} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS;

34
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -556,4 +556,36 @@ typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
NVB0CC_CTRL_HES_TYPE type;
} NVB0CC_CTRL_RELEASE_HES_PARAMS;
/*!
* NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST
*
* Disable the Dynamic MMA clock boost during profiler lifetime.
*
*/
#define NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST (0xb0cc0117) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID (0x17U)
typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS {
/*!
* [in]: En/Disable Dynamic MMA Boost. True = disable Boost; False = re-enable Boost.
*/
NvBool disable;
} NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS;
/*!
* NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS
*
* Request the Dynamic MMA clock boost feature enablement status.
*
*/
#define NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS (0xb0cc0118) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID (0x18U)
typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS {
/*!
* [out]: Dynamic MMA Boost status: true = boost enabled/available; False = Boost disabled/unavailable.
*/
NvBool enabled;
} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS;
/* _ctrlb0ccprofiler_h_ */

2
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -558,8 +558,6 @@ typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER;
typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED;
#define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U)
typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX;
#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U)
typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR;
#define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U)
typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED;

3
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -122,7 +122,8 @@
#define ROBUST_CHANNEL_DLA_ERROR (138)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_LAST_ERROR (UNRECOVERABLE_ECC_ERROR_ESCAPE)
#define GPU_INIT_ERROR (143)
#define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR)
// Indexed CE reference

174
src/common/uproc/os/common/include/libos_v3_crashcat.h Normal file
View File

@@ -0,0 +1,174 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef LIBOS_V3_CRASH_CAT_H
#define LIBOS_V3_CRASH_CAT_H
#include "nv-crashcat.h"
#include "nv-crashcat-decoder.h"
// libosv3 implements the CrashCat V1 protocol with the following implementation-defined bits
typedef enum
{
LibosPanicReasonUnspecified = 0x00,
LibosPanicReasonUnhandledState = 0x01,
LibosPanicReasonInvalidConfiguration = 0x02,
LibosPanicReasonFatalHardwareError = 0x03,
LibosPanicReasonInsufficientResources = 0x04,
LibosPanicReasonTimeout = 0x05,
LibosPanicReasonEnvCallFailed = 0x06,
LibosPanicReasonAsanMemoryError = 0x08,
LibosPanicReasonProgrammingError = 0x0a,
LibosPanicReasonAssertionFailed = 0x0b,
LibosPanicReasonTrapKernelPanic = 0x0c,
LibosPanicReasonTrapInstruction = 0x0d,
LibosPanicReasonCount
} LibosPanicReason;
typedef enum{
LibosKernelModuleInit = 0x00,
LibosKernelModuleIpi = 0x01,
LibosKernelModuleLoader = 0x02,
LibosKernelModulePartition = 0x03,
LibosKernelModuleSbi = 0x04,
LibosKernelModulePagetable = 0x05,
LibosKernelModuleAddressSpace = 0x06,
LibosKernelModuleIdentity = 0x07,
LibosKernelModuleObjectPool = 0x08,
LibosKernelModulePageState = 0x09,
LibosKernelModuleMemoryPool = 0x10,
LibosKernelModuleBuddyState = 0x11,
LibosKernelModuleServer = 0x12,
LibosKernelModuleDmaDriver = 0x13,
LibosKernelModuleExtIntrDriver = 0x14,
LibosKernelModuleSoftMmuCore = 0x15,
LibosKernelModulePagestream = 0x16,
LibosKernelModuleTask = 0x17,
LibosKernelModuleGdmaDriver = 0x18,
LibosKernelModuleCacheDriver = 0x19,
LibosKernelModuleMinTree = 0x20,
LibosKernelModuleList = 0x21,
LibosKernelModuleSpinlock = 0x22,
LibosKernelModuleScheduler = 0x23,
LibosKernelModulePort = 0x24,
LibosKernelModuleGlobalPort = 0x25,
LibosKernelModuleProxyPort = 0x26,
LibosKernelModuleTimer = 0x27,
} LibosKernelModule;
// NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE (bits 63:0) - "LIBOS3.1"
#define NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE_LIBOS3 (0x4C49424F53332E31ull)
// NV_CRASHCAT_REPORT_V1_REPORTER_ID_IMPL_DEF (bits 63:18)
#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID 31:24
#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_RESERVED 63:32
#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF)
static NV_INLINE
void crashcatReportV1SetReporterLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id)
{
pReport->reporterId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID,
task_id, pReport->reporterId);
}
static NV_INLINE
NvU8 crashcatReportV1ReporterLibos3TaskId(NvCrashCatReport_V1 *pReport)
{
return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID, pReport->reporterId);
}
// NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION (bits 31:0)
#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_CL 23:0
#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MINOR 27:24
#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MAJOR 31:28
static NV_INLINE
void crashcatReportV1SetReporterVersionLibos3(NvCrashCatReport_V1 *pReport, NvU32 cl)
{
pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA,
_VERSION_LIBOS3_MAJOR, 3, pReport->reporterData);
pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA,
_VERSION_LIBOS3_MINOR, 1, pReport->reporterData);
pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA,
_VERSION_LIBOS3_CL, cl, pReport->reporterData);
}
static NV_INLINE
NvU32 crashcatReportV1ReporterVersionLibos3Cl(NvCrashCatReport_V1 *pReport)
{
return DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_CL,
crashcatReportV1ReporterVersion(pReport));
}
static NV_INLINE
NvU8 crashcatReportV1ReporterVersionLibos3Minor(NvCrashCatReport_V1 *pReport)
{
return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MINOR,
crashcatReportV1ReporterVersion(pReport));
}
static NV_INLINE
NvU8 crashcatReportV1ReporterVersionLibos3Major(NvCrashCatReport_V1 *pReport)
{
return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MAJOR,
crashcatReportV1ReporterVersion(pReport));
}
// NV_CRASHCAT_REPORT_V1_SOURCE_ID_IMPL_DEF (63:18)
#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID 31:24
#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_RESERVED 63:32
#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF)
static NV_INLINE
void crashcatReportV1SetSourceLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id)
{
pReport->sourceId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, task_id,
pReport->sourceId);
}
static NV_INLINE
NvU8 crashcatReportV1SourceLibos3TaskId(NvCrashCatReport_V1 *pReport)
{
return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, pReport->sourceId);
}
// NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_IMPL_DEF (63:32)
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_REASON 39:32
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_RESERVED 63:40
static NV_INLINE
void crashcatReportV1SetSourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport,
LibosPanicReason reason)
{
pReport->sourceCause = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON,
reason, pReport->sourceCause);
}
static NV_INLINE
LibosPanicReason crashcatReportV1SourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport)
{
return (LibosPanicReason)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON,
pReport->sourceCause);
}
#endif // LIBOS_V3_CRASH_CAT_H