mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-07 16:49:58 +00:00
535.129.03
This commit is contained in:
@@ -158,6 +158,7 @@
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_op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \
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_op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \
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_op(NvlStatus, nvswitch_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS * params), _arch) \
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_op(NvlStatus, nvswitch_bbx_get_data, (nvswitch_device *device, NvU8 dataType, void * params), _arch) \
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_op(NvlStatus, nvswitch_smbpbi_alloc, (nvswitch_device *device), _arch) \
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_op(NvlStatus, nvswitch_smbpbi_post_init_hal, (nvswitch_device *device), _arch) \
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_op(void, nvswitch_smbpbi_destroy_hal, (nvswitch_device *device), _arch) \
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@@ -235,6 +236,7 @@
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_op(NvlStatus, nvswitch_ctrl_therm_read_power, (nvswitch_device *device, NVSWITCH_GET_POWER_PARAMS *info), _arch) \
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_op(NvBool, nvswitch_does_link_need_termination_enabled, (nvswitch_device *device, nvlink_link *link), _arch) \
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_op(NvlStatus, nvswitch_link_termination_setup, (nvswitch_device *device, nvlink_link *link), _arch) \
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_op(NvlStatus, nvswitch_check_io_sanity, (nvswitch_device *device), _arch) \
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#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
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_op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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||||
* SPDX-License-Identifier: MIT
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||||
*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -184,6 +184,7 @@ NvlStatus nvswitch_inforom_bbx_add_sxid(nvswitch_device *device,
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NvU32 data1, NvU32 data2);
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NvlStatus nvswitch_inforom_bbx_get_sxid(nvswitch_device *device,
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NVSWITCH_GET_SXIDS_PARAMS *params);
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NvlStatus nvswitch_inforom_bbx_get_data(nvswitch_device *device, NvU8 dataType, void *params);
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// InfoROM DEM APIs
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NvlStatus nvswitch_inforom_dem_load(nvswitch_device *device);
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -169,4 +169,12 @@ nvswitch_bbx_get_sxid_lr10
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NVSWITCH_GET_SXIDS_PARAMS * params
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);
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NvlStatus
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nvswitch_bbx_get_data_lr10
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(
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nvswitch_device *device,
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NvU8 dataType,
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void *params
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);
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#endif //_INFOROM_LR10_H_
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@@ -1,5 +1,5 @@
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/*
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||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -154,4 +154,11 @@ nvswitch_bbx_get_sxid_ls10
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NVSWITCH_GET_SXIDS_PARAMS * params
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);
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NvlStatus
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nvswitch_bbx_get_data_ls10
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(
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nvswitch_device *device,
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NvU8 dataType,
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void *params
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);
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#endif //_INFOROM_LS10_H_
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@@ -1370,7 +1370,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
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||||
0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03,
|
||||
0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf,
|
||||
0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801,
|
||||
0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
|
||||
0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
|
||||
0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111,
|
||||
0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d,
|
||||
0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28,
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||||
@@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
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||||
0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
|
||||
0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999,
|
||||
0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff,
|
||||
0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
|
||||
0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
|
||||
0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c,
|
||||
0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0,
|
||||
0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00,
|
||||
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x176bd707, 0x7693db62, 0xcee1dbf7, 0x0ec5a1fa,
|
||||
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x930f31b1, 0x6ce8df20, 0xa1e5e4d9, 0xc55f48a9,
|
||||
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7,
|
||||
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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||||
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||||
@@ -1370,7 +1370,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
|
||||
0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03,
|
||||
0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf,
|
||||
0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801,
|
||||
0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
|
||||
0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
|
||||
0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111,
|
||||
0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d,
|
||||
0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28,
|
||||
@@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
|
||||
0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
|
||||
0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999,
|
||||
0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff,
|
||||
0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
|
||||
0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
|
||||
0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c,
|
||||
0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0,
|
||||
0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00,
|
||||
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x176bd707, 0x7693db62, 0xcee1dbf7, 0x0ec5a1fa,
|
||||
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x930f31b1, 0x6ce8df20, 0xa1e5e4d9, 0xc55f48a9,
|
||||
0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7,
|
||||
0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -130,3 +130,21 @@ nvswitch_inforom_bbx_get_sxid
|
||||
return status;
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_inforom_bbx_get_data
|
||||
(
|
||||
nvswitch_device *device,
|
||||
NvU8 dataType,
|
||||
void *params
|
||||
)
|
||||
{
|
||||
NvlStatus status;
|
||||
|
||||
status = device->hal.nvswitch_bbx_get_data(device, dataType, params);
|
||||
if (status != NVL_SUCCESS)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: (type=%d) failed, status=%d\n", __FUNCTION__, dataType, status);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -32,6 +32,7 @@
|
||||
#include "nvVer.h"
|
||||
#include "regkey_nvswitch.h"
|
||||
#include "inforom/inforom_nvl_v3_nvswitch.h"
|
||||
#include "soe/soeififr.h"
|
||||
|
||||
//
|
||||
// TODO: Split individual object hals to their own respective files
|
||||
@@ -1280,3 +1281,14 @@ nvswitch_bbx_get_sxid_lr10
|
||||
return -NVL_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_bbx_get_data_lr10
|
||||
(
|
||||
nvswitch_device *device,
|
||||
NvU8 dataType,
|
||||
void *params
|
||||
)
|
||||
{
|
||||
return -NVL_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
@@ -566,6 +566,11 @@ nvswitch_init_lpwr_regs_lr10
|
||||
NvU8 softwareDesired, hardwareDisable;
|
||||
NvBool bLpEnable;
|
||||
|
||||
if (nvswitch_is_link_in_reset(device, link))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO)
|
||||
{
|
||||
return;
|
||||
|
||||
@@ -3656,6 +3656,15 @@ nvswitch_initialize_device_state_lr10
|
||||
goto nvswitch_initialize_device_state_exit;
|
||||
}
|
||||
|
||||
retval = nvswitch_check_io_sanity(device);
|
||||
if (NVL_SUCCESS != retval)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR,
|
||||
"%s: IO sanity test failed\n",
|
||||
__FUNCTION__);
|
||||
goto nvswitch_initialize_device_state_exit;
|
||||
}
|
||||
|
||||
NVSWITCH_PRINT(device, SETUP,
|
||||
"%s: MMIO discovery\n",
|
||||
__FUNCTION__);
|
||||
@@ -7850,6 +7859,15 @@ nvswitch_ctrl_get_nvlink_error_threshold_lr10
|
||||
return -NVL_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_check_io_sanity_lr10
|
||||
(
|
||||
nvswitch_device *device
|
||||
)
|
||||
{
|
||||
return NVL_SUCCESS;
|
||||
}
|
||||
|
||||
//
|
||||
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
|
||||
// macro in haldef_nvswitch.h
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -863,3 +863,174 @@ nvswitch_bbx_get_sxid_ls10_free_and_exit:
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_bbx_get_data_ls10
|
||||
(
|
||||
nvswitch_device *device,
|
||||
NvU8 dataType,
|
||||
void *params
|
||||
)
|
||||
{
|
||||
NvlStatus status;
|
||||
void *pDmaBuf;
|
||||
NvU64 dmaHandle;
|
||||
FLCN *pFlcn;
|
||||
RM_FLCN_CMD_SOE bbxCmd;
|
||||
NvU32 cmdSeqDesc;
|
||||
NVSWITCH_TIMEOUT timeout;
|
||||
NvU32 transferSize;
|
||||
|
||||
if (!nvswitch_is_inforom_supported_ls10(device))
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: InfoROM is not supported\n", __FUNCTION__);
|
||||
return -NVL_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
if (params == NULL)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: params is NULL\n", __FUNCTION__);
|
||||
return -NVL_BAD_ARGS;
|
||||
}
|
||||
|
||||
switch (dataType)
|
||||
{
|
||||
case RM_SOE_IFR_BBX_GET_SYS_INFO:
|
||||
transferSize = sizeof(NVSWITCH_GET_SYS_INFO_PARAMS);
|
||||
break;
|
||||
|
||||
case RM_SOE_IFR_BBX_GET_TIME_INFO:
|
||||
transferSize = sizeof(NVSWITCH_GET_TIME_INFO_PARAMS);
|
||||
break;
|
||||
|
||||
case RM_SOE_IFR_BBX_GET_TEMP_DATA:
|
||||
transferSize = sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS);
|
||||
break;
|
||||
|
||||
case RM_SOE_IFR_BBX_GET_TEMP_SAMPLES:
|
||||
transferSize = sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS);
|
||||
break;
|
||||
default:
|
||||
NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType);
|
||||
return -NVL_BAD_ARGS;
|
||||
break;
|
||||
}
|
||||
|
||||
status = nvswitch_os_alloc_contig_memory(device->os_handle, &pDmaBuf, transferSize,
|
||||
(device->dma_addr_width == 32));
|
||||
if (status != NVL_SUCCESS)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: Failed to allocate contig memory. rc:%d\n", __FUNCTION__, status);
|
||||
return status;
|
||||
}
|
||||
|
||||
status = nvswitch_os_map_dma_region(device->os_handle, pDmaBuf, &dmaHandle,
|
||||
transferSize, NVSWITCH_DMA_DIR_TO_SYSMEM);
|
||||
if (status != NVL_SUCCESS)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: Failed to map DMA region. rc:%d\n", __FUNCTION__, status);
|
||||
goto nvswitch_bbx_get_data_ls10_free_and_exit;
|
||||
}
|
||||
|
||||
nvswitch_os_memset(pDmaBuf, 0, transferSize);
|
||||
|
||||
pFlcn = device->pSoe->pFlcn;
|
||||
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
|
||||
|
||||
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
|
||||
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
|
||||
bbxCmd.hdr.size = sizeof(bbxCmd);
|
||||
bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_DATA_GET;
|
||||
bbxCmd.cmd.ifr.bbxDataGet.sizeInBytes = transferSize;
|
||||
bbxCmd.cmd.ifr.bbxDataGet.dataType = dataType;
|
||||
RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxDataGet.dmaHandle, &dmaHandle);
|
||||
|
||||
status = flcnQueueCmdPostBlocking(device, pFlcn,
|
||||
(PRM_FLCN_CMD)&bbxCmd,
|
||||
NULL, // pMsg
|
||||
NULL, // pPayload
|
||||
SOE_RM_CMDQ_LOG_ID,
|
||||
&cmdSeqDesc,
|
||||
&timeout);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: BX_GET_DATA type=%d failed. rc:%d\n",
|
||||
__FUNCTION__, dataType, status);
|
||||
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
|
||||
}
|
||||
|
||||
status = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle,
|
||||
transferSize,
|
||||
NVSWITCH_DMA_DIR_TO_SYSMEM);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: Failed to sync DMA region. rc:%d\n", __FUNCTION__, status);
|
||||
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
|
||||
}
|
||||
|
||||
if (dataType == RM_SOE_IFR_BBX_GET_SYS_INFO)
|
||||
{
|
||||
NVSWITCH_GET_SYS_INFO_PARAMS bbxSysInfoData = {0};
|
||||
|
||||
nvswitch_os_memcpy((NvU8 *)&bbxSysInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS));
|
||||
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxSysInfoData, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS));
|
||||
}
|
||||
else if (dataType == RM_SOE_IFR_BBX_GET_TIME_INFO)
|
||||
{
|
||||
NVSWITCH_GET_TIME_INFO_PARAMS bbxTimeInfoData = {0};
|
||||
|
||||
nvswitch_os_memcpy((NvU8 *)&bbxTimeInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS));
|
||||
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxTimeInfoData, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS));
|
||||
}
|
||||
else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_DATA)
|
||||
{
|
||||
NVSWITCH_GET_TEMP_DATA_PARAMS *pBbxTempData = NULL;
|
||||
|
||||
pBbxTempData = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
|
||||
if (pBbxTempData == NULL)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType);
|
||||
status = -NVL_NO_MEM;
|
||||
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
|
||||
}
|
||||
|
||||
nvswitch_os_memset(pBbxTempData, 0, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
|
||||
|
||||
nvswitch_os_memcpy((NvU8 *)pBbxTempData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
|
||||
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempData, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
|
||||
|
||||
nvswitch_os_free(pBbxTempData);
|
||||
}
|
||||
else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_SAMPLES)
|
||||
{
|
||||
NVSWITCH_GET_TEMP_SAMPLES_PARAMS *pBbxTempSamples = NULL;
|
||||
|
||||
pBbxTempSamples = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
|
||||
if (pBbxTempSamples == NULL)
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType);
|
||||
status = -NVL_NO_MEM;
|
||||
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
|
||||
}
|
||||
|
||||
nvswitch_os_memset(pBbxTempSamples, 0, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
|
||||
|
||||
nvswitch_os_memcpy((NvU8 *)pBbxTempSamples, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
|
||||
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempSamples, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
|
||||
|
||||
nvswitch_os_free(pBbxTempSamples);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType);
|
||||
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
|
||||
}
|
||||
|
||||
nvswitch_bbx_get_data_ls10_unmap_and_exit:
|
||||
nvswitch_os_unmap_dma_region(device->os_handle, pDmaBuf, dmaHandle,
|
||||
transferSize, NVSWITCH_DMA_DIR_FROM_SYSMEM);
|
||||
nvswitch_bbx_get_data_ls10_free_and_exit:
|
||||
nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -42,6 +42,7 @@
|
||||
#include "ls10/gfw_ls10.h"
|
||||
|
||||
#include "nvswitch/ls10/dev_nvs_top.h"
|
||||
#include "nvswitch/ls10/ptop_discovery_ip.h"
|
||||
#include "nvswitch/ls10/dev_pri_masterstation_ip.h"
|
||||
#include "nvswitch/ls10/dev_pri_hub_sys_ip.h"
|
||||
#include "nvswitch/ls10/dev_nvlw_ip.h"
|
||||
@@ -5839,6 +5840,104 @@ nvswitch_ctrl_get_nvlink_error_threshold_ls10
|
||||
return NVL_SUCCESS;
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_check_io_sanity_ls10
|
||||
(
|
||||
nvswitch_device *device
|
||||
)
|
||||
{
|
||||
NvBool keepPolling;
|
||||
NVSWITCH_TIMEOUT timeout;
|
||||
NvU32 val;
|
||||
NvBool error = NV_FALSE;
|
||||
NvU32 sxid;
|
||||
const char *sxid_desc = NULL;
|
||||
|
||||
//
|
||||
// NOTE: MMIO discovery has not been performed so only constant BAR0 offset
|
||||
// addressing can be performed.
|
||||
//
|
||||
|
||||
// BAR0 offset 0 should always contain valid data -- unless it doesn't
|
||||
val = NVSWITCH_OFF_RD32(device, 0);
|
||||
if (val == 0)
|
||||
{
|
||||
error = NV_TRUE;
|
||||
sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE;
|
||||
sxid_desc = "Firmware recovery mode";
|
||||
}
|
||||
else if ((val == 0xFFFFFFFF) || ((val & 0xFFFF0000) == 0xBADF0000))
|
||||
{
|
||||
error = NV_TRUE;
|
||||
sxid = NVSWITCH_ERR_HW_HOST_IO_FAILURE;
|
||||
sxid_desc = "IO failure";
|
||||
}
|
||||
else if (!IS_FMODEL(device))
|
||||
{
|
||||
// check if FSP successfully started
|
||||
nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
|
||||
do
|
||||
{
|
||||
keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
|
||||
|
||||
val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS);
|
||||
if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
nvswitch_os_sleep(1);
|
||||
}
|
||||
while (keepPolling);
|
||||
if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val))
|
||||
{
|
||||
error = NV_TRUE;
|
||||
sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE;
|
||||
sxid_desc = "Firmware initialization failure";
|
||||
}
|
||||
}
|
||||
|
||||
if (error)
|
||||
{
|
||||
NVSWITCH_RAW_ERROR_LOG_TYPE report = { 0, { 0 } };
|
||||
NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }};
|
||||
NvU32 report_idx = 0;
|
||||
NvU32 i;
|
||||
|
||||
val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS);
|
||||
report.data[report_idx++] = val;
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n",
|
||||
__FUNCTION__, val);
|
||||
|
||||
for (i = 0; i <= 15; i++)
|
||||
{
|
||||
val = NVSWITCH_OFF_RD32(device,
|
||||
NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 + NV_NVLSAW_SW_SCRATCH(i));
|
||||
report_saw.data[i] = val;
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n",
|
||||
__FUNCTION__, i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++)
|
||||
{
|
||||
val = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i));
|
||||
report.data[report_idx++] = val;
|
||||
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
|
||||
__FUNCTION__, i, val);
|
||||
}
|
||||
|
||||
// Include useful scratch information for triage
|
||||
NVSWITCH_PRINT_SXID_NO_BBX(device, sxid,
|
||||
"Fatal, %s (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", sxid_desc,
|
||||
report.data[0], report.data[1], report.data[2], report.data[3], report.data[4],
|
||||
report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]);
|
||||
|
||||
return -NVL_INITIALIZATION_TOTAL_FAILURE;
|
||||
}
|
||||
|
||||
return NVL_SUCCESS;
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_read_vbios_link_entries_ls10
|
||||
(
|
||||
|
||||
@@ -30,6 +30,7 @@
|
||||
#include "flcn/haldefs_flcnable_nvswitch.h"
|
||||
#include "flcn/flcn_nvswitch.h"
|
||||
#include "soe/soe_nvswitch.h"
|
||||
#include "soe/soeififr.h"
|
||||
#include "nvVer.h"
|
||||
#include "nvlink_inband_msg.h"
|
||||
|
||||
@@ -3475,6 +3476,46 @@ _nvswitch_ctrl_get_inforom_bbx_sxid
|
||||
return nvswitch_inforom_bbx_get_sxid(device, params);
|
||||
}
|
||||
|
||||
static NvlStatus
|
||||
_nvswitch_ctrl_get_inforom_bbx_sys_info
|
||||
(
|
||||
nvswitch_device *device,
|
||||
NVSWITCH_GET_SYS_INFO_PARAMS *params
|
||||
)
|
||||
{
|
||||
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_SYS_INFO, (void *)params);
|
||||
}
|
||||
|
||||
static NvlStatus
|
||||
_nvswitch_ctrl_get_inforom_bbx_time_info
|
||||
(
|
||||
nvswitch_device *device,
|
||||
NVSWITCH_GET_TIME_INFO_PARAMS *params
|
||||
)
|
||||
{
|
||||
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TIME_INFO, (void *)params);
|
||||
}
|
||||
|
||||
static NvlStatus
|
||||
_nvswitch_ctrl_get_inforom_bbx_temp_data
|
||||
(
|
||||
nvswitch_device *device,
|
||||
NVSWITCH_GET_TEMP_DATA_PARAMS *params
|
||||
)
|
||||
{
|
||||
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_DATA, (void *)params);
|
||||
}
|
||||
|
||||
static NvlStatus
|
||||
_nvswitch_ctrl_get_inforom_bbx_temp_samples
|
||||
(
|
||||
nvswitch_device *device,
|
||||
NVSWITCH_GET_TEMP_SAMPLES_PARAMS *params
|
||||
)
|
||||
{
|
||||
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_SAMPLES, (void *)params);
|
||||
}
|
||||
|
||||
static NvlStatus
|
||||
_nvswitch_ctrl_get_nvlink_lp_counters
|
||||
(
|
||||
@@ -4666,6 +4707,15 @@ nvswitch_program_l1_scratch_reg
|
||||
device->hal.nvswitch_program_l1_scratch_reg(device, linkNumber);
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_check_io_sanity
|
||||
(
|
||||
nvswitch_device *device
|
||||
)
|
||||
{
|
||||
return device->hal.nvswitch_check_io_sanity(device);
|
||||
}
|
||||
|
||||
NvlStatus
|
||||
nvswitch_launch_ALI
|
||||
(
|
||||
@@ -5181,6 +5231,26 @@ nvswitch_lib_ctrl
|
||||
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER,
|
||||
_nvswitch_ctrl_therm_read_power,
|
||||
NVSWITCH_GET_POWER_PARAMS);
|
||||
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
|
||||
CTRL_NVSWITCH_GET_SYS_INFO,
|
||||
_nvswitch_ctrl_get_inforom_bbx_sys_info,
|
||||
NVSWITCH_GET_SYS_INFO_PARAMS,
|
||||
osPrivate, flags);
|
||||
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
|
||||
CTRL_NVSWITCH_GET_TIME_INFO,
|
||||
_nvswitch_ctrl_get_inforom_bbx_time_info,
|
||||
NVSWITCH_GET_TIME_INFO_PARAMS,
|
||||
osPrivate, flags);
|
||||
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
|
||||
CTRL_NVSWITCH_GET_TEMP_DATA,
|
||||
_nvswitch_ctrl_get_inforom_bbx_temp_data,
|
||||
NVSWITCH_GET_TEMP_DATA_PARAMS,
|
||||
osPrivate, flags);
|
||||
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
|
||||
CTRL_NVSWITCH_GET_TEMP_SAMPLES,
|
||||
_nvswitch_ctrl_get_inforom_bbx_temp_samples,
|
||||
NVSWITCH_GET_TEMP_SAMPLES_PARAMS,
|
||||
osPrivate, flags);
|
||||
|
||||
default:
|
||||
nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd);
|
||||
|
||||
Reference in New Issue
Block a user