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This commit is contained in:
Bernhard Stoeckner
2025-04-17 17:56:49 +02:00
parent c5e439fea4
commit e8113f665d
15 changed files with 47 additions and 105 deletions
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3
src/nvidia/generated/g_chipset_nvoc.h
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@@ -157,6 +157,9 @@ struct PCIECONFIGSPACEBASE
#define CL_AER_ERROR_SOURCE (CL_AER_BEGIN + 0x34)
#define CL_AER_END (CL_AER_BEGIN + 0x34)
// Advanced Error Reporting Root Error Status ERR_COR Subclass Capable Mask
#define CL_AER_ROOT_ERROR_STATUS_ERR_COR_SUBCLASS_MASK (NVBIT32(7) | NVBIT32(8))
// PCI Express Device Capabilities 2
#define CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT NVBIT(6)
#define CL_PCIE_DEV_CAP_2_ATOMIC_32BIT NVBIT(7)

8
src/nvidia/generated/g_gpu_acct_nvoc.h
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@@ -49,7 +49,6 @@ extern "C" {
#include "ctrl/ctrl0000/ctrl0000gpuacct.h"
#include "ctrl/ctrl0000/ctrl0000gpu.h" // NV0000_CTRL_GPU_MAX_ATTACHED_GPUS
#include "ctrl/ctrl2080/ctrl2080perf.h" // NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS
#include "rmapi/client.h"
typedef struct TMR_EVENT TMR_EVENT;
@@ -75,7 +74,6 @@ typedef struct
{
NvU32 procId; // Pid of the process.
NvU32 procType; // Type of the process.
struct RmClient *pClient; // Process' RmClient.
NvU32 gpuUtil; // Process's average GR engine utilization.
NvU64 sumUtil; // Running sum of process's GR engine utilization.
NvU32 fbUtil; // Process's average FB bandwidth utilization.
@@ -242,15 +240,15 @@ static inline NV_STATUS gpuacctClearAccountingData(struct GpuAccounting *arg1, N
#define gpuacctClearAccountingData(arg1, arg2, arg3) gpuacctClearAccountingData_IMPL(arg1, arg2, arg3)
#endif //__nvoc_gpu_acct_h_disabled
NV_STATUS gpuacctStartGpuAccounting_IMPL(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4, struct RmClient *arg5);
NV_STATUS gpuacctStartGpuAccounting_IMPL(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4);
#ifdef __nvoc_gpu_acct_h_disabled
static inline NV_STATUS gpuacctStartGpuAccounting(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4, struct RmClient *arg5) {
static inline NV_STATUS gpuacctStartGpuAccounting(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4) {
NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else //__nvoc_gpu_acct_h_disabled
#define gpuacctStartGpuAccounting(arg1, arg2, arg3, arg4, arg5) gpuacctStartGpuAccounting_IMPL(arg1, arg2, arg3, arg4, arg5)
#define gpuacctStartGpuAccounting(arg1, arg2, arg3, arg4) gpuacctStartGpuAccounting_IMPL(arg1, arg2, arg3, arg4)
#endif //__nvoc_gpu_acct_h_disabled
NV_STATUS gpuacctStopGpuAccounting_IMPL(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4);

10
src/nvidia/generated/g_nv_name_released.h
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@@ -5409,11 +5409,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2901, 0x1999, 0x10de, "NVIDIA B200" },
{ 0x2901, 0x199b, 0x10de, "NVIDIA B200" },
{ 0x2901, 0x20da, 0x10de, "NVIDIA B200" },
{ 0x2941, 0x2046, 0x10de, "NVIDIA HGX GB200" },
{ 0x2941, 0x20ca, 0x10de, "NVIDIA HGX GB200" },
{ 0x2941, 0x20d5, 0x10de, "NVIDIA HGX GB200" },
{ 0x2941, 0x21c9, 0x10de, "NVIDIA HGX GB200" },
{ 0x2941, 0x21ca, 0x10de, "NVIDIA HGX GB200" },
{ 0x2941, 0x2046, 0x10de, "NVIDIA GB200" },
{ 0x2941, 0x20ca, 0x10de, "NVIDIA GB200" },
{ 0x2941, 0x20d5, 0x10de, "NVIDIA GB200" },
{ 0x2941, 0x21c9, 0x10de, "NVIDIA GB200" },
{ 0x2941, 0x21ca, 0x10de, "NVIDIA GB200" },
{ 0x2B85, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090" },
{ 0x2B87, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 D" },
{ 0x2BB1, 0x204b, 0x1028, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },