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This commit is contained in:
Bernhard Stoeckner
2024-04-17 17:23:37 +02:00
parent 3bf16b890c
commit ea4c27fad6
103 changed files with 60736 additions and 56138 deletions
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3
src/common/displayport/inc/dp_connectorimpl.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -360,6 +360,7 @@ namespace DisplayPort
// the stale messages from previous discovery.
//
bool bForceClearPendingMsg;
bool bSkipFakeDeviceDpcdAccess;
Group *perHeadAttachedGroup[NV_MAX_HEADS];

5
src/common/displayport/inc/dp_deviceimpl.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -199,8 +199,9 @@ namespace DisplayPort
TriState bAsyncSDPCapable;
bool bMSAOverMSTCapable;
bool bDscPassThroughColorFormatWar;
bool bSkipFakeDeviceDpcdAccess;
DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent);
DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent, bool bSkipFakeDeviceDpcdAccess);
~DeviceImpl();
virtual bool isCableOk();

4
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -83,6 +83,7 @@
// Bug 4459839 : This regkey will enable DSC irrespective of LT status.
//
#define NV_DP_REGKEY_FORCE_DSC_ON_SINK "DP_FORCE_DSC_ON_SINK"
#define NV_DP_REGKEY_ENABLE_SKIP_DPCD_READS_WAR "DP_BUG_4478047_WAR"
//
// Data Base used to store all the regkey values.
@@ -119,6 +120,7 @@ struct DP_REGKEY_DATABASE
bool bReassessMaxLink;
bool bMSTPCONCapsReadDisabled;
bool bForceDscOnSink;
bool bSkipFakeDeviceDpcdAccess;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

30
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -166,15 +166,16 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bKeepLinkAliveMST = dpRegkeyDatabase.bOptLinkKeptAliveMst;
this->bKeepLinkAliveSST = dpRegkeyDatabase.bOptLinkKeptAliveSst;
}
this->bReportDeviceLostBeforeNew = dpRegkeyDatabase.bReportDeviceLostBeforeNew;
this->maxLinkRateFromRegkey = dpRegkeyDatabase.applyMaxLinkRateOverrides;
this->bEnableAudioBeyond48K = dpRegkeyDatabase.bAudioBeyond48kEnabled;
this->bDisableSSC = dpRegkeyDatabase.bSscDisabled;
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
this->bForceDscOnSink = dpRegkeyDatabase.bForceDscOnSink;
this->bReportDeviceLostBeforeNew = dpRegkeyDatabase.bReportDeviceLostBeforeNew;
this->maxLinkRateFromRegkey = dpRegkeyDatabase.applyMaxLinkRateOverrides;
this->bEnableAudioBeyond48K = dpRegkeyDatabase.bAudioBeyond48kEnabled;
this->bDisableSSC = dpRegkeyDatabase.bSscDisabled;
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
this->bForceDscOnSink = dpRegkeyDatabase.bForceDscOnSink;
this->bSkipFakeDeviceDpcdAccess = dpRegkeyDatabase.bSkipFakeDeviceDpcdAccess;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -478,7 +479,7 @@ create:
}
else
{
newDev = new DeviceImpl(hal, this, parent);
newDev = new DeviceImpl(hal, this, parent, this->bSkipFakeDeviceDpcdAccess);
}
if (parent)
@@ -4632,11 +4633,6 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
}
}
//
// There is no point in fallback here since we are link training
// to loweset link config that can support the mode.
//
lowestSelected.policy.setSkipFallBack(true);
bLinkTrainingSuccessful = train(lowestSelected, false);
//
// If LT failed, check if skipLT was marked. If so, clear the flag and
@@ -7022,7 +7018,7 @@ void ConnectorImpl::createFakeMuxDevice(const NvU8 *buffer, NvU32 bufferSize)
return;
}
DeviceImpl *newDev = new DeviceImpl(hal, this, NULL);
DeviceImpl *newDev = new DeviceImpl(hal, this, NULL, this->bSkipFakeDeviceDpcdAccess);
if (!newDev)
{
return;

19
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -75,7 +75,7 @@ DeviceImpl::~DeviceImpl()
}
DeviceImpl::DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent)
DeviceImpl::DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent, bool bSkipFakeDeviceDpcdAccess)
: parent(parent),
hal(hal),
activeGroup(0),
@@ -95,7 +95,8 @@ DeviceImpl::DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * pa
bIgnoreMsaCapCached(false),
bSdpExtCapable(Indeterminate),
bAsyncSDPCapable(Indeterminate),
bDscPassThroughColorFormatWar(false)
bDscPassThroughColorFormatWar(false),
bSkipFakeDeviceDpcdAccess(bSkipFakeDeviceDpcdAccess)
{
bandwidth.enum_path.dataValid = false;
shadow.plugged = false;
@@ -375,6 +376,12 @@ AuxBus::status DeviceImpl::getDpcdData(unsigned offset, NvU8 * buffer,
unsigned * sizeCompleted,
unsigned * pNakReason)
{
if (this->bSkipFakeDeviceDpcdAccess && isFakedMuxDevice())
{
DP_LOG(("Device is faked, returning nack\n"));
return AuxBus::nack;
}
if (!buffer || !sizeCompleted)
{
// default param may be NULL
@@ -403,6 +410,12 @@ AuxBus::status DeviceImpl::setDpcdData(unsigned offset, NvU8 * buffer,
unsigned * sizeCompleted,
unsigned * pNakReason)
{
if (this->bSkipFakeDeviceDpcdAccess && isFakedMuxDevice())
{
DP_LOG(("Device is faked, returning nack\n"));
return AuxBus::nack;
}
if (!buffer || !sizeCompleted)
{
// default param may be NULL

3
src/common/displayport/src/dp_evoadapter.cpp
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -96,6 +96,7 @@ const struct
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_DSC_ON_SINK, &dpRegkeyDatabase.bForceDscOnSink, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_SKIP_DPCD_READS_WAR, &dpRegkeyDatabase.bSkipFakeDeviceDpcdAccess, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

16
src/common/inc/nvBldVer.h
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@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-204"
#define NV_BUILD_CHANGELIST_NUM (34025356)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-237"
#define NV_BUILD_CHANGELIST_NUM (34145289)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-204"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34025356)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-237"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34145289)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r550_00-192"
#define NV_BUILD_CHANGELIST_NUM (34025356)
#define NV_BUILD_BRANCH_VERSION "r550_00-227"
#define NV_BUILD_CHANGELIST_NUM (34145289)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "551.86"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34025356)
#define NV_BUILD_NAME "552.19"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34145289)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "550.67"
#define NV_VERSION_STRING "550.76"
#else

19
src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,12 +26,15 @@
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE 7:6
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_NONE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x1
#endif // __gh100_dev_gc6_island_addendum_h__

3
src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -96,4 +96,5 @@
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1__SIZE_1 4 /* */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_3(i) (0x00000c50+(i)*0x4) /* RW-4A */
#endif // __ls10_dev_nvlsaw_ip_h__

7
src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip_addendum.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -52,4 +52,9 @@
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_FABRIC_MANAGER_ERROR 23:17
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_EVENT_MESSAGE_COUNT 31:24
#define NV_NVLSAW_TNVL_MODE NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_3(0)
#define NV_NVLSAW_TNVL_MODE_STATUS 0:0
#define NV_NVLSAW_TNVL_MODE_STATUS_DISABLED 0x0
#define NV_NVLSAW_TNVL_MODE_STATUS_ENABLED 0x1
#endif //__ls10_dev_nvlsaw_ip_addendum_h__

4
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -115,6 +115,7 @@ typedef struct
#define NVLINK_INBAND_FM_CAPS_BW_MODE_HALF NVBIT64(3)
#define NVLINK_INBAND_FM_CAPS_BW_MODE_3QUARTER NVBIT64(4)
#define NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2 NVBIT64(5)
#define NVLINK_INBAND_FM_CAPS_EGM_ENABLED NVBIT64(6)
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
@@ -135,7 +136,8 @@ typedef struct
NvU32 linkMaskToBeReduced; /* bit mask of unused NVLink ports for P2P */
NvU32 cliqueId; /* Fabric Clique Id */
NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */
NvU8 reserved[20]; /* For future use. Must be initialized to zero */
NvU32 gpaAddressEGMHi; /* GPA Address for EGM. Don't use if EGM support is not present in GFM */
NvU8 reserved[16]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_rsp_t;
typedef struct

90
src/common/nvswitch/interface/ctrl_dev_nvswitch.h
View File

@@ -4456,9 +4456,93 @@ typedef struct
NvU32 commandNvdmType;
NvU32 responseNvdmType;
NvU32 errorCode;
NvU8* pRspPayload;
} NVSWITCH_FSPRPC_GET_CAPS_PARAMS;
typedef enum nvswitch_device_tnvl_mode
{
NVSWITCH_DEVICE_TNVL_MODE_DISABLED = 0, // TNVL mode is disabled
NVSWITCH_DEVICE_TNVL_MODE_ENABLED, // TNVL mode is enabled
NVSWITCH_DEVICE_TNVL_MODE_FAILURE, // TNVL mode is enabled but in failure state
NVSWITCH_DEVICE_TNVL_MODE_LOCKED, // TNVL mode is enabled and locked
NVSWITCH_DEVICE_TNVL_MODE_COUNT
} NVSWITCH_DEVICE_TNVL_MODE;
/*
* CTRL_NVSWITCH_SET_DEVICE_TNVL_LOCK
*
* Control to set Trusted NVLink(TNVL) lock
*
* FM sets the TNVL lock after Fabric State is CONFIGURED
*
* Parameters:
* tnvlStatus [OUT]
* TNVL mode status of the device
*/
typedef struct nvswitch_set_device_tnvl_lock_params
{
NVSWITCH_DEVICE_TNVL_MODE tnvlStatus;
} NVSWITCH_SET_DEVICE_TNVL_LOCK_PARAMS;
/*
* CTRL_NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN
*
* Control to query NvSwitch session attestation certificate chain
*
* Parameters:
*
* attestationCertChain: [OUT]
* Attestation certificate chain for the NvSwitch queried
*
* attestationCertChainSize: [OUT]
* Actual size of attestation cert chain data
*/
#define NVSWITCH_ATTESTATION_CERT_CHAIN_MAX_SIZE 0x1400
typedef struct nvswitch_get_attestation_certificate_chain_params
{
NvU8 attestationCertChain[NVSWITCH_ATTESTATION_CERT_CHAIN_MAX_SIZE];
NvU32 attestationCertChainSize;
} NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS;
/*
* CTRL_NVSWITCH_GET_ATTESTATION_REPORT
*
* Control to query NvSwitch attestation report.
*
* Parameters:
* nonce: [IN]
* nonce
* attestationReport: [OUT]
* Attestation report of the NvSwitch queried
* attestationReportSize: [OUT]
* Actual size of the report
*/
#define NVSWITCH_NONCE_SIZE 0x20
#define NVSWITCH_ATTESTATION_REPORT_MAX_SIZE 0x2000
typedef struct nvswitch_get_attestation_report_params
{
NvU8 nonce[NVSWITCH_NONCE_SIZE];
NvU8 attestationReport[NVSWITCH_ATTESTATION_REPORT_MAX_SIZE];
NvU32 attestationReportSize;
} NVSWITCH_GET_ATTESTATION_REPORT_PARAMS;
/*
* CTRL_NVSWITCH_GET_TNVL_STATUS
*
* Control to query Trusted NVLink(TNVL) status
*
* Parameters :
* status: [OUT]
* TNVL mode status
*/
typedef struct nvswitch_get_tnvl_status_params
{
NVSWITCH_DEVICE_TNVL_MODE status;
} NVSWITCH_GET_TNVL_STATUS_PARAMS;
#define REGISTER_RW_ENGINE_RAW 0x00
#define REGISTER_RW_ENGINE_CLKS 0x10
@@ -4604,6 +4688,10 @@ typedef struct
#define CTRL_NVSWITCH_GET_NVLINK_L1_THRESHOLD 0x66
#define CTRL_NVSWITCH_SET_NVLINK_L1_THRESHOLD 0x67
#define CTRL_NVSWITCH_FSPRPC_GET_CAPS 0x68
#define CTRL_NVSWITCH_SET_DEVICE_TNVL_LOCK 0x69
#define CTRL_NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN 0x6A
#define CTRL_NVSWITCH_GET_ATTESTATION_REPORT 0x6B
#define CTRL_NVSWITCH_GET_TNVL_STATUS 0x6C
#ifdef __cplusplus
}

16
src/common/nvswitch/interface/export_nvswitch.h
View File

@@ -994,6 +994,22 @@ nvswitch_os_get_supported_register_events_params
NvBool *bUserSuppliesOsData
);
/*
* @Brief : Is TNVL mode enabled.
*
* @Description : Returns if TNVL is enabled for the device
*
* @param[in] device a reference to the device
*
* @returns NV_TRUE, if TNVL is enabled
* NV_FALSE, if TNVL is disabled
*/
NvBool
nvswitch_lib_is_tnvl_enabled
(
nvswitch_device *device
);
#ifdef __cplusplus
}
#endif

2
src/common/nvswitch/interface/ioctl_common_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

3
src/common/nvswitch/kernel/fsprpc_nvswitch.c
View File

@@ -25,9 +25,6 @@
#include "haldef_nvswitch.h"
#include "fsprpc_nvswitch.h"
#include "fsp/nvdm_payload_cmd_response.h"
#include "fsp/fsp_nvdm_format.h"
/*!
* @brief Check if FSP RM command queue is empty
*

3
src/common/nvswitch/kernel/inc/common_nvswitch.h
View File

@@ -469,6 +469,9 @@ struct nvswitch_device
// To be removed once newer vbios is on TOT.
NvBool bIsNvlinkVbiosTableVersion2;
// Trusted NVLink Mode
NVSWITCH_DEVICE_TNVL_MODE tnvl_mode;
};
#define NVSWITCH_IS_DEVICE_VALID(device) \

6
src/common/nvswitch/kernel/inc/fsprpc_nvswitch.h
View File

@@ -24,6 +24,12 @@
#ifndef _FSPRPC_NVSWITCH_H_
#define _FSPRPC_NVSWITCH_H_
#include "fsp/fsp_emem_channels.h"
#include "fsp/nvdm_payload_cmd_response.h"
#include "fsp/fsp_nvdm_format.h"
#include "fsp/fsp_mctp_format.h"
#include "fsp/fsp_tnvl_rpc.h"
#define FSP_OK (0x00U)
#define FSP_ERR_IFS_ERR_INVALID_STATE (0x9EU)
#define FSP_ERR_IFR_FILE_NOT_FOUND (0x9FU)

7
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -288,6 +288,13 @@
_op(NvlStatus, nvswitch_fsp_error_code_to_nvlstatus_map, (nvswitch_device *device, NvU32 errorCode), _arch) \
_op(NvlStatus, nvswitch_fsp_get_packet_info, (nvswitch_device *device, NvU8 *pBuffer, NvU32 size, NvU8 *pPacketState, NvU8 *pTag), _arch) \
_op(NvlStatus, nvswitch_fsprpc_get_caps, (nvswitch_device *device, NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_detect_tnvl_mode, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_tnvl_mode_enabled, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_tnvl_mode_locked, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_tnvl_get_attestation_certificate_chain, (nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_tnvl_get_attestation_report, (nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_tnvl_send_fsp_lock_config, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_tnvl_get_status, (nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params), _arch) \
NVSWITCH_HAL_FUNCTION_LIST_FEATURE_0(_op, _arch) \
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \

4
src/common/nvswitch/kernel/inc/lr10/lr10.h
View File

@@ -707,5 +707,7 @@ NvlStatus nvswitch_fsp_config_ememc_lr10(nvswitch_device *device, NvU32 offset,
NvlStatus nvswitch_fsp_write_to_emem_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size);
NvlStatus nvswitch_fsp_read_from_emem_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size);
NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_lr10(nvswitch_device *device, NvU32 errorCode);
NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params);
NvlStatus nvswitch_tnvl_get_attestation_report_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_get_status_lr10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
#endif //_LR10_H_

7
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -1051,6 +1051,13 @@ NvlStatus nvswitch_fsp_write_to_emem_ls10(nvswitch_device *device, NvU8 *pBuffer
NvlStatus nvswitch_fsp_read_from_emem_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size);
NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_ls10(nvswitch_device *device, NvU32 errorCode);
NvlStatus nvswitch_fsprpc_get_caps_ls10(nvswitch_device *device, NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params);
NvlStatus nvswitch_detect_tnvl_mode_ls10(nvswitch_device *device);
NvBool nvswitch_is_tnvl_mode_enabled_ls10(nvswitch_device *device);
NvBool nvswitch_is_tnvl_mode_locked_ls10(nvswitch_device *device);
NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params);
NvlStatus nvswitch_tnvl_get_attestation_report_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_send_fsp_lock_config_ls10(nvswitch_device *device);
NvlStatus nvswitch_tnvl_get_status_ls10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p);
NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable);

73
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -3720,6 +3720,9 @@ nvswitch_initialize_device_state_lr10
(NvU64)device->regkeys.link_enable_mask) &
((~0ULL) >> (64 - NVSWITCH_LINK_COUNT(device))));
// Detect TNVL mode
nvswitch_detect_tnvl_mode(device);
if (nvswitch_is_soe_supported(device))
{
retval = nvswitch_init_soe(device);
@@ -8107,10 +8110,80 @@ nvswitch_fsprpc_get_caps_lr10
nvswitch_device *device,
NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_detect_tnvl_mode_lr10
(
nvswitch_device *device
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
NvBool
nvswitch_is_tnvl_mode_enabled_lr10
(
nvswitch_device *device
)
{
return NV_FALSE;
}
NvBool
nvswitch_is_tnvl_mode_locked_lr10
(
nvswitch_device *device
)
{
return NV_FALSE;
}
NvlStatus
nvswitch_tnvl_get_attestation_certificate_chain_lr10
(
nvswitch_device *device,
NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params
)
{
// Not supported in LR10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_tnvl_get_attestation_report_lr10
(
nvswitch_device *device,
NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params
)
{
// Not supported in LR10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_tnvl_send_fsp_lock_config_lr10
(
nvswitch_device *device
)
{
// Not supported in LR10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_tnvl_get_status_lr10
(
nvswitch_device *device,
NVSWITCH_GET_TNVL_STATUS_PARAMS *params
)
{
// Not supported in LR10
return -NVL_ERR_NOT_SUPPORTED;
}
//
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
// macro in haldef_nvswitch.h

8
src/common/nvswitch/kernel/ls10/fsprpc_ls10.c
View File

@@ -28,12 +28,6 @@
#include "fsprpc_nvswitch.h"
#include "ls10/ls10.h"
#include "fsp/fsp_emem_channels.h"
#include "fsp/nvdm_payload_cmd_response.h"
#include "fsp/fsp_nvdm_format.h"
#include "fsp/fsp_mctp_format.h"
#include "fsp/fsp_tnvl_rpc.h"
#include "nvswitch/ls10/dev_fsp_pri.h"
/*!
@@ -346,6 +340,7 @@ nvswitch_fsp_process_nvdm_msg_ls10
switch (nvdmType)
{
case NVDM_TYPE_TNVL:
case NVDM_TYPE_FSP_RESPONSE:
status = nvswitch_fsp_process_cmd_response(device, pBuffer, size);
break;
@@ -606,7 +601,6 @@ nvswitch_fsprpc_get_caps_ls10
params->responseNvdmType = responsePayload.nvdmType;
params->commandNvdmType = responsePayload.cmdResponse.commandNvdmType;
params->errorCode = responsePayload.cmdResponse.errorCode;
params->pRspPayload = responsePayload.rspPayload;
return NVL_SUCCESS;
}

21
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -2979,6 +2979,13 @@ nvswitch_is_soe_supported_ls10
NVSWITCH_PRINT(device, WARN, "SOE can not be disabled via regkey.\n");
}
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, INFO,
"SOE is not supported when TNVL mode is locked\n");
return NV_FALSE;
}
return NV_TRUE;
}
@@ -3026,6 +3033,13 @@ nvswitch_is_inforom_supported_ls10
return NV_FALSE;
}
if (nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, INFO,
"INFOROM is not supported when TNVL mode is enabled\n");
return NV_FALSE;
}
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO,
@@ -3124,6 +3138,13 @@ nvswitch_is_smbpbi_supported_ls10
return NV_FALSE;
}
if (nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, INFO,
"SMBPBI is not supported when TNVL mode is enabled\n");
return NV_FALSE;
}
status = _nvswitch_get_bios_version(device, &version);
if (status != NVL_SUCCESS)
{

1037
src/common/nvswitch/kernel/ls10/tnvl_ls10.c Normal file
View File

File diff suppressed because it is too large Load Diff

151
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -991,6 +991,36 @@ _nvswitch_ctrl_fsprpc_get_caps
return device->hal.nvswitch_fsprpc_get_caps(device, params);
}
static NvlStatus
_nvswitch_ctrl_get_attestation_certificate_chain
(
nvswitch_device *device,
NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params
)
{
return device->hal.nvswitch_tnvl_get_attestation_certificate_chain(device, params);
}
static NvlStatus
_nvswitch_ctrl_get_attestation_report
(
nvswitch_device *device,
NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params
)
{
return device->hal.nvswitch_tnvl_get_attestation_report(device, params);
}
static NvlStatus
_nvswitch_ctrl_get_tnvl_status
(
nvswitch_device *device,
NVSWITCH_GET_TNVL_STATUS_PARAMS *params
)
{
return device->hal.nvswitch_tnvl_get_status(device, params);
}
static NvlStatus
_nvswitch_construct_soe
(
@@ -2777,6 +2807,11 @@ nvswitch_lib_register_device
device->device_fabric_state = NVSWITCH_DEVICE_FABRIC_STATE_STANDBY;
device->device_blacklist_reason = NVSWITCH_DEVICE_BLACKLIST_REASON_NONE;
//
// Initialize TNVL Mode
//
device->tnvl_mode = NVSWITCH_DEVICE_TNVL_MODE_DISABLED;
//
// Initialize HAL connectivity as early as possible so that other lib
// interfaces can work.
@@ -5888,6 +5923,101 @@ _nvswitch_ctrl_set_link_l1_threshold
return NVL_SUCCESS;
}
NvlStatus
nvswitch_detect_tnvl_mode
(
nvswitch_device *device
)
{
return device->hal.nvswitch_detect_tnvl_mode(device);
}
NvBool
nvswitch_is_tnvl_mode_enabled
(
nvswitch_device *device
)
{
return device->hal.nvswitch_is_tnvl_mode_enabled(device);
}
NvBool
nvswitch_is_tnvl_mode_locked
(
nvswitch_device *device
)
{
return device->hal.nvswitch_is_tnvl_mode_locked(device);
}
NvBool NV_API_CALL
nvswitch_lib_is_tnvl_enabled
(
nvswitch_device *device
)
{
return nvswitch_is_tnvl_mode_enabled(device);
}
NvlStatus
nvswitch_tnvl_send_fsp_lock_config
(
nvswitch_device *device
)
{
return device->hal.nvswitch_tnvl_send_fsp_lock_config(device);
}
static NvlStatus
_nvswitch_ctrl_set_device_tnvl_lock
(
nvswitch_device *device,
NVSWITCH_SET_DEVICE_TNVL_LOCK_PARAMS *p
)
{
NvlStatus status = NVL_SUCCESS;
if (!NVSWITCH_IS_DEVICE_ACCESSIBLE(device))
{
return -NVL_BAD_ARGS;
}
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL is not enabled\n",
__FUNCTION__);
return -NVL_ERR_NOT_SUPPORTED;
}
// Return failure if FM is not yet configured
if (device->device_fabric_state != NVSWITCH_DEVICE_FABRIC_STATE_CONFIGURED)
{
NVSWITCH_PRINT(device, ERROR,
"%s: FM is not configured yet\n",
__FUNCTION__);
return -NVL_ERR_INVALID_STATE;
}
//
// Disable non-fatal and legacy interrupts
// Disable commands to SOE
//
// Send lock-config command to FSP
status = nvswitch_tnvl_send_fsp_lock_config(device);
if (status == NVL_SUCCESS)
{
device->tnvl_mode = NVSWITCH_DEVICE_TNVL_MODE_LOCKED;
}
else
{
device->tnvl_mode = NVSWITCH_DEVICE_TNVL_MODE_FAILURE;
}
return status;
}
NvlStatus
nvswitch_lib_ctrl
(
@@ -6308,7 +6438,26 @@ nvswitch_lib_ctrl
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_FSPRPC_GET_CAPS,
_nvswitch_ctrl_fsprpc_get_caps,
NVSWITCH_FSPRPC_GET_CAPS_PARAMS);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_SET_DEVICE_TNVL_LOCK,
_nvswitch_ctrl_set_device_tnvl_lock,
NVSWITCH_SET_DEVICE_TNVL_LOCK_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN,
_nvswitch_ctrl_get_attestation_certificate_chain,
NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_ATTESTATION_REPORT,
_nvswitch_ctrl_get_attestation_report,
NVSWITCH_GET_ATTESTATION_REPORT_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TNVL_STATUS,
_nvswitch_ctrl_get_tnvl_status,
NVSWITCH_GET_TNVL_STATUS_PARAMS,
osPrivate, flags);
default:
nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd);
retval = -NVL_BAD_ARGS;

2
src/common/sdk/nvidia/inc/cc_drv.h
View File

@@ -94,7 +94,7 @@ typedef struct CC_CRYPTOBUNDLE_STATS {
NV_DECLARE_ALIGNED(NvU64 numEncryptionsH2D, 8);
NV_DECLARE_ALIGNED(NvU64 numEncryptionsD2H, 8);
NV_DECLARE_ALIGNED(NvU64 bytesEncryptedH2D, 8);
NV_DECLARE_ALIGNED(NvU64 bytesDecryptedD2H, 8);
NV_DECLARE_ALIGNED(NvU64 bytesEncryptedD2H, 8);
} CC_CRYPTOBUNDLE_STATS;
typedef struct CC_CRYPTOBUNDLE_STATS *PCC_CRYPTOBUNDLE_STATS;

66
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,7 @@
//
#include "nvimpshared.h"
#include "cc_drv.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
@@ -862,6 +863,19 @@ typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
NvBool bTeardown;
} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
@@ -3620,11 +3634,15 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*
* bLocalEgmEnabled[IN]
* - EGM Enablement Status that needs to be set in GSP-RM
*/
#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
NvU8 bwMode;
NvBool bLocalEgmEnabled;
} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
@@ -3757,6 +3775,50 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS
*
* This command handles key rotation for a given H2D key (and corresponding D2H key)
* by deriving new key on GSP and updating the key on relevant SEC2 or LCE.
* It also updates IVs for all channels using the key and conditionally re-enables them
* and notifies clients of key rotation status at the end.
*
* globalH2DKey : [IN]
* global h2d key to be rotated
* updatedEncryptIVMask: [OUT]
* Encrypt IV mask post IV key rotation for a given engine's kernel channel
* updatedDecryptIVMask: [OUT]
* Decrypt IV mask post IV key rotation for a given engine's kernel channel
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS (0x20800ae5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID (0xE5U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS {
NvU32 globalH2DKey;
NvU32 updatedEncryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
NvU32 updatedDecryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION
*
* This command RCs all channels that use the given key and have not reported
* idle via NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION yet.
* RM needs to RC such channels before going ahead with key rotation.
*
* globalH2DKey : [IN]
* global h2d key whose channels will be RCed
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION (0x20800ae6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0xE6U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS {
NvU32 exceptionType;
NvU32 globalH2DKey;
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE
*

3
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -124,7 +124,8 @@
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (141)
#define GPU_INIT_ERROR (143)
#define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR)
#define ROBUST_CHANNEL_KEY_ROTATION_ERROR (144)
#define ROBUST_CHANNEL_LAST_ERROR (ROBUST_CHANNEL_KEY_ROTATION_ERROR)
// Indexed CE reference

1
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -151,6 +151,7 @@ NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC
NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded")
NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value")
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

80
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -682,6 +682,8 @@ ENTRY(0x2329, 0x2032, 0x10de, "NVIDIA H20-16C"),
ENTRY(0x2329, 0x2033, 0x10de, "NVIDIA H20-24C"),
ENTRY(0x2329, 0x2034, 0x10de, "NVIDIA H20-48C"),
ENTRY(0x2329, 0x2035, 0x10de, "NVIDIA H20-96C"),
ENTRY(0x2329, 0x2047, 0x10de, "NVIDIA H20-8C"),
ENTRY(0x2329, 0x2048, 0x10de, "NVIDIA H20-32C"),
ENTRY(0x2330, 0x187A, 0x10de, "NVIDIA H100XM-1-10CME"),
ENTRY(0x2330, 0x187B, 0x10de, "NVIDIA H100XM-1-10C"),
ENTRY(0x2330, 0x187C, 0x10de, "NVIDIA H100XM-1-20C"),
@@ -856,45 +858,45 @@ ENTRY(0x26B2, 0x1835, 0x10de, "NVIDIA RTX5000-Ada-4C"),
ENTRY(0x26B2, 0x1836, 0x10de, "NVIDIA RTX5000-Ada-8C"),
ENTRY(0x26B2, 0x1837, 0x10de, "NVIDIA RTX5000-Ada-16C"),
ENTRY(0x26B2, 0x1838, 0x10de, "NVIDIA RTX5000-Ada-32C"),
ENTRY(0x26B3, 0x1958, 0x10de, "NVIDIA RTX 5880-Ada-1B"),
ENTRY(0x26B3, 0x1959, 0x10de, "NVIDIA RTX 5880-Ada-2B"),
ENTRY(0x26B3, 0x195A, 0x10de, "NVIDIA RTX 5880-Ada-1Q"),
ENTRY(0x26B3, 0x195B, 0x10de, "NVIDIA RTX 5880-Ada-2Q"),
ENTRY(0x26B3, 0x195C, 0x10de, "NVIDIA RTX 5880-Ada-3Q"),
ENTRY(0x26B3, 0x195D, 0x10de, "NVIDIA RTX 5880-Ada-4Q"),
ENTRY(0x26B3, 0x195E, 0x10de, "NVIDIA RTX 5880-Ada-6Q"),
ENTRY(0x26B3, 0x195F, 0x10de, "NVIDIA RTX 5880-Ada-8Q"),
ENTRY(0x26B3, 0x1960, 0x10de, "NVIDIA RTX 5880-Ada-12Q"),
ENTRY(0x26B3, 0x1961, 0x10de, "NVIDIA RTX 5880-Ada-16Q"),
ENTRY(0x26B3, 0x1962, 0x10de, "NVIDIA RTX 5880-Ada-24Q"),
ENTRY(0x26B3, 0x1963, 0x10de, "NVIDIA RTX 5880-Ada-48Q"),
ENTRY(0x26B3, 0x1964, 0x10de, "NVIDIA RTX 5880-Ada-1A"),
ENTRY(0x26B3, 0x1965, 0x10de, "NVIDIA RTX 5880-Ada-2A"),
ENTRY(0x26B3, 0x1966, 0x10de, "NVIDIA RTX 5880-Ada-3A"),
ENTRY(0x26B3, 0x1967, 0x10de, "NVIDIA RTX 5880-Ada-4A"),
ENTRY(0x26B3, 0x1968, 0x10de, "NVIDIA RTX 5880-Ada-6A"),
ENTRY(0x26B3, 0x1969, 0x10de, "NVIDIA RTX 5880-Ada-8A"),
ENTRY(0x26B3, 0x196A, 0x10de, "NVIDIA RTX 5880-Ada-12A"),
ENTRY(0x26B3, 0x196B, 0x10de, "NVIDIA RTX 5880-Ada-16A"),
ENTRY(0x26B3, 0x196C, 0x10de, "NVIDIA RTX 5880-Ada-24A"),
ENTRY(0x26B3, 0x196D, 0x10de, "NVIDIA RTX 5880-Ada-48A"),
ENTRY(0x26B3, 0x196E, 0x10de, "NVIDIA RTX 5880-Ada-1"),
ENTRY(0x26B3, 0x196F, 0x10de, "NVIDIA RTX 5880-Ada-2"),
ENTRY(0x26B3, 0x1970, 0x10de, "NVIDIA RTX 5880-Ada-3"),
ENTRY(0x26B3, 0x1971, 0x10de, "NVIDIA RTX 5880-Ada-4"),
ENTRY(0x26B3, 0x1972, 0x10de, "NVIDIA RTX 5880-Ada-6"),
ENTRY(0x26B3, 0x1973, 0x10de, "NVIDIA RTX 5880-Ada-8"),
ENTRY(0x26B3, 0x1974, 0x10de, "NVIDIA RTX 5880-Ada-12"),
ENTRY(0x26B3, 0x1975, 0x10de, "NVIDIA RTX 5880-Ada-16"),
ENTRY(0x26B3, 0x1976, 0x10de, "NVIDIA RTX 5880-Ada-24"),
ENTRY(0x26B3, 0x1977, 0x10de, "NVIDIA RTX 5880-Ada-48"),
ENTRY(0x26B3, 0x1978, 0x10de, "NVIDIA RTX 5880-Ada-4C"),
ENTRY(0x26B3, 0x1979, 0x10de, "NVIDIA RTX 5880-Ada-6C"),
ENTRY(0x26B3, 0x197A, 0x10de, "NVIDIA RTX 5880-Ada-8C"),
ENTRY(0x26B3, 0x197B, 0x10de, "NVIDIA RTX 5880-Ada-12C"),
ENTRY(0x26B3, 0x197C, 0x10de, "NVIDIA RTX 5880-Ada-16C"),
ENTRY(0x26B3, 0x197D, 0x10de, "NVIDIA RTX 5880-Ada-24C"),
ENTRY(0x26B3, 0x197E, 0x10de, "NVIDIA RTX 5880-Ada-48C"),
ENTRY(0x26B3, 0x1958, 0x10de, "NVIDIA RTX5880-Ada-1B"),
ENTRY(0x26B3, 0x1959, 0x10de, "NVIDIA RTX5880-Ada-2B"),
ENTRY(0x26B3, 0x195A, 0x10de, "NVIDIA RTX5880-Ada-1Q"),
ENTRY(0x26B3, 0x195B, 0x10de, "NVIDIA RTX5880-Ada-2Q"),
ENTRY(0x26B3, 0x195C, 0x10de, "NVIDIA RTX5880-Ada-3Q"),
ENTRY(0x26B3, 0x195D, 0x10de, "NVIDIA RTX5880-Ada-4Q"),
ENTRY(0x26B3, 0x195E, 0x10de, "NVIDIA RTX5880-Ada-6Q"),
ENTRY(0x26B3, 0x195F, 0x10de, "NVIDIA RTX5880-Ada-8Q"),
ENTRY(0x26B3, 0x1960, 0x10de, "NVIDIA RTX5880-Ada-12Q"),
ENTRY(0x26B3, 0x1961, 0x10de, "NVIDIA RTX5880-Ada-16Q"),
ENTRY(0x26B3, 0x1962, 0x10de, "NVIDIA RTX5880-Ada-24Q"),
ENTRY(0x26B3, 0x1963, 0x10de, "NVIDIA RTX5880-Ada-48Q"),
ENTRY(0x26B3, 0x1964, 0x10de, "NVIDIA RTX5880-Ada-1A"),
ENTRY(0x26B3, 0x1965, 0x10de, "NVIDIA RTX5880-Ada-2A"),
ENTRY(0x26B3, 0x1966, 0x10de, "NVIDIA RTX5880-Ada-3A"),
ENTRY(0x26B3, 0x1967, 0x10de, "NVIDIA RTX5880-Ada-4A"),
ENTRY(0x26B3, 0x1968, 0x10de, "NVIDIA RTX5880-Ada-6A"),
ENTRY(0x26B3, 0x1969, 0x10de, "NVIDIA RTX5880-Ada-8A"),
ENTRY(0x26B3, 0x196A, 0x10de, "NVIDIA RTX5880-Ada-12A"),
ENTRY(0x26B3, 0x196B, 0x10de, "NVIDIA RTX5880-Ada-16A"),
ENTRY(0x26B3, 0x196C, 0x10de, "NVIDIA RTX5880-Ada-24A"),
ENTRY(0x26B3, 0x196D, 0x10de, "NVIDIA RTX5880-Ada-48A"),
ENTRY(0x26B3, 0x196E, 0x10de, "NVIDIA RTX5880-Ada-1"),
ENTRY(0x26B3, 0x196F, 0x10de, "NVIDIA RTX5880-Ada-2"),
ENTRY(0x26B3, 0x1970, 0x10de, "NVIDIA RTX5880-Ada-3"),
ENTRY(0x26B3, 0x1971, 0x10de, "NVIDIA RTX5880-Ada-4"),
ENTRY(0x26B3, 0x1972, 0x10de, "NVIDIA RTX5880-Ada-6"),
ENTRY(0x26B3, 0x1973, 0x10de, "NVIDIA RTX5880-Ada-8"),
ENTRY(0x26B3, 0x1974, 0x10de, "NVIDIA RTX5880-Ada-12"),
ENTRY(0x26B3, 0x1975, 0x10de, "NVIDIA RTX5880-Ada-16"),
ENTRY(0x26B3, 0x1976, 0x10de, "NVIDIA RTX5880-Ada-24"),
ENTRY(0x26B3, 0x1977, 0x10de, "NVIDIA RTX5880-Ada-48"),
ENTRY(0x26B3, 0x1978, 0x10de, "NVIDIA RTX5880-Ada-4C"),
ENTRY(0x26B3, 0x1979, 0x10de, "NVIDIA RTX5880-Ada-6C"),
ENTRY(0x26B3, 0x197A, 0x10de, "NVIDIA RTX5880-Ada-8C"),
ENTRY(0x26B3, 0x197B, 0x10de, "NVIDIA RTX5880-Ada-12C"),
ENTRY(0x26B3, 0x197C, 0x10de, "NVIDIA RTX5880-Ada-16C"),
ENTRY(0x26B3, 0x197D, 0x10de, "NVIDIA RTX5880-Ada-24C"),
ENTRY(0x26B3, 0x197E, 0x10de, "NVIDIA RTX5880-Ada-48C"),
ENTRY(0x26B5, 0x176D, 0x10de, "NVIDIA L40-1B"),
ENTRY(0x26B5, 0x176E, 0x10de, "NVIDIA L40-2B"),
ENTRY(0x26B5, 0x176F, 0x10de, "NVIDIA L40-1Q"),

1
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -21,6 +21,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x2330, 0x16C0, 0x2330, 0x16C1 },
{ 0x2336, 0x16C2, 0x2330, 0x16C1 },
{ 0x26BA, 0x1990, 0x26BA, 0x1957 },
};
for (NvU32 i = 0; i < (sizeof(vgpu_aliases) / sizeof(struct vgpu_alias_details)); ++i) {

6
src/common/shared/inc/nvdevid.h
View File

@@ -448,9 +448,13 @@
// Cavium, Inc. CN99xx [ThunderX2] [177d:af00]
#define CAVIUM_X2_DEVID 0xAF00
// Lenovo Tomcat Workstation
// Lenovo Tomcat/Falcon/Hornet Workstations
#define LENOVO_TOMCAT_DEVID 0x1B81
#define LENOVO_TOMCAT_SSDEVID 0x104e
#define LENOVO_FALCON_DEVID 0x7A8A
#define LENOVO_FALCON_SSDEVID 0x1055
#define LENOVO_HORNET_DEVID 0x7A8A
#define LENOVO_HORNET_SSDEVID 0x1056
// NVIDIA C51
#define NVIDIA_C51_DEVICE_ID_MIN 0x2F0