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This commit is contained in:
Bernhard Stoeckner
2024-04-17 17:23:37 +02:00
parent 3bf16b890c
commit ea4c27fad6
103 changed files with 60736 additions and 56138 deletions
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2
src/common/sdk/nvidia/inc/cc_drv.h
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@@ -94,7 +94,7 @@ typedef struct CC_CRYPTOBUNDLE_STATS {
NV_DECLARE_ALIGNED(NvU64 numEncryptionsH2D, 8);
NV_DECLARE_ALIGNED(NvU64 numEncryptionsD2H, 8);
NV_DECLARE_ALIGNED(NvU64 bytesEncryptedH2D, 8);
NV_DECLARE_ALIGNED(NvU64 bytesDecryptedD2H, 8);
NV_DECLARE_ALIGNED(NvU64 bytesEncryptedD2H, 8);
} CC_CRYPTOBUNDLE_STATS;
typedef struct CC_CRYPTOBUNDLE_STATS *PCC_CRYPTOBUNDLE_STATS;

66
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,7 @@
//
#include "nvimpshared.h"
#include "cc_drv.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
@@ -862,6 +863,19 @@ typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
NvBool bTeardown;
} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
@@ -3620,11 +3634,15 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*
* bLocalEgmEnabled[IN]
* - EGM Enablement Status that needs to be set in GSP-RM
*/
#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
NvU8 bwMode;
NvBool bLocalEgmEnabled;
} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
@@ -3757,6 +3775,50 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS
*
* This command handles key rotation for a given H2D key (and corresponding D2H key)
* by deriving new key on GSP and updating the key on relevant SEC2 or LCE.
* It also updates IVs for all channels using the key and conditionally re-enables them
* and notifies clients of key rotation status at the end.
*
* globalH2DKey : [IN]
* global h2d key to be rotated
* updatedEncryptIVMask: [OUT]
* Encrypt IV mask post IV key rotation for a given engine's kernel channel
* updatedDecryptIVMask: [OUT]
* Decrypt IV mask post IV key rotation for a given engine's kernel channel
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS (0x20800ae5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID (0xE5U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS {
NvU32 globalH2DKey;
NvU32 updatedEncryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
NvU32 updatedDecryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION
*
* This command RCs all channels that use the given key and have not reported
* idle via NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION yet.
* RM needs to RC such channels before going ahead with key rotation.
*
* globalH2DKey : [IN]
* global h2d key whose channels will be RCed
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION (0x20800ae6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0xE6U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS {
NvU32 exceptionType;
NvU32 globalH2DKey;
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE
*

3
src/common/sdk/nvidia/inc/nverror.h
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@@ -124,7 +124,8 @@
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (141)
#define GPU_INIT_ERROR (143)
#define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR)
#define ROBUST_CHANNEL_KEY_ROTATION_ERROR (144)
#define ROBUST_CHANNEL_LAST_ERROR (ROBUST_CHANNEL_KEY_ROTATION_ERROR)
// Indexed CE reference

1
src/common/sdk/nvidia/inc/nvstatuscodes.h
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@@ -151,6 +151,7 @@ NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC
NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded")
NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value")
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")