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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -31,6 +31,7 @@
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//
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#include "nvimpshared.h"
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#include "cc_drv.h"
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#include "ctrl/ctrl2080/ctrl2080base.h"
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#include "ctrl/ctrl2080/ctrl2080gpu.h"
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@@ -862,6 +863,19 @@ typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080
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#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
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typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
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NvBool bTeardown;
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} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
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typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
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NvBool bPerSubCtxheaderSupported;
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} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
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@@ -3620,11 +3634,15 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
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*
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* bwMode[IN]
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* - Nvlink Bandwidth mode
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*
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* bLocalEgmEnabled[IN]
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* - EGM Enablement Status that needs to be set in GSP-RM
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*/
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#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
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typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
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NvU8 bwMode;
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NvU8 bwMode;
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NvBool bLocalEgmEnabled;
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} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
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/*!
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@@ -3757,6 +3775,50 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
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NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
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} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
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/*!
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* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS
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*
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* This command handles key rotation for a given H2D key (and corresponding D2H key)
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* by deriving new key on GSP and updating the key on relevant SEC2 or LCE.
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* It also updates IVs for all channels using the key and conditionally re-enables them
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* and notifies clients of key rotation status at the end.
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*
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* globalH2DKey : [IN]
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* global h2d key to be rotated
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* updatedEncryptIVMask: [OUT]
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* Encrypt IV mask post IV key rotation for a given engine's kernel channel
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* updatedDecryptIVMask: [OUT]
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* Decrypt IV mask post IV key rotation for a given engine's kernel channel
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*/
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#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS (0x20800ae5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID (0xE5U)
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typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS {
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NvU32 globalH2DKey;
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NvU32 updatedEncryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
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NvU32 updatedDecryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
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} NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS;
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/*!
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* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION
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*
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* This command RCs all channels that use the given key and have not reported
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* idle via NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION yet.
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* RM needs to RC such channels before going ahead with key rotation.
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*
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* globalH2DKey : [IN]
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* global h2d key whose channels will be RCed
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*/
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#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION (0x20800ae6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0xE6U)
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typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS {
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NvU32 exceptionType;
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NvU32 globalH2DKey;
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} NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS;
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/*!
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* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE
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*
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