mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-03 20:29:53 +00:00
535.43.02
This commit is contained in:
Andy Ritger
@@ -1,25 +1,25 @@
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/*******************************************************************************
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Copyright (c) 2014 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _clc06f_h_
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#define _clc06f_h_
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@@ -30,10 +30,47 @@ extern "C" {
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#include "nvtypes.h"
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/* class PASCAL_CHANNEL_GPFIFO */
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/*
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* Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
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* chapter "User Control Registers". It is documented as device NV_UDMA.
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* The GPFIFO format itself is also documented in dev_pbdma.ref,
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* NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
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* chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
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*
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* Note there is no .mfs file for this class.
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*/
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#define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F)
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/* class PASCAL_CHANNEL_GPFIFO_A */
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#define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA
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/* dma flow control data structure */
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typedef volatile struct Nvc06fControl_struct {
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NvU32 Ignored00[0x010]; /* 0000-003f*/
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NvU32 Put; /* put offset, read/write 0040-0043*/
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NvU32 Get; /* get offset, read only 0044-0047*/
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NvU32 Reference; /* reference value, read only 0048-004b*/
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NvU32 PutHi; /* high order put offset bits 004c-004f*/
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NvU32 Ignored01[0x002]; /* 0050-0057*/
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NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
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NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
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NvU32 GetHi; /* high order get offset bits 0060-0063*/
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NvU32 Ignored02[0x007]; /* 0064-007f*/
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NvU32 Ignored03; /* used to be engine yield 0080-0083*/
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NvU32 Ignored04[0x001]; /* 0084-0087*/
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NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
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NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
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NvU32 Ignored05[0x5c];
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} Nvc06fControl, PascalAControlGPFifo;
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/* fields and values */
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#define NVC06F_NUMBER_OF_SUBCHANNELS (8)
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#define NVC06F_SET_OBJECT (0x00000000)
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#define NVC06F_SET_OBJECT_NVCLASS 15:0
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#define NVC06F_SET_OBJECT_ENGINE 20:16
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#define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f
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#define NVC06F_ILLEGAL (0x00000004)
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#define NVC06F_ILLEGAL_HANDLE 31:0
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#define NVC06F_NOP (0x00000008)
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#define NVC06F_NOP_HANDLE 31:0
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#define NVC06F_SEMAPHOREA (0x00000010)
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@@ -47,54 +84,33 @@ extern "C" {
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#define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
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#define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002
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#define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
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#define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
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#define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
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#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12
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#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
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#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
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/* GPFIFO entry format */
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#define NVC06F_GP_ENTRY__SIZE 8
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#define NVC06F_GP_ENTRY0_GET 31:2
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#define NVC06F_GP_ENTRY0_OPERAND 31:0
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#define NVC06F_GP_ENTRY1_GET_HI 7:0
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#define NVC06F_GP_ENTRY1_PRIV 8:8
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#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000
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#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001
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#define NVC06F_GP_ENTRY1_LEVEL 9:9
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#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000
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#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
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#define NVC06F_GP_ENTRY1_LENGTH 30:10
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/* dma incrementing method format */
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#define NVC06F_DMA_INCR_ADDRESS 11:0
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#define NVC06F_DMA_INCR_SUBCHANNEL 15:13
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#define NVC06F_DMA_INCR_COUNT 28:16
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#define NVC06F_DMA_INCR_OPCODE 31:29
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#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001)
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#define NVC06F_DMA_INCR_DATA 31:0
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/* dma non-incrementing method format */
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#define NVC06F_DMA_NONINCR_ADDRESS 11:0
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#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13
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#define NVC06F_DMA_NONINCR_COUNT 28:16
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#define NVC06F_DMA_NONINCR_OPCODE 31:29
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#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
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#define NVC06F_DMA_NONINCR_DATA 31:0
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/* dma increment-once method format */
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#define NVC06F_DMA_ONEINCR_ADDRESS 11:0
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#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13
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#define NVC06F_DMA_ONEINCR_COUNT 28:16
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#define NVC06F_DMA_ONEINCR_OPCODE 31:29
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#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
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#define NVC06F_DMA_ONEINCR_DATA 31:0
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/* dma no-operation format */
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#define NVC06F_DMA_NOP (0x00000000)
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/* dma immediate-data format */
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#define NVC06F_DMA_IMMD_ADDRESS 11:0
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#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13
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#define NVC06F_DMA_IMMD_DATA 28:16
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#define NVC06F_DMA_IMMD_OPCODE 31:29
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#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004)
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#define NVC06F_SEMAPHORED_RELEASE_WFI 20:20
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#define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
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#define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
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#define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24
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#define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
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#define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
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#define NVC06F_SEMAPHORED_REDUCTION 30:27
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#define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000
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#define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001
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#define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002
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#define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003
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#define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004
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#define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005
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#define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006
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#define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007
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#define NVC06F_SEMAPHORED_FORMAT 31:31
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#define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000
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#define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
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#define NVC06F_NON_STALL_INTERRUPT (0x00000020)
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#define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0
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#define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
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#define NVC06F_FB_FLUSH_HANDLE 31:0
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// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
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// specifying the page address for a targeted TLB invalidate and the uTLB for
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// a targeted REPLAY_CANCEL for UVM.
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@@ -153,19 +169,142 @@ extern "C" {
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#define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
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#define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
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// CLEAN_LINES is an alias for Tegra/GPU IP usage
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#define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
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// This B alias is confusing but it was missed as part of the update. Left here
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// for compatibility.
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#define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
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#define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
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#define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
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#define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
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#define NVC06F_SET_REFERENCE (0x00000050)
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#define NVC06F_SET_REFERENCE_COUNT 31:0
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// Syncpoint methods are only available on Tegra parts. Attempting to use
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// them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD.
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#define NVC06F_SYNCPOINTA (0x00000070)
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#define NVC06F_SYNCPOINTA_PAYLOAD 31:0
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#define NVC06F_SYNCPOINTB (0x00000074)
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#define NVC06F_SYNCPOINTB_OPERATION 0:0
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#define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000
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#define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001
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#define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4
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#define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000
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#define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001
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#define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8
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#define NVC06F_WFI (0x00000078)
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#define NVC06F_WFI_SCOPE 0:0
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#define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
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#define NVC06F_WFI_SCOPE_ALL 0x00000001
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#define NVC06F_CRC_CHECK (0x0000007c)
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#define NVC06F_CRC_CHECK_VALUE 31:0
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#define NVC06F_YIELD (0x00000080)
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#define NVC06F_YIELD_OP 1:0
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#define NVC06F_YIELD_OP_NOP 0x00000000
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#define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001
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#define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002
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#define NVC06F_YIELD_OP_TSG 0x00000003
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/* GPFIFO entry format */
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#define NVC06F_GP_ENTRY__SIZE 8
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#define NVC06F_GP_ENTRY0_FETCH 0:0
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#define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
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#define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
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#define NVC06F_GP_ENTRY0_GET 31:2
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#define NVC06F_GP_ENTRY0_OPERAND 31:0
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#define NVC06F_GP_ENTRY1_GET_HI 7:0
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#define NVC06F_GP_ENTRY1_PRIV 8:8
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#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000
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#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001
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#define NVC06F_GP_ENTRY1_LEVEL 9:9
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#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000
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#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
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#define NVC06F_GP_ENTRY1_LENGTH 30:10
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#define NVC06F_GP_ENTRY1_SYNC 31:31
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#define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000
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#define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001
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#define NVC06F_GP_ENTRY1_OPCODE 7:0
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#define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000
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#define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
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#define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
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#define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
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/* dma method formats */
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#define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2
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#define NVC06F_DMA_METHOD_ADDRESS 11:0
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#define NVC06F_DMA_SUBDEVICE_MASK 15:4
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#define NVC06F_DMA_METHOD_SUBCHANNEL 15:13
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#define NVC06F_DMA_TERT_OP 17:16
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#define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
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#define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
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#define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
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#define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
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#define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
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#define NVC06F_DMA_METHOD_COUNT_OLD 28:18
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#define NVC06F_DMA_METHOD_COUNT 28:16
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#define NVC06F_DMA_IMMD_DATA 28:16
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#define NVC06F_DMA_SEC_OP 31:29
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#define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
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#define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001)
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#define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
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#define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
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#define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
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#define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005)
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#define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006)
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#define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
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/* dma incrementing method format */
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#define NVC06F_DMA_INCR_ADDRESS 11:0
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#define NVC06F_DMA_INCR_SUBCHANNEL 15:13
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#define NVC06F_DMA_INCR_COUNT 28:16
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#define NVC06F_DMA_INCR_OPCODE 31:29
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#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001)
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#define NVC06F_DMA_INCR_DATA 31:0
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/* dma non-incrementing method format */
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#define NVC06F_DMA_NONINCR_ADDRESS 11:0
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#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13
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#define NVC06F_DMA_NONINCR_COUNT 28:16
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#define NVC06F_DMA_NONINCR_OPCODE 31:29
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#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
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#define NVC06F_DMA_NONINCR_DATA 31:0
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/* dma increment-once method format */
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#define NVC06F_DMA_ONEINCR_ADDRESS 11:0
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#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13
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#define NVC06F_DMA_ONEINCR_COUNT 28:16
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#define NVC06F_DMA_ONEINCR_OPCODE 31:29
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#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
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#define NVC06F_DMA_ONEINCR_DATA 31:0
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/* dma no-operation format */
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#define NVC06F_DMA_NOP (0x00000000)
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/* dma immediate-data format */
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#define NVC06F_DMA_IMMD_ADDRESS 11:0
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#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13
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#define NVC06F_DMA_IMMD_DATA 28:16
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#define NVC06F_DMA_IMMD_OPCODE 31:29
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#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004)
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/* dma set sub-device mask format */
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#define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
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#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
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#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
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/* dma store sub-device mask format */
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#define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
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#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
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#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
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/* dma use sub-device mask format */
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#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
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#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
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/* dma end-segment format */
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#define NVC06F_DMA_ENDSEG_OPCODE 31:29
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#define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
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/* dma legacy incrementing/non-incrementing formats */
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#define NVC06F_DMA_ADDRESS 12:2
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#define NVC06F_DMA_SUBCH 15:13
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#define NVC06F_DMA_OPCODE3 17:16
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#define NVC06F_DMA_OPCODE3_NONE (0x00000000)
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#define NVC06F_DMA_COUNT 28:18
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#define NVC06F_DMA_OPCODE 31:29
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#define NVC06F_DMA_OPCODE_METHOD (0x00000000)
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#define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002)
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#define NVC06F_DMA_DATA 31:0
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#ifdef __cplusplus
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}; /* extern "C" */
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#endif
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Block a user