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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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11
src/common/displayport/inc/dp_connectorimpl.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -125,6 +125,7 @@ namespace DisplayPort
bool bPConConnected; // HDMI2.1-Protocol Converter (Support SRC control mode) connected.
bool bSkipAssessLinkForPCon; // Skip assessLink() for PCON. DD will call assessFRLLink later.
bool bHdcpAuthOnlyOnDemand; // True if only initiate Hdcp authentication on demand and MST won't auto-trigger authenticate at device attach.
bool bReassessMaxLink; // Retry assessLink() if the first assessed link config is lower than the panel max config.
bool constructorFailed;
@@ -333,6 +334,14 @@ namespace DisplayPort
//
bool bPowerDownPhyBeforeD3;
//
// Reset the MSTM_CTRL registers on Synaptics branch device irrespective of
// IRQ VECTOR register having stale message. Synaptics device needs to reset
// the topology before issue of new LAM message if previous LAM was not finished
// bug 3928070
//
bool bForceClearPendingMsg;
void sharedInit();
ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);

1
src/common/displayport/inc/dp_deviceimpl.h
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@@ -39,6 +39,7 @@
namespace DisplayPort
{
#define PREDEFINED_DSC_MST_BPPX16 160;
#define MAX_DSC_COMPRESSION_BPPX16 128;
#define HDCP_BCAPS_DDC_OFFSET 0x40
#define HDCP_BCAPS_DDC_EN_BIT 0x80
#define HDCP_BCAPS_DP_EN_BIT 0x01

3
src/common/displayport/inc/dp_evoadapter.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -160,6 +160,7 @@ namespace DisplayPort
bool _applyLinkBwOverrideWarRegVal;
bool _isDynamicMuxCapable;
bool _enableMSAOverrideOverMST;
bool _enableFecCheckForDDS;
bool _isLTPhyRepeaterSupported;
//

22
src/common/displayport/inc/dp_linkconfig.h
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@@ -36,6 +36,7 @@
#include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE
#include "displayport.h"
namespace DisplayPort
{
typedef NvU64 LinkRate;
@@ -45,7 +46,7 @@ namespace DisplayPort
public:
// Store link rate in multipler of 270MBPS to save space
NvU8 element[NV_DPCD_SUPPORTED_LINK_RATES__SIZE];
NvU8 entries;
NvU8 entries;
LinkRates()
{
@@ -143,18 +144,17 @@ namespace DisplayPort
totalUsableTimeslots = totalTimeslots - 1
};
// in MBps
// in 10bps
enum
{
RBR = 162000000,
EDP_2_16GHZ = 216000000,
EDP_2_43GHZ = 243000000,
HBR = 270000000,
EDP_3_24GHZ = 324000000,
EDP_4_32GHZ = 432000000,
HBR2 = 540000000,
EDP_6_75GHZ = 675000000,
HBR3 = 810000000
RBR = 162000000,
EDP_2_16GHZ = 216000000,
EDP_2_43GHZ = 243000000,
HBR = 270000000,
EDP_3_24GHZ = 324000000,
EDP_4_32GHZ = 432000000,
HBR2 = 540000000,
HBR3 = 810000000
};
struct HDCPState

14
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,15 +59,25 @@
#define NV_DP_REGKEY_FORCE_EDP_ILR "DP_BYPASS_EDP_ILR_REV_CHECK"
// Regkey to make sure enable FEC only when RM notified sink successfully
#define NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL "DP_DDS_CHECK_FEC_TO_ENABLE"
// Message to power down video stream before power down link (set D3)
#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY"
//
// Regkey to re-assess max link if the first assessed link config
// is lower than the panel max
//
#define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK"
//
// DSC capability of downstream device should be decided based on device's own
// and its parent's DSC capability.
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -100,6 +110,8 @@ struct DP_REGKEY_DATABASE
bool bBypassEDPRevCheck;
bool bDscMstCapBug3143315;
bool bPowerDownPhyBeforeD3;
bool bCheckFECForDynamicMuxDSCPanel;
bool bReassessMaxLink;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

5
src/common/displayport/src/dp_configcaps.cpp
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -739,7 +739,7 @@ struct DPCDHALImpl : DPCDHAL
}
return bSDPExtnForColorimetry;
}
virtual bool getRootAsyncSDPSupported()
{
NvU8 byte = 0;
@@ -758,7 +758,6 @@ struct DPCDHALImpl : DPCDHAL
return true;
}
virtual AuxRetry::status setOuiSource(unsigned ouiId, const char * model, size_t modelNameLength, NvU8 chipRevision)
{
NvU8 ouiBuffer[16];

152
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -195,6 +195,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -691,6 +692,25 @@ create:
}
}
if (newDev->peerDevice == Dongle)
{
// For Dongle, we need to read detailed port caps if DPCD access is available on DP 1.4+.
if (newDev->isAtLeastVersion(1,4))
{
newDev->getPCONCaps(&(newDev->pconCaps));
}
//
// If dongle does not have DPCD access but it is native PCON with Virtual peer support,
// we can get dongle port capabilities from parent VP DPCD detailed port descriptors.
//
else if (newDev->parent && (newDev->parent)->isVirtualPeerDevice())
{
newDev->parent->getPCONCaps(&(newDev->pconCaps));
newDev->connectorType = newDev->parent->getConnectorType();
}
}
// Read panel replay capabilities
newDev->getPanelReplayCaps();
@@ -1107,6 +1127,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
{
DP_ASSERT( compoundQueryActive );
ModesetInfo localModesetInfo = modesetParams.modesetInfo;
NVT_STATUS result;
compoundQueryCount++;
@@ -1202,6 +1223,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
NvU64 availableBandwidthBitsPerSecond = 0;
unsigned PPS[DSC_MAX_PPS_SIZE_DWORD];
unsigned bitsPerPixelX16 = 0;
bool bDscBppForced = false;
if (!pDscParams->bitsPerPixelX16)
{
@@ -1211,6 +1233,10 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
//
pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16;
}
else
{
bDscBppForced = true;
}
bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
@@ -1283,10 +1309,25 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth;
warData.connectorType = DSC_DP;
if ((DSC_GeneratePPS(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16))) != NVT_STATUS_SUCCESS)
result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16));
// Try max dsc compression bpp = 8 once to check if that can support that mode.
if (result != NVT_STATUS_SUCCESS && !bDscBppForced)
{
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16));
}
if (result != NVT_STATUS_SUCCESS)
{
//
// If generating PPS failed
@@ -1325,7 +1366,50 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
localModesetInfo.bEnableDsc = true;
localModesetInfo.depth = bitsPerPixelX16;
if (dev->devDoingDscDecompression != dev)
if (dev->peerDevice == Dongle && dev->connectorType == connectorHDMI)
{
//
// For DP2HDMI PCON, if FRL BW is available in detailed caps,
// we need to check if we have enough BW for the stream on FRL link.
//
if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0)
{
NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000);
if (requiredBW > availableBw)
{
compoundQueryResult = false;
pDscParams->bEnableDsc = false;
return false;
}
}
//
// If DP2HDMI PCON does not support FRL, but advertises TMDS
// Character clock rate on detailed caps, we need to honor that.
//
else if (dev->pconCaps.maxTmdsClkRate != 0)
{
NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate);
NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
if (modesetParams.colorFormat == dpColorFormat_YCbCr420)
{
if (maxTmdsClkRateU64 < ((requireBw/24)/2))
{
compoundQueryResult = false;
return false;
}
}
else
{
if (maxTmdsClkRateU64 < (requireBw/24))
{
compoundQueryResult = false;
return false;
}
}
}
}
else if (dev->devDoingDscDecompression != dev)
{
//
// Device's parent is doing DSC decompression so we need to check
@@ -2696,8 +2780,15 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
DP_ASSERT(!this->isLinkQuiesced && "TMDS is attached, NABegin is impossible!");
//
// Update the FEC enabled flag according to the mode requested.
//
// In MST config, if one panel needs DSC/FEC and the other one does not,
// we still need to keep FEC enabled on the connector since at least one
// stream needs it.
//
this->bFECEnable |= bEnableFEC;
highestAssessedLC.enableFEC(this->bFECEnable);
if (main->isEDP())
@@ -4653,6 +4744,7 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
{
LinkTrainingType preferredTrainingType = trainType;
bool result;
bool bEnableFecOnSor;
//
// Validate link config against caps
//
@@ -4739,14 +4831,21 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
this->hal->setDirtyLinkStatus(true);
// We don't need post LQA while powering down the lanes.
if ((lConfig.lanes != 0) &&
hal->isPostLtAdjustRequestSupported() &&
result)
if ((lConfig.lanes != 0) && hal->isPostLtAdjustRequestSupported() && result)
{
result = postLTAdjustment(activeLinkConfig, force);
}
if((lConfig.lanes != 0) && result && lConfig.bEnableFEC)
bEnableFecOnSor = lConfig.bEnableFEC;
if (main->isEDP())
{
DeviceImpl * nativeDev = findDeviceInList(Address());
if (nativeDev && nativeDev->bIsPreviouslyFakedMuxDevice)
bEnableFecOnSor = activeLinkConfig.bEnableFEC;
}
if((lConfig.lanes != 0) && result && bEnableFecOnSor)
{
//
// Extended latency from link-train end to FEC enable pattern
@@ -4762,7 +4861,14 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
DP_ASSERT(result);
}
if (lConfig != activeLinkConfig)
//
// Do not compare bEnableFEC here. In DDS case FEC might be requested but
// not performed in RM.
//
if ((lConfig.lanes != activeLinkConfig.lanes) ||
(lConfig.peakRate != activeLinkConfig.peakRate) ||
(lConfig.enhancedFraming != activeLinkConfig.enhancedFraming) ||
(lConfig.multistream != activeLinkConfig.multistream))
{
// fallback happens, returns fail to make sure clients notice it.
result = false;
@@ -5763,7 +5869,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
discoveryManager = new DiscoveryManager(messageManager, this, timer, hal);
// Check and clear if any pending message here
if (hal->clearPendingMsg())
if (hal->clearPendingMsg() || bForceClearPendingMsg)
{
DP_LOG(("DP> Stale MSG found: set branch to D3 and back to D0..."));
if (hal->isAtLeastVersion(1, 4))
@@ -5930,11 +6036,13 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
bPConConnected = true;
}
LinkConfiguration maxLinkConfig = getMaxLinkConfig();
if (bPConConnected ||
(main->isEDP() && this->bSkipAssessLinkForEDP) ||
(main->isInternalPanelDynamicMuxCapable()))
{
this->highestAssessedLC = getMaxLinkConfig();
this->highestAssessedLC = maxLinkConfig;
this->linkGuessed = bPConConnected;
this->bSkipAssessLinkForPCon = bPConConnected;
}
@@ -5949,6 +6057,22 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
hal->setPowerState(PowerStateD0);
}
this->assessLink();
if (this->bReassessMaxLink)
{
//
// If the highest assessed LC is not equal to
// max possible link config, re-assess link
//
NvU8 retries = 0U;
while((retries < WAR_MAX_REASSESS_ATTEMPT) && (highestAssessedLC != maxLinkConfig))
{
DP_LOG(("DP> Assessed link is not equal to highest possible config. Reassess link."));
this->assessLink();
retries++;
}
}
}
if (hal->getLegacyPortCount() != 0)
@@ -6806,6 +6930,7 @@ bool ConnectorImpl::updatePsrLinkState(bool bTrainLink)
{
// Bug 3438892 If the panel is turned off the reciever on its side,
// force panel link on by writting 600 = 1
this->hal->setDirtyLinkStatus(true);
if (this->isLinkLost())
{
hal->setPowerState(PowerStateD0);
@@ -6969,5 +7094,6 @@ void ConnectorImpl::configInit()
bNoFallbackInPostLQA = 0;
LT2FecLatencyMs = 0;
bDscCapBasedOnParent = false;
bForceClearPendingMsg = false;
}

107
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -929,7 +929,7 @@ void DeviceImpl::applyOUIOverrides()
// color formats that are listed in 0x69h even in pass through mode.
//
this->bDscPassThroughColorFormatWar = true;
if ((buffer[8] == 0x31) || (buffer[8] == 0x20))
{
this->bSdpExtCapable = False;
@@ -957,7 +957,7 @@ void DeviceImpl::applyOUIOverrides()
bool DeviceImpl::getAsyncSDPSupported()
{
NvU8 byte = 0;
unsigned size = 0;
unsigned size = 1;
unsigned sizeCompleted;
unsigned nakReason = NakUndefined;
//
@@ -2102,7 +2102,7 @@ bool DeviceImpl::setDscEnable(bool enable)
return false;
}
if ((this->devDoingDscDecompression == this) && !this->isLogical() && this->parent != NULL)
if ((this->devDoingDscDecompression == this) && !this->isLogical() && !(this->peerDevice == Dongle) && this->parent != NULL)
{
//
// If the device has a parent, that means the sink is on a MST link and
@@ -2414,52 +2414,77 @@ AuxBus::status DeviceImpl::dscCrcControl(NvBool bEnable, gpuDscCrc *gpuData, sin
bool DeviceImpl::getPCONCaps(PCONCaps *pPCONCaps)
{
AuxBus::status status = AuxBus::success;
NvU32 addr = NV_DPCD_DETAILED_CAP_INFO_ONE(0);
NvU8 data = 0;
unsigned size = 1;
NvU32 addr = NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT(0);
NvU8 data[4] = {0};
unsigned sizeCompleted = 0;
unsigned nakReason = 0;
NvU8 pConType = 0;
if (isMultistream())
return false;
status = getDpcdData(addr, &data, size, &sizeCompleted, &nakReason);
if (status != AuxBus::success)
status = this->getDpcdData(addr, &data[0], sizeof(data), &sizeCompleted, &nakReason);
if (status == AuxBus::success)
{
return false;
pConType = DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _DWNSTRM_PORT_TX_TYPE, data[0]);
if (pConType == NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_HDMI)
{
this->connectorType = connectorHDMI;
pPCONCaps->maxTmdsClkRate = data[1] * 2500000;
pPCONCaps->bSourceControlModeSupported =
FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _SRC_CONTROL_MODE_SUPPORT, _YES, data[2]);
pPCONCaps->bConcurrentLTSupported =
FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _CONCURRENT_LT_SUPPORT, _YES, data[2]);
switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_FRL_LINK_BW_SUPPORT, data[2]))
{
case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_9G:
pPCONCaps->maxHdmiLinkBandwidthGbps = 9;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_18G:
pPCONCaps->maxHdmiLinkBandwidthGbps = 18;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_24G:
pPCONCaps->maxHdmiLinkBandwidthGbps = 24;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_32G:
pPCONCaps->maxHdmiLinkBandwidthGbps = 32;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_40G:
pPCONCaps->maxHdmiLinkBandwidthGbps = 40;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_48G:
pPCONCaps->maxHdmiLinkBandwidthGbps = 48;
break;
default:
pPCONCaps->maxHdmiLinkBandwidthGbps = 0;
break;
}
switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_BITS_PER_COMPONENT_DEF, data[2]))
{
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_10BPC:
pPCONCaps->maxBpc = 10;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_12BPC:
pPCONCaps->maxBpc = 12;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_16BPC:
pPCONCaps->maxBpc = 16;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_8BPC:
default:
pPCONCaps->maxBpc = 8;
break;
}
DP_LOG((" DP2HDMI PCON caps - Max TMDS Clk: %u LinkBWGbps: %u MaxBpc: %u",
pPCONCaps->maxTmdsClkRate, pPCONCaps->maxHdmiLinkBandwidthGbps, pPCONCaps->maxBpc));
}
}
pPCONCaps->maxTmdsClkRate = data;
addr = NV_DPCD_DETAILED_CAP_INFO_TWO(0);
status = getDpcdData(addr, &data, size, &sizeCompleted, &nakReason);
if (status != AuxBus::success)
else
{
DP_LOG((" DP-DEV> Error - DPCD Read for detailed port capabilities (0x80) failed."));
return false;
}
pPCONCaps->bSourceControlModeSupported =
FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _SRC_CONTROL_MODE_SUPPORT, _YES, data);
pPCONCaps->bConcurrentLTSupported =
FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _CONCURRENT_LT_SUPPORT, _YES, data);
pPCONCaps->maxHdmiLinkBandwidthGbps =
DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_FRL_LINK_BW_SUPPORT, data);
switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_BITS_PER_COMPONENT_DEF, data))
{
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_10BPC:
pPCONCaps->maxBpc = 10;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_12BPC:
pPCONCaps->maxBpc = 12;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_16BPC:
pPCONCaps->maxBpc = 16;
break;
case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_8BPC:
default:
pPCONCaps->maxBpc = 8;
break;
}
return true;
}

22
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,7 +40,6 @@
#include <ctrl/ctrl0073/ctrl0073specific.h>
#include <ctrl/ctrl0073/ctrl0073system.h>
#include <ctrl/ctrl5070/ctrl5070or.h>
using namespace DisplayPort;
//
@@ -94,7 +93,9 @@ const struct
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL}
{NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL, &dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
@@ -892,6 +893,7 @@ void EvoMainLink::applyRegkeyOverrides()
_skipPowerdownEDPPanelWhenHeadDetach = dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped;
_applyLinkBwOverrideWarRegVal = dpRegkeyDatabase.bLinkBwOverrideWarApplied;
_enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled;
_enableFecCheckForDDS = dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel;
}
NvU32 EvoMainLink::getRegkeyValue(const char *key)
@@ -1043,7 +1045,6 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
case EDP_3_24GHZ:
case EDP_4_32GHZ:
case HBR2:
case EDP_6_75GHZ:
case HBR3:
linkBw = linkrate / DP_LINK_BW_FREQ_MULTI_MBPS;
dpCtrlData = FLD_SET_DRF_NUM(0073_CTRL, _DP_DATA, _SET_LINK_BW,
@@ -1160,7 +1161,7 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
//
if (!requestRmLC.lowerConfig())
{
// If no valid link config could be found, break here.
// If no valid link config could be found, break here.
break;
}
fallback = true;
@@ -1235,6 +1236,16 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
retLink->setLaneRate(requestRmLC.peakRate, result ? requestRmLC.lanes : 0);
retLink->setLTCounter(ltCounter);
// For release branch only, check FEC return values and update to "retLink"
if (_enableFecCheckForDDS)
{
if (requestRmLC.bEnableFEC && (FLD_TEST_DRF(0073_CTRL_DP, _ERR, _ENABLE_FEC, _ERR, err)))
{
retLink->bEnableFEC = false;
DP_ASSERT(0);
}
}
NV_DPTRACE_INFO(LINK_TRAINING_DONE, status, requestRmLC.peakRate, requestRmLC.lanes);
return result;
@@ -1797,7 +1808,6 @@ bool EvoMainLink::configureLinkRateTable
case linkBW_3_24Gbps:
case linkBW_4_32Gbps:
case linkBW_5_40Gbps:
case linkBW_6_75Gbps:
case linkBW_8_10Gbps:
pLinkRates->import(params.linkBwTbl[i]);
break;

11
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -84,6 +84,17 @@ void ConnectorImpl::applyOuiWARs()
//
LT2FecLatencyMs = 57;
//
// This is to reset the MSTM control bit on the branch device. On this
// device, if continuous LAM message are sent very close then IRQ vector
// will fail to see stale/pending message and will not reset the MSTM_CTRL
// register. Currently making this specific to linux so as to have minimum
// effect on windows. Later proper fix for this will be generic.
//
#if defined(NV_UNIX)
bForceClearPendingMsg = true;
#endif
if (bDscMstCapBug3143315)
{
//