535.43.02

src/common/displayport/inc/dp_connectorimpl.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -125,6 +125,7 @@ namespace DisplayPort
         bool    bPConConnected;                 // HDMI2.1-Protocol Converter (Support SRC control mode) connected.
         bool    bSkipAssessLinkForPCon;         // Skip assessLink() for PCON. DD will call assessFRLLink later.
         bool    bHdcpAuthOnlyOnDemand;          // True if only initiate Hdcp authentication on demand and MST won't auto-trigger authenticate at device attach.
+        bool    bReassessMaxLink;               // Retry assessLink() if the first assessed link config is lower than the panel max config.
 
         bool    constructorFailed;
 
@@ -333,6 +334,14 @@ namespace DisplayPort
         //
         bool        bPowerDownPhyBeforeD3;
 
+        //
+        // Reset the MSTM_CTRL registers on Synaptics branch device irrespective of
+        // IRQ VECTOR register having stale message. Synaptics device needs to reset
+        // the topology before issue of new LAM message if previous LAM was not finished
+        // bug 3928070
+        //
+        bool bForceClearPendingMsg;
+
         void sharedInit();
         ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);
 

src/common/displayport/inc/dp_deviceimpl.h

@@ -39,6 +39,7 @@
 namespace DisplayPort
 {
     #define PREDEFINED_DSC_MST_BPPX16 160;
+    #define MAX_DSC_COMPRESSION_BPPX16 128;
     #define HDCP_BCAPS_DDC_OFFSET 0x40
     #define HDCP_BCAPS_DDC_EN_BIT 0x80
     #define HDCP_BCAPS_DP_EN_BIT  0x01

src/common/displayport/inc/dp_evoadapter.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -160,6 +160,7 @@ namespace DisplayPort
         bool _applyLinkBwOverrideWarRegVal;
         bool _isDynamicMuxCapable;
         bool _enableMSAOverrideOverMST;
+        bool _enableFecCheckForDDS;
 
         bool _isLTPhyRepeaterSupported;
         //

src/common/displayport/inc/dp_linkconfig.h

@@ -36,6 +36,7 @@
 #include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE
 #include "displayport.h"
 
+
 namespace DisplayPort
 {
     typedef NvU64 LinkRate;
@@ -45,7 +46,7 @@ namespace DisplayPort
     public:
         // Store link rate in multipler of 270MBPS to save space
         NvU8 element[NV_DPCD_SUPPORTED_LINK_RATES__SIZE];
-        NvU8 entries;
+        NvU8  entries;
 
         LinkRates()
         {
@@ -143,18 +144,17 @@ namespace DisplayPort
         totalUsableTimeslots = totalTimeslots - 1
     };
 
-    // in MBps
+    // in 10bps
     enum
     {
-        RBR         = 162000000,
-        EDP_2_16GHZ = 216000000,
-        EDP_2_43GHZ = 243000000,
-        HBR         = 270000000,
-        EDP_3_24GHZ = 324000000,
-        EDP_4_32GHZ = 432000000,
-        HBR2        = 540000000,
-        EDP_6_75GHZ = 675000000,
-        HBR3        = 810000000
+        RBR             =  162000000,
+        EDP_2_16GHZ     =  216000000,
+        EDP_2_43GHZ     =  243000000,
+        HBR             =  270000000,
+        EDP_3_24GHZ     =  324000000,
+        EDP_4_32GHZ     =  432000000,
+        HBR2            =  540000000,
+        HBR3            =  810000000
     };
 
     struct HDCPState

src/common/displayport/inc/dp_regkeydatabase.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,15 +59,25 @@
 
 #define NV_DP_REGKEY_FORCE_EDP_ILR                    "DP_BYPASS_EDP_ILR_REV_CHECK"
 
+// Regkey to make sure enable FEC only when RM notified sink successfully
+#define NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL             "DP_DDS_CHECK_FEC_TO_ENABLE"
+
 // Message to power down video stream before power down link (set D3)
 #define NV_DP_REGKEY_POWER_DOWN_PHY                   "DP_POWER_DOWN_PHY"
 
+//
+// Regkey to re-assess max link if the first assessed link config 
+// is lower than the panel max
+//
+#define NV_DP_REGKEY_REASSESS_MAX_LINK                "DP_REASSESS_MAX_LINK"
+
 //
 // DSC capability of downstream device should be decided based on device's own
 // and its parent's DSC capability.
 //
 #define NV_DP_DSC_MST_CAP_BUG_3143315                  "DP_DSC_MST_CAP_BUG_3143315"
 
+
 //
 // Data Base used to store all the regkey values.
 // The actual data base is declared statically in dp_evoadapter.cpp.
@@ -100,6 +110,8 @@ struct DP_REGKEY_DATABASE
     bool  bBypassEDPRevCheck;
     bool  bDscMstCapBug3143315;
     bool  bPowerDownPhyBeforeD3;
+    bool  bCheckFECForDynamicMuxDSCPanel;
+    bool  bReassessMaxLink;
 };
 
 #endif //INCLUDED_DP_REGKEYDATABASE_H