535.43.02

src/common/displayport/inc/dp_regkeydatabase.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,15 +59,25 @@
 
 #define NV_DP_REGKEY_FORCE_EDP_ILR                    "DP_BYPASS_EDP_ILR_REV_CHECK"
 
+// Regkey to make sure enable FEC only when RM notified sink successfully
+#define NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL             "DP_DDS_CHECK_FEC_TO_ENABLE"
+
 // Message to power down video stream before power down link (set D3)
 #define NV_DP_REGKEY_POWER_DOWN_PHY                   "DP_POWER_DOWN_PHY"
 
+//
+// Regkey to re-assess max link if the first assessed link config 
+// is lower than the panel max
+//
+#define NV_DP_REGKEY_REASSESS_MAX_LINK                "DP_REASSESS_MAX_LINK"
+
 //
 // DSC capability of downstream device should be decided based on device's own
 // and its parent's DSC capability.
 //
 #define NV_DP_DSC_MST_CAP_BUG_3143315                  "DP_DSC_MST_CAP_BUG_3143315"
 
+
 //
 // Data Base used to store all the regkey values.
 // The actual data base is declared statically in dp_evoadapter.cpp.
@@ -100,6 +110,8 @@ struct DP_REGKEY_DATABASE
     bool  bBypassEDPRevCheck;
     bool  bDscMstCapBug3143315;
     bool  bPowerDownPhyBeforeD3;
+    bool  bCheckFECForDynamicMuxDSCPanel;
+    bool  bReassessMaxLink;
 };
 
 #endif //INCLUDED_DP_REGKEYDATABASE_H