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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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4
src/common/inc/swref/published/hopper/gh100/dev_fb.h
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@@ -21,7 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fb_h
#ifndef __gh100_dev_fb_h_
#define __gh100_dev_fb_h_
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00100A34 /* RW-4R */
@@ -29,4 +29,4 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#endif // __gh100_dev_fb_h__
#endif // __gh100_dev_fb_h_

32
src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fsp_addendum_h__
#define __gh100_dev_fsp_addendum_h__
#define NV_GFW_FSP_UCODE_VERSION NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(1)
#define NV_GFW_FSP_UCODE_VERSION_FULL 11:0
#define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8
#define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0
#endif // __gh100_dev_fsp_addendum_h__

6
src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -64,5 +64,9 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gh100_dev_fsp_pri_h__

52
src/common/inc/swref/published/hopper/gh100/dev_fuse.h Normal file
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@@ -0,0 +1,52 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fuse_h__
#define __gh100_dev_fuse_h__
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_0 0x00824E04 /* RW-4R */
#define NV_FUSE_SPARE_BIT_0_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_0_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_0_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_1 0x00824E08 /* RW-4R */
#define NV_FUSE_SPARE_BIT_1_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_1_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_1_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_2 0x00824E0C /* RW-4R */
#define NV_FUSE_SPARE_BIT_2_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_2_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_2_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_2_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_3 0x00824E10 /* RW-4R */
#define NV_FUSE_SPARE_BIT_3_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_3_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_3_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_3_DATA_ENABLE 0x00000001 /* RW--V */
#endif // __gh100_dev_fuse_h__

13
src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,14 @@
#ifndef __gh100_dev_gc6_island_h__
#define __gh100_dev_gc6_island_h__
#define NV_PGC6_SCI_SEC_TIMER_TIME_0 0x00118f54 /* RW-4R */
#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC 31:5 /* RWEUF */
#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1 0x00118f58 /* RW-4R */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC 28:0 /* RWEUF */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0 0x00118df4 /* RW-4R */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE 0:0 /* RWEVF */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_DONE 0x00000000 /* R-E-V */
@@ -33,5 +41,8 @@
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1 0x00118df8 /* RW-4R */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC 28:0 /* RWEUF */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20 0x001182cc /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA 31:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA_INIT 0x00000000 /* RWI-V */
#endif // __gh100_dev_gc6_island_h__

8
src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h
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@@ -26,4 +26,12 @@
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#endif // __gh100_dev_gc6_island_addendum_h__

16
src/common/inc/swref/published/hopper/gh100/dev_vm.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -46,5 +46,19 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#endif // __gh100_dev_vm_h__

4
src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h
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@@ -50,4 +50,8 @@
//
#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT 0x00000081
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gh100_dev_vm_addendum_h__

9
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h
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@@ -27,11 +27,20 @@
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE 1:1 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_DEFAULT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_ENABLE 0x00000001 /* RW--V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER 2:2 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_DISABLE 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_ENABLE 0x00000001 /* RW--V */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE 0x00000008 /* R--4R */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE 15:8 /* R-IVF */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE 23:16 /* R-IVF */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE 31:24 /* R-IVF */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE_3D 0x00000003 /* R-I-V */
#define NV_EP_PCFG_GPU_BARREG0 0x00000010 /* RW-4R */
#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS 31:18 /* RWIVF */
#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_SUBSYSTEM_ID 0x0000002C /* R--4R */
#define NV_EP_PCFG_GPU_MSI_64_HEADER 0x00000048 /* RW-4R */
#define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE 16:16 /* RWIVF */