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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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3
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -315,7 +315,8 @@ NvHdmi_QueryFRLConfig(NvHdmiPkt_Handle libHandle,
}
// if there is no FRL capability reported fail this call
if (pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE)
if ((pSrcCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE) ||
(pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE))
{
return NVHDMIPKT_FAIL;
}

3
src/common/modeset/hdmipacket/nvhdmipkt_9171.c
View File

@@ -573,12 +573,13 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis,
packetLen == 0 || pPacketIn == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE)
{
result = NVHDMIPKT_INVALID_ARG;
NvHdmiPkt_Print(pThis, "Invalid arg");
goto hdmiPacketWrite9171_exit;
}
if ((result = validateInputPacketLength(pktType9171, packetLen, pPacketIn)) != NVHDMIPKT_SUCCESS)
{
NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect");
NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d", packetLen);
NvHdmiPkt_Assert(0);
goto hdmiPacketWrite9171_exit;
}

1
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -460,6 +460,7 @@ static NvBool evaluateIsDSCPossible(NVHDMIPKT_CLASS *pThis,
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
bIsDSCPossible = pGetHdmiFrlCapacityComputationParams->dsc.bIsDSCPossible;
*pFRLParams = pGetHdmiFrlCapacityComputationParams->input;
}
pThis->callback.free(pThis->cbHandle, pGetHdmiFrlCapacityComputationParams);

27
src/common/modeset/timing/displayid20.h
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -275,7 +275,7 @@ typedef struct _tagDISPLAYID_2_0_TIMING_7_BLOCK
#define DISPLAYID_2_0_TIMING_DSC_PASSTHRU_TIMING 1
// the following fields apply to Timing Descriptors 7 (Not all of them are
// the following fields apply to Timing 7 Descriptors (Not all of them are
// used per descriptor, but the format is the same
#define DISPLAYID_2_0_TIMING_ASPECT_RATIO_1_1 0
#define DISPLAYID_2_0_TIMING_ASPECT_RATIO_5_4 1
@@ -308,29 +308,15 @@ typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK_HEADER
NvU8 data_bytes; // Values range from 1(0x01) to 248(0xF8)
} DISPLAYID_2_0_TIMING_8_BLOCK_HEADER;
typedef struct _tagDISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE
{
NvU8 timing_code;
} DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE;
typedef struct _tagDISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE
{
NvU8 timing_code[2];
} DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE;
#define DISPLAYID_2_0_TIMING_8_MAX_CODES 248
typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK
{
DISPLAYID_2_0_TIMING_8_BLOCK_HEADER header;
union
{
DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE timing_code_1[DISPLAYID_2_0_TIMING_8_MAX_CODES];
DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE timing_code_2[DISPLAYID_2_0_TIMING_8_MAX_CODES / 2];
};
NvU8 timingCode[DISPLAYID_2_0_TIMING_8_MAX_CODES];
} DISPLAYID_2_0_TIMING_8_BLOCK;
// the following fields apply to Timing 8 Descriptors
#define DISPLAYID_2_0_TIMING_CODE_DMT 0
#define DISPLAYID_2_0_TIMING_CODE_CTA_VIC 1
#define DISPLAYID_2_0_TIMING_CODE_HDMI_VIC 2
@@ -353,6 +339,7 @@ typedef struct _TAG_DISPLAYID_2_0_TIMING_9_DESCRIPTOR
NvU8 refresh_rate; // 1 Hz to 256 Hz
} DISPLAYID_2_0_TIMING_9_DESCRIPTOR;
// the following fields apply to Timing 9/10 Descriptors
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD 0
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1 1
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2 2
@@ -384,8 +371,8 @@ typedef struct _DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR
{
struct {
NvU8 timing_formula :3;
NvU8 early_vsync :1;
NvU8 rr1000div1001_or_hblank :1;
NvU8 early_vsync :1;
NvU8 rr1000div1001_or_hblank :1;
NvU8 stereo_support :2;
NvU8 ycc420_support :1;
} options;

231
src/common/modeset/timing/nvt_displayid20.c
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -61,7 +61,6 @@ static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER
// Helper function
static NVT_STATUS getPrimaryUseCase(NvU8 product_type, NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE *primary_use_case);
static NVT_STATUS parseDisplayId20Timing7Descriptor(const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 revision, NvU8 count);
static NVT_STATUS parseDisplayId20Timing9Descriptor(const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 count);
static NvU32 greatestCommonDenominator(NvU32 x, NvU32 y);
static NvU8 getExistedTimingSeqNumber(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, enum NVT_TIMING_TYPE);
@@ -625,6 +624,7 @@ parseDisplayId20Timing7(
return NVT_STATUS_ERR;
}
revision = pTiming7Block->header.revision;
descriptorCount = pDataBlock->data_bytes / (sizeof(DISPLAYID_2_0_TIMING_7_DESCRIPTOR) + pTiming7Block->header.payload_bytes_len);
if (descriptorCount < 1 || descriptorCount > DISPLAYID_2_0_TIMING_7_MAX_DESCRIPTORS)
@@ -641,8 +641,36 @@ parseDisplayId20Timing7(
for (i = 0; i < descriptorCount; i++)
{
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
if (parseDisplayId20Timing7Descriptor(&pTiming7Block->descriptors[i], &newTiming, revision, startSeqNumber+i) == NVT_STATUS_SUCCESS)
if (parseDisplayId20Timing7Descriptor(&pTiming7Block->descriptors[i], &newTiming, startSeqNumber+i) == NVT_STATUS_SUCCESS)
{
newTiming.etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION && pTiming7Block->header.dsc_passthrough == 1) ?
NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU :
0;
if (revision >= DISPLAYID_2_0_TYPE7_YCC420_SUPPORT_REVISION)
{
newTiming.etc.flag |= pTiming7Block->descriptors[i].options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0;
if (pTiming7Block->descriptors[i].options.is_preferred_or_ycc420) // YCC 420 support
{
UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, 1, 1, 0, 1);
}
}
else
{
newTiming.etc.flag |= pTiming7Block->descriptors[i].options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0;
}
NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type7:#%2d:%dx%dx%3d.%03dHz/%s",
(int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status),
(int)newTiming.HVisible,
(int)((newTiming.interlaced ? 2 : 1)*newTiming.VVisible),
(int)newTiming.etc.rrx1k/1000,
(int)newTiming.etc.rrx1k%1000,
(newTiming.interlaced ? "I":"P"));
newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0';
newTiming.etc.rep = 0x1;
if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming))
{
break;
@@ -667,80 +695,50 @@ parseDisplayId20Timing8(
NVT_STATUS status = NVT_STATUS_SUCCESS;
const DISPLAYID_2_0_TIMING_8_BLOCK *pTiming8Block = NULL;
NVT_TIMING newTiming;
NvU8 codeType = DISPLAYID_2_0_TIMING_CODE_RSERVED;
NvU8 codeCount = 0;
NvU8 startSeqNumber = 0;
NvU8 i;
pTiming8Block = (const DISPLAYID_2_0_TIMING_8_BLOCK *)pDataBlock;
codeCount = pDataBlock->data_bytes;
// 1-byte descriptor timing code
if (pTiming8Block->header.timing_code_size == DISPLAYID_2_0_TIMING_CODE_SIZE_1_BYTE)
if (codeCount == 0)
{
if (pDataBlock->data_bytes % sizeof(DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE) != 0)
{
return NVT_STATUS_ERR;
}
nvt_assert(0 && "No available byte code!");
return NVT_STATUS_SUCCESS;
}
codeCount = pDataBlock->data_bytes / sizeof(DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE);
if (codeCount < 1 || codeCount > DISPLAYID_2_0_TIMING_8_MAX_CODES)
if (codeCount > DISPLAYID_2_0_TIMING_8_MAX_CODES)
{
nvt_assert(0 && "one byte code is out of range!");
return NVT_STATUS_SUCCESS;
}
if (pDisplayIdInfo != NULL)
{
startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8);
}
for (i = 0; i < codeCount; i++)
{
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
if (parseDisplayId20Timing8Descriptor(&pTiming8Block->timingCode, &newTiming,
pTiming8Block->header.timing_code_type,
pTiming8Block->header.timing_code_size, i, startSeqNumber+i) == NVT_STATUS_SUCCESS)
{
return NVT_STATUS_ERR;
}
codeType = pTiming8Block->header.timing_code_type;
if (pDisplayIdInfo != NULL)
{
startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8);
}
for (i = 0; i < codeCount; i++)
{
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
if (codeType == DISPLAYID_2_0_TIMING_CODE_DMT)
{
if (NvTiming_EnumDMT((NvU32)(pTiming8Block->timing_code_1[i].timing_code),
&newTiming) != NVT_STATUS_SUCCESS)
{
if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR;
break;
}
}
else if (codeType == DISPLAYID_2_0_TIMING_CODE_CTA_VIC)
{
if (NvTiming_EnumCEA861bTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code),
&newTiming) != NVT_STATUS_SUCCESS)
{
if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR;
break;
}
}
else if (codeType == DISPLAYID_2_0_TIMING_CODE_HDMI_VIC)
{
if (NvTiming_EnumHdmiVsdbExtendedTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code),
&newTiming) != NVT_STATUS_SUCCESS)
{
if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR;
break;
}
}
else
{
// RESERVED
break;
}
newTiming.etc.flag |= ((pTiming8Block->header.revision >= 1) && pTiming8Block->header.is_support_yuv420) ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0;
newTiming.etc.status = NVT_STATUS_DISPLAYID_8N(++startSeqNumber);
newTiming.etc.flag |= ((pTiming8Block->header.revision == 1) && pTiming8Block->header.is_support_yuv420) ?
NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 :
0;
NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type8:#%3d:%dx%dx%3d.%03dHz/%s",
(int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status),
(int)newTiming.HVisible, (int)newTiming.VVisible,
(int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000,
(newTiming.interlaced ? "I":"P"));
(int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status),
(int)newTiming.HVisible, (int)newTiming.VVisible,
(int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000,
(newTiming.interlaced ? "I":"P"));
newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0';
newTiming.etc.rep = 0x1;
if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming))
{
@@ -748,11 +746,6 @@ parseDisplayId20Timing8(
}
}
}
else
{
nvt_assert(0);
// TODO : 2-byte descriptor timing code did not define yet in DID20.
}
return status;
}
@@ -859,11 +852,11 @@ parseDisplayId20Timing10(
for (i = 0; i < descriptorCount; i++)
{
startSeqNumber += i;
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i*eachOfDescriptorsSize],
&newTiming,
pTiming10Block->header.payload_bytes_len))
pTiming10Block->header.payload_bytes_len,
startSeqNumber+i))
{
p6bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *)&pTiming10Block->descriptors[i*eachOfDescriptorsSize];
@@ -894,8 +887,8 @@ parseDisplayId20Timing10(
(newTiming.interlaced ? "I":"P"));
}
newTiming.etc.status = NVT_STATUS_DISPLAYID_10N(++startSeqNumber);
newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0';
newTiming.etc.rep = 0x1;
if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming))
{
@@ -1417,9 +1410,9 @@ parseDisplayId20CtaData(
parseCea861Hdr10PlusDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
// CEA861-F at 7.5.12 section about VFPDB block.
if (p861Info->total_vfpdb > 0)
if (p861Info->total_svr > 0)
{
parse861bShortPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
parseCta861NativeOrPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
}
return status;
@@ -1532,16 +1525,19 @@ assignNextAvailableDisplayId20Timing(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20Timing7Descriptor(
const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor,
const void *pVoidDescriptor,
NVT_TIMING *pTiming,
NvU8 revision,
NvU8 count)
{
NVT_STATUS status = NVT_STATUS_SUCCESS;
NvU32 gdc = 0;
const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor = NULL;
pDescriptor = (const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *)pVoidDescriptor;
// pclk is in 10Khz
// pixel_clock is in kHz
pTiming->pclk = ((pDescriptor->pixel_clock[2] << 16 |
@@ -1636,36 +1632,63 @@ parseDisplayId20Timing7Descriptor(
pTiming->etc.rrx1k = NvTiming_CalcRRx1k(pTiming->pclk,
pTiming->interlaced,
pTiming->HTotal,
pTiming->VTotal);
pTiming->VTotal);
pTiming->etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION ) ? NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU : 0;
pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count);
if (revision >= DISPLAYID_2_0_TYPE7_YCC420_SUPPORT_REVISION)
return status;
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS
parseDisplayId20Timing8Descriptor(
const void *pVoidDescriptor,
NVT_TIMING *pTiming,
NvU8 codeType,
NvU8 codeSize,
NvU8 idx,
NvU8 count)
{
NVT_STATUS status = NVT_STATUS_SUCCESS;
const NvU8 *pTimingCode = (const NvU8 *)pVoidDescriptor;
const NvU16 *pTiming2ByteCode = (const NvU16 *)pVoidDescriptor;
if (codeSize == DISPLAYID_2_0_TIMING_CODE_SIZE_1_BYTE)
{
pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0;
if (pDescriptor->options.is_preferred_or_ycc420) // YCC 420 support
switch (codeType)
{
UPDATE_BPC_FOR_COLORFORMAT(pTiming->etc.yuv420, 0, 1, 1, 1, 0, 1);
case DISPLAYID_2_0_TIMING_CODE_DMT: //single-byte DMT ID Codes
status = NvTiming_EnumDMT((NvU32)(pTimingCode[idx]), pTiming);
break;
case DISPLAYID_2_0_TIMING_CODE_CTA_VIC:
status = NvTiming_EnumCEA861bTiming((NvU32)(pTimingCode[idx]), pTiming);
break;
case DISPLAYID_2_0_TIMING_CODE_HDMI_VIC:
status = NvTiming_EnumHdmiVsdbExtendedTiming((NvU32)(pTimingCode[idx]), pTiming);
break;
default:
{
nvt_assert(0 && "RESERVED timing code type");
status = NVT_STATUS_ERR;
}
break;
}
}
else
else if (codeSize == DISPLAYID_2_0_TIMING_CODE_SIZE_2_BYTE)
{
pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0;
// Standard two-byte codes
if (codeType == DISPLAYID_2_0_TIMING_CODE_DMT)
{
status = NvTiming_EnumStdTwoBytesCode((NvU16)pTiming2ByteCode[idx], pTiming);
}
}
pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count);
NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type7:#%2d:%dx%dx%3d.%03dHz/%s",
(int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status),
(int)pTiming->HVisible,
(int)((pTiming->interlaced ? 2 : 1)*pTiming->VVisible),
(int)pTiming->etc.rrx1k/1000,
(int)pTiming->etc.rrx1k%1000,
(pTiming->interlaced ? "I":"P"));
pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0';
pTiming->etc.rep = 0x1;
if (status == NVT_STATUS_SUCCESS)
{
pTiming->etc.status = NVT_STATUS_DISPLAYID_8N(++count);
return status;
}
return status;
}
@@ -1733,6 +1756,7 @@ parseDisplayId20Timing9Descriptor(
}
}
pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0';
pTiming->etc.rep = 0x1;
return status;
}
@@ -1742,7 +1766,8 @@ NVT_STATUS
parseDisplayId20Timing10Descriptor(
const void *pDescriptor,
NVT_TIMING *pTiming,
NvU8 payloadBytes)
NvU8 payloadBytes,
NvU8 count)
{
NVT_STATUS status = NVT_STATUS_SUCCESS;
const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR* p6bytesDescriptor = NULL;
@@ -1810,7 +1835,11 @@ parseDisplayId20Timing10Descriptor(
break;
}
if (status == NVT_STATUS_SUCCESS) return status;
if (status == NVT_STATUS_SUCCESS)
{
pTiming->etc.status = NVT_STATUS_DISPLAYID_10N(++count);
return status;
}
return status;
}

79
src/common/modeset/timing/nvt_dmt.c
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,7 +34,7 @@
PUSH_SEGMENTS
// DMT table
// DMT table 2-1
// Macro to declare a TIMING initializer for given parameters without border
#define DMT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rr,pclk,id) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT,id),"VESA DMT"}}
@@ -192,6 +192,43 @@ NVT_STATUS NvTiming_EnumDMT(NvU32 dmtId, NVT_TIMING *pT)
return NVT_STATUS_ERR;
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_EnumStdTwoBytesCode(NvU16 std2ByteCode, NVT_TIMING *pT)
{
NvU32 aspect, width, height, rr;
if ((pT == NULL) || (std2ByteCode == 0))
{
return NVT_STATUS_ERR;
}
// The value in the EDID = (Horizontal active pixels/8) - 31
width = (std2ByteCode & 0x0FF) + 31;
width <<= 3;
rr = ((std2ByteCode >> 8) & 0x3F) + 60; // bits 5->0
// get the height
aspect = ((std2ByteCode >> 8) & 0xC0); // aspect ratio at bit 7:6
if (aspect == 0x00) height = width * 5 / 8; // 16:10
else if (aspect == 0x40) height = width * 3 / 4; // 4:3
else if (aspect == 0x80) height = width * 4 / 5; // 5:4
else height = width * 9 / 16; // 16:9
// try to get the timing from DMT or DMT_RB
if (NvTiming_CalcDMT(width, height, rr, 0, pT) == NVT_STATUS_SUCCESS)
{
return NVT_STATUS_SUCCESS;
}
// try to get the timing from DMT_RB2
else if (NvTiming_CalcDMT_RB2(width, height, rr, 0, pT) == NVT_STATUS_SUCCESS)
{
return NVT_STATUS_SUCCESS;
}
return NVT_STATUS_ERR;
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_CalcDMT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT)
{
@@ -269,4 +306,42 @@ NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag,
return NVT_STATUS_ERR;
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_CalcDMT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT)
{
NVT_TIMING *p = (NVT_TIMING *)DMT;
if (pT == NULL)
return NVT_STATUS_ERR;
if (width == 0 || height == 0 || rr == 0)
return NVT_STATUS_ERR;
// no interlaced DMT timing
if ((flag & NVT_PVT_INTERLACED_MASK) != 0)
return NVT_STATUS_ERR;
while (p->HVisible != 0 && p->VVisible != 0)
{
// select only reduced-bandwidth timing.
if (NVT_GET_TIMING_STATUS_TYPE(p->etc.status) == NVT_TYPE_DMT_RB_2)
{
if ((NvU32)p->HVisible == width &&
(NvU32)p->VVisible == height &&
(NvU32)p->etc.rr == rr)
{
NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING));
*pT = *p;
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
NVT_SNPRINTF((char *)pT->etc.name, 40, "DMT-RB2:%dx%dx%dHz",width, height, rr);
pT->etc.name[39] = '\0';
pT->etc.rgb444.bpc.bpc8 = 1;
return NVT_STATUS_SUCCESS;
}
}
p ++;
}
return NVT_STATUS_ERR;
}
POP_SEGMENTS

93
src/common/modeset/timing/nvt_edid.c
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -1079,15 +1079,17 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
// add the detailed timings in 18-byte long display descriptor
parse861ExtDetailedTiming(pExt, p861Info->basic_caps, pInfo);
if (p861Info->revision >= NVT_CTA861_REV_H && p861Info->total_did_type10db != 0)
if (p861Info->revision >= NVT_CTA861_REV_H)
{
parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo);
if (p861Info->total_did_type7db != 0) parseCta861DIDType7VideoTimingDataBlock(p861Info, pInfo);
if (p861Info->total_did_type8db != 0) parseCta861DIDType8VideoTimingDataBlock(p861Info, pInfo);
if (p861Info->total_did_type10db != 0) parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo);
}
// CEA861-F at 7.5.12 section about VFPDB block.
if (p861Info->revision >= NVT_CEA861_REV_F && p861Info->total_vfpdb != 0)
if (p861Info->revision >= NVT_CEA861_REV_F && (p861Info->total_svr != 0 || p861Info->valid.NVRDB == 1))
{
parse861bShortPreferredTiming(p861Info, pInfo, FROM_CTA861_EXTENSION);
parseCta861NativeOrPreferredTiming(p861Info, pInfo, FROM_CTA861_EXTENSION);
}
k++;
@@ -1175,6 +1177,27 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
// find out the total established timings - base EDID and then the LDDs
parseEdidEstablishedTiming(pInfo);
// remove the T8VTDB timing if it co-existed in standard or established timings
if (pInfo->ext861.revision >= NVT_CTA861_REV_H && pInfo->ext861.total_did_type8db != 0 && pInfo->total_timings > 1)
{
for (i = 0; i < pInfo->total_timings; i++)
{
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == NVT_TYPE_CTA861_DID_T8)
{
if (isMatchedStandardTiming(pInfo, &pInfo->timing[i]) || isMatchedEstablishedTiming(pInfo, &pInfo->timing[i]))
{
for (j = i; j < pInfo->total_timings - 1; j++)
{
// remove the entry by moving the next entry up.
pInfo->timing[j] = pInfo->timing[j+1];
}
NVMISC_MEMSET(&pInfo->timing[pInfo->total_timings-1], 0, sizeof(NVT_TIMING));
pInfo->total_timings--; i--;
}
}
}
}
getEdidHDM1_4bVsdbTiming(pInfo);
// Assert if no timings were found (due to a bad EDID) or if we mistakenly
@@ -1286,7 +1309,38 @@ void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
}
}
}
}
CODE_SEGMENT(PAGE_DD_CODE)
NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT)
{
NvU32 j;
for (j = 0; j < pInfo->total_timings; j++)
{
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_STD &&
NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT))
{
return NV_TRUE;
}
}
return NV_FALSE;
}
CODE_SEGMENT(PAGE_DD_CODE)
NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT)
{
NvU32 j;
for (j = 0; j < pInfo->total_timings; j++)
{
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_EST &&
NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT))
{
return NV_TRUE;
}
}
return NV_FALSE;
}
CODE_SEGMENT(PAGE_DD_CODE)
@@ -1390,7 +1444,7 @@ CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k)
{
NvU32 i, j;
NvU32 preferred_cea, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt;
NvU32 native_cta, preferred_cta, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt;
NVT_TIMING *pEdidTiming;
NVT_EDID_DD_RANGE_CVT *pCVT = NULL;
NVT_TIMING cvtTiming;
@@ -1406,7 +1460,9 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
// the timing mapping index :
//
// preferred_cea - the "prefer SVD" in CEA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB)
// native_cta - the "native resoluiotn of the sink" in the CTA861.6 A Source shall override any other native video resolution indicators
// if the Source supports NVRDB and the NVRDB was found in the E-EDID
// preferred_cta - the "prefer SVD" in CTA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB)
// preferred_displayid_dtd - the "prefer detailed timing of DispalyID" extension
// preferred_dtd1 - the first deatiled timing and PTM flag is enable
// dtd1 - the first detailed timing
@@ -1416,7 +1472,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
// map3 - the "closest" match to the panel's native timing (i.e. the first DTD timing or the short 861B/C/D timings with "native" flag).
// map4 - the "closest" match with the same refresh rate
// max - the timing with the max visible area
preferred_cea = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings;
native_cta = preferred_cta = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings;
max = cvt = 0;
for (i = 0; i < pEdidInfo->total_timings; i++)
{
@@ -1440,7 +1496,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
map0 = i;
}
if ( (NVT_PREFERRED_TIMING_IS_CEA(pEdidTiming[i].etc.flag)) ||
if ( (NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) ||
((0 == (flag & NVT_FLAG_EDID_861_ST)) && NVT_PREFERRED_TIMING_IS_DTD1(pEdidTiming[i].etc.flag, pEdidTiming[i].etc.status)) ||
(NVT_PREFERRED_TIMING_IS_DISPLAYID(pEdidTiming[i].etc.flag)) ||
(NVT_IS_NATIVE_TIMING(pEdidTiming[i].etc.status)))
@@ -1479,10 +1535,14 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
}
// find out the preferred timing just in case of cea_vfpdb is existed
if (preferred_cea == pEdidInfo->total_timings &&
NVT_PREFERRED_TIMING_IS_CEA(pEdidTiming[i].etc.flag))
if (native_cta == pEdidInfo->total_timings && NVT_NATIVE_TIMING_IS_CTA(pEdidTiming[i].etc.flag))
{
preferred_cea = i;
native_cta = i;
}
if (preferred_cta == pEdidInfo->total_timings && NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag))
{
preferred_cta = i;
}
// find out the preferred timing just in case
@@ -1741,7 +1801,8 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
if (flag & NVT_FLAG_NV_PREFERRED_TIMING)
{
*pT = (preferred_displayid_dtd != pEdidInfo->total_timings) ? pEdidTiming[preferred_displayid_dtd] :
(preferred_cea != pEdidInfo->total_timings) ? pEdidTiming[preferred_cea] :
(native_cta != pEdidInfo->total_timings) ? pEdidTiming[native_cta] :
(preferred_cta != pEdidInfo->total_timings) ? pEdidTiming[preferred_cta] :
(preferred_dtd1 != pEdidInfo->total_timings) ? pEdidTiming[preferred_dtd1] :
pEdidTiming[dtd1];
// what if DTD1 itself is filtered out, in such case dtd1 index points to an invalid timing[]?
@@ -1998,7 +2059,7 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
{
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION);
return ret;
}
}
// check block 0 checksum value
if (!isChecksumValid(pEdid))
@@ -2313,7 +2374,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
}
else if (ctaBlockTag == NVT_CEA861_TAG_EXTENDED_FLAG)
{
if (*pData_collection == NVT_CEA861_EXT_TAG_HF_EEODB)
if (*pData_collection == NVT_CTA861_EXT_TAG_HF_EEODB)
{
if ((p->bVersionNumber != 0x01) || (p->bRevisionNumber != 0x03))
{
@@ -2334,7 +2395,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
else
pData_collection += ctaPayload;
}
else if (ctaBlockTag == NVT_CEA861_TAG_RSVD || ctaBlockTag == NVT_CEA861_TAG_RSVD1)
else if (ctaBlockTag == NVT_CEA861_TAG_RSVD)
{
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_TAG);
pData_collection += ctaPayload;

760
src/common/modeset/timing/nvt_edidext_861.c
View File

File diff suppressed because it is too large Load Diff

6
src/common/modeset/timing/nvt_edidext_displayid.c
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -1372,9 +1372,9 @@ static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo)
// yuv420-only video
parse861bShortYuv420Timing(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK);
// CEA861-F at 7.5.12 section about VFPDB block.
if (p861info->total_vfpdb != 0)
if (p861info->total_svr != 0)
{
parse861bShortPreferredTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK);
parseCta861NativeOrPreferredTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK);
}
return NVT_STATUS_SUCCESS;

487
src/common/modeset/timing/nvtiming.h
View File

@@ -1,6 +1,6 @@
//****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -278,17 +278,17 @@ typedef enum NVT_TIMING_TYPE
NVT_TYPE_CVT_RB, // CVT timing with reduced blanking
NVT_TYPE_CUST, // Customized timing
NVT_TYPE_EDID_DTD, // EDID detailed timing
NVT_TYPE_EDID_STD, // EDID standard timing
NVT_TYPE_EDID_STD, // = 10 EDID standard timing
NVT_TYPE_EDID_EST, // EDID established timing
NVT_TYPE_EDID_CVT, // EDID defined CVT timing (EDID 1.4)
NVT_TYPE_EDID_861ST, // EDID defined CEA/EIA 861 timing (in the EDID 861 extension)
NVT_TYPE_EDID_861ST, // EDID defined CEA/EIA 861 timing (in the CTA861 extension)
NVT_TYPE_NV_PREDEFINED, // NV pre-defined timings (PsF timings)
NVT_TYPE_DMT_RB, // DMT timing with reduced blanking
NVT_TYPE_EDID_EXT_DTD, // EDID detailed timing in the extension
NVT_TYPE_SDTV, // SDTV timing (including NTSC, PAL etc)
NVT_TYPE_HDTV, // HDTV timing (480p,480i,720p, 1080i etc)
NVT_TYPE_SMPTE, // deprecated ? still used by drivers\unix\nvkms\src\nvkms-dpy.c
NVT_TYPE_EDID_VTB_EXT, // EDID defined VTB extension timing
NVT_TYPE_EDID_VTB_EXT, // = 20 EDID defined VTB extension timing
NVT_TYPE_EDID_VTB_EXT_STD, // EDID defined VTB extension standard timing
NVT_TYPE_EDID_VTB_EXT_DTD, // EDID defined VTB extension detailed timing
NVT_TYPE_EDID_VTB_EXT_CVT, // EDID defined VTB extension cvt timing
@@ -298,13 +298,16 @@ typedef enum NVT_TIMING_TYPE
NVT_TYPE_HDMI_EXT, // EDID defined HDMI extended resolution timing (UHDTV - 4k, 8k etc.)
NVT_TYPE_CUST_AUTO, // Customized timing generated automatically by NVCPL
NVT_TYPE_CUST_MANUAL, // Customized timing entered manually by user
NVT_TYPE_CVT_RB_2, // CVT timing with reduced blanking V2
NVT_TYPE_CVT_RB_2, // = 30 CVT timing with reduced blanking V2
NVT_TYPE_DMT_RB_2, // DMT timing with reduced blanking V2
NVT_TYPE_DISPLAYID_7, // DisplayID 2.0 detailed timing - Type VII
NVT_TYPE_DISPLAYID_8, // DisplayID 2.0 enumerated timing - Type VIII
NVT_TYPE_DISPLAYID_9, // DisplayID 2.0 formula-based timing - Type IX
NVT_TYPE_DISPLAYID_10, // DisplayID 2.0 formula-based timing - Type X
NVT_TYPE_CVT_RB_3, // CVT timing with reduced blanking V3
NVT_TYPE_CTA861_DID_T7, // EDID defined CTA861 DisplayID Type VII timing (in the CTA861 extension)
NVT_TYPE_CTA861_DID_T8, // EDID defined CTA861 DisplayID Type VIII timing (in the CTA861 extension)
NVT_TYPE_CTA861_DID_T10 // EDID defined CTA861 DisplayID Type X timing (in the CTA861 extension)
}NVT_TIMING_TYPE;
//
// 5. the timing sequence number like the TV format and EIA861B predefined timing format
@@ -424,7 +427,9 @@ typedef enum NVT_TV_FORMAT
#define NVT_STATUS_DISPLAYID_9N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_9, n)
#define NVT_STATUS_DISPLAYID_10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_10, n)
#define NVT_STATUS_HDMI_EXTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_HDMI_EXT, n)
#define NVT_STATUS_CTA861_DID_T7N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T7, n)
#define NVT_STATUS_CTA861_DID_T8N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T8, n)
#define NVT_STATUS_CTA861_DID_T10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T10, n)
//********************************
// CEA/EIA 861 related EDID info
@@ -456,7 +461,7 @@ typedef enum NVT_TV_FORMAT
#define NVT_CEA861_SHORT_DESCRIPTOR_TAG_MASK 0xE0
#define NVT_CEA861_SHORT_DESCRIPTOR_TAG_SHIFT 5
//
// the descriptor type tags
// the CTA Tag Codes
#define NVT_CEA861_TAG_RSVD 0 // reserved block
#define NVT_CEA861_TAG_NONE 0 // reserved block
#define NVT_CEA861_TAG_AUDIO 1 // Audio Data Block
@@ -476,33 +481,34 @@ typedef enum NVT_TV_FORMAT
#define NVT_CEA861_EXT_TAG_COLORIMETRY 5 // Colorimetry Data Block
#define NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA 6 // HDR Static Metadata Data Block CEA861.3 HDR extension for HDMI 2.0a
#define NVT_CTA861_EXT_TAG_HDR_DYNAMIC_METADATA 7 // CTA861-H HDR Dynamic Metadata Data Block
#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MIN 8 // 8...12 : Reserved for video-related blocks
#define NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION 8 // CTA861.6 Native Video Resolution Data Block
#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MIN 9 // 9...12 : Reserved for video-related blocks
#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MAX 12
#define NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE 13 // CEA861F Video Format Preference Data Block
#define NVT_CEA861_EXT_TAG_YCBCR420_VIDEO 14 // CEA861F YCBCR 4:2:0 Video Data Block
#define NVT_CEA861_EXT_TAG_YCBCR420_CAP 15 // CEA861F YCBCR 4:2:0 Capability Map Data Block
#define NVT_CEA861_EXT_TAG_MISC_AUDIO 16 // CEA Miscellaneous Audio Fields
#define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_AUDIO 17 // Vendor-Specific Audio Data Block
#define NVT_CEA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block
#define NVT_CTA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block
#define NVT_CTA861_EXT_TAG_ROOM_CONFIGURATION 19 // CTA861-H Room Configuration Data Block
#define NVT_CTA861_EXT_TAG_SPEACKER_LOCATION 20 // CTA861-H Speaker Location Data Block
#define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MIN 21 // 21...31 : Reserved for audio-related blocks
#define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MAX 31
#define NVT_CEA861_EXT_TAG_INFOFRAME 32 // Infoframe Data Block
#define NVT_CEA861_EXT_TAG_RSVD 33 // Reserved
#define NVT_CTA861_EXT_TAG_RSVD 33 // Reserved
#define NVT_CTA861_EXT_TAG_DID_TYPE_VII 34 // DisplayID Type VII Video Timing Data Block
#define NVT_CTA861_EXT_TAG_DID_TYPE_VIII 35 // DisplayID Type VIII Video Timing Data Block
#define NVT_CTA861_EXT_TAG_RSVD_MIN_1 36 // 36...41 : Reserved for general
#define NVT_CTA861_EXT_TAG_RSVD_MAX_1 41
#define NVT_CTA861_EXT_TAG_DID_TYPE_X 42 // DisplayID Type X Video Timing Data Block
#define NVT_CTA861_EXT_TAG_RSVD_MIN_2 43 // 43...119 : Reserved for general
#define NVT_CEA861_EXT_TAG_RSVD_MAX_2 119
#define NVT_CEA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block
#define NVT_CTA861_EXT_TAG_RSVD_MAX_2 119
#define NVT_CTA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block
#define NVT_CTA861_EXT_TAG_SCDB 121 // 0x79 == Tag for Sink Capability Data Block
#define NVT_CEA861_EXT_TAG_HDMI_RSVD_MIN 122 // 122...127 : Reserved for HDMI
#define NVT_CEA861_EXT_TAG_HDMI_RSVD_MAX 127
#define NVT_CEA861_EXT_TAG_RSVD_MIN_3 128 // 128...255 : Reserved for general
#define NVT_CEA861_EXT_TAG_RSVD_MAX_3 255
#define NVT_CTA861_EXT_TAG_HDMI_RSVD_MIN 122 // 122...127 : Reserved for HDMI
#define NVT_CTA861_EXT_TAG_HDMI_RSVD_MAX 127
#define NVT_CTA861_EXT_TAG_RSVD_MIN_3 128 // 128...255 : Reserved for general
#define NVT_CTA861_EXT_TAG_RSVD_MAX_3 255
//
//the extended tag payload size; the size includes the extended tag code
#define NVT_CEA861_EXT_VIDEO_CAP_SD_SIZE 2
@@ -1008,8 +1014,10 @@ typedef struct tagNVT_HDR10PLUS_INFO
#define NVT_CEA861_COLORIMETRY_BT2020YCC 0x40 // BT2020 Y'CbCr capable
#define NVT_CEA861_COLORIMETRY_BT2020RGB 0x80 // BT2020 RGB capable
// Colorimetry capabilities - byte 4
#define NVT_CEA861_COLORIMETRY_DCI_P3 0x80 // DCI-P3
#define NVT_CEA861_COLORIMETRY_defaultRGB 0x10 // based on the default chromaticity in Basic Display Parameters and Feature Block
#define NVT_CEA861_COLORIMETRY_sRGB 0x20 // IEC 61966-2-1
#define NVT_CEA861_COLORIMETRY_ICtCp 0x40 // ITU-R BT.2100 ICtCp
#define NVT_CEA861_COLORIMETRY_ST2113RGB 0x80 // SMPTE ST 2113 R'G'B'
//
// gamut-related metadata capabilities - byte 4
#define NVT_CEA861_GAMUT_METADATA_MASK 0x8F // the colorimetry or gamut-related metadata block mask
@@ -1121,14 +1129,58 @@ typedef struct tagNVT_2BYTES
NvU8 byte2;
} NVT_2BYTES;
#pragma pack(1)
#define NVT_CTA861_DID_MAX_DATA_BLOCK 4
//***********************
// DisplayID 10 Timing Data Block
// DisplayID VII Video Timing Data Block (T7VDB)
//***********************
#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MIN 1
#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MAX 1
#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_LENGTH 20
typedef struct tagDID_TYPE7_DATA
{
struct {
NvU8 revision : 3;
NvU8 dsc_pt : 1;
NvU8 t7_m : 3;
NvU8 F37 : 1;
} version;
NvU8 total_descriptors;
NvU8 payload[29]; // t7_m=0 so only 20byte used
} DID_TYPE7_DATA;
//***********************
// DisplayID VIII Video Timing Data Block (T8VDB)
//***********************
#define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTOR 1
#define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTOR 2
#define NVT_CTA861_DID_TYPE8_DESCRIPTORS_MIN 1
#define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX 28
#define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTORS_MAX 14
typedef struct tagDID_TYPE8_DATA
{
struct {
NvU8 revision : 3;
NvU8 tcs : 1;
NvU8 F34 : 1;
NvU8 t8y420 : 1;
NvU8 code_type : 2;
} version;
NvU8 total_descriptors;
NvU8 payload[NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX]; // used one_byte descriptor length
} DID_TYPE8_DATA;
//***********************
// DisplayID X Video Timing Data Block (T10VDB)
//***********************
#define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN 1
#define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX 4
#define NVT_CTA861_DID_TYPE10_MAX_DATA_BLOCK 4
typedef struct DID_TYPE10_DATA
typedef struct tagDID_TYPE10_DATA
{
struct {
NvU8 revision : 3;
@@ -1138,11 +1190,34 @@ typedef struct DID_TYPE10_DATA
} version;
NvU8 total_descriptors;
NvU8 payload[28]; // given the 7bytes * 4 space
} DID_TYPE10_DATA;
// See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid, e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid
//***********************
// Native Video Resolution Data Block (NVRDB)
//***********************
typedef struct tagNATIVE_VIDEO_RESOLUTION_DATA
{
NvU8 native_svr;
struct {
NvU8 img_size : 1;
NvU8 f41 : 1;
NvU8 f42 : 1;
NvU8 f43 : 1;
NvU8 f44 : 1;
NvU8 f45 : 1;
NvU8 f46 : 1;
NvU8 sz_prec : 1;
} option;
NvU8 image_size[4];
} NATIVE_VIDEO_RESOLUTION_DATA;
#pragma pack()
// See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid,
// e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid
typedef struct tagNVT_VALID_EXTENDED_BLOCKS
{
NvU32 VCDB : 1;
@@ -1158,6 +1233,7 @@ typedef struct tagNVT_VALID_EXTENDED_BLOCKS
NvU32 HF_EEODB : 1;
NvU32 nvda_vsdb : 1;
NvU32 msft_vsdb : 1;
NvU32 NVRDB : 1;
} NVT_VALID_EXTENDED_BLOCKS;
//*************************
@@ -1223,9 +1299,12 @@ typedef struct tagEDID_CEA861_INFO
NVT_5BYTES hdr_static_metadata;
// VFPDB extended block. See CEA861-H, Section 7.5.12 Video Format Preference Data Block
NvU8 total_vfpdb;
NvU8 total_svr;
NvU8 svr_vfpdb[NVT_CEA861_VFPDB_MAX_DESCRIPTOR]; // svr of preferred video formats
// NVRDB extended block. see CTA861.6, Section 7.5.18 Native Video Resolution Data Block
NATIVE_VIDEO_RESOLUTION_DATA native_video_resolution_db;
// Y420VDB extended block. See CEA861-F, Section 7.5.10 YCBCR 4:2:0 Video Data Block
NvU8 total_y420vdb;
NvU8 svd_y420vdb[NVT_CEA861_Y420VDB_MAX_DESCRIPTOR]; // svd of video formats that only support YCbCr 4:2:0
@@ -1238,9 +1317,17 @@ typedef struct tagEDID_CEA861_INFO
NvU32 hfscdbSize;
NvU8 hfscdb[NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH];
// DID Type X Video extended block, see CTA861-H, section 3.5.17.3 DisplayID Type X Video Timing Data Block
NvU8 total_did_type10db;
DID_TYPE10_DATA did_type10_data_block[NVT_CTA861_DID_TYPE10_MAX_DATA_BLOCK];
// DID Type VII Video extended block, see 7.5.17.1 in CTA861-H
NvU8 total_did_type7db;
DID_TYPE7_DATA did_type7_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK];
// DID Type VIII Video extended block, see 7.5.17.2 in CTA861-H
NvU8 total_did_type8db;
DID_TYPE8_DATA did_type8_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK];
// DID Type X Video extended block, see 7.5.17.3 in CTA861-H
NvU8 total_did_type10db;
DID_TYPE10_DATA did_type10_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK];
NvU8 hfeeodb; // HDMI Forum Edid Extension Override Data Block.
} NVT_EDID_CEA861_INFO;
@@ -2153,12 +2240,14 @@ typedef struct tagNVT_HDMI_FORUM_INFO
NvU8 cnmvrr : 1;
NvU8 cinemaVrr : 1;
NvU8 m_delta : 1;
NvU8 qms : 1;
NvU8 fapa_end_extended : 1;
NvU8 rsvd : 1;
NvU16 vrr_min : 6;
NvU16 vrr_max : 10;
NvU8 qms_tfr_min : 1;
NvU8 qms_tfr_max : 1;
NvU16 dsc_MaxSlices : 6;
NvU16 dsc_MaxPclkPerSliceMHz : 10;
@@ -2804,6 +2893,7 @@ typedef struct tagNVT_VIDEO_INFOFRAME_CTRL
NvU16 left_bar;
NvU16 right_bar;
}NVT_VIDEO_INFOFRAME_CTRL;
//
typedef struct tagNVT_AUDIO_INFOFRAME_CTRL
{
@@ -2818,14 +2908,16 @@ typedef struct tagNVT_AUDIO_INFOFRAME_CTRL
typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL
{
NvU32 Enable;
NvU8 HDMIFormat;
NvU8 HDMI_VIC;
NvU8 ThreeDStruc;
NvU8 ThreeDDetail;
NvU8 MetadataPresent;
NvU8 MetadataType;
NvU8 Metadata[8]; // type determines length
NvU32 Enable;
NvU8 HDMIRevision;
NvU8 HDMIFormat;
NvU8 HDMI_VIC;
NvBool ALLMEnable;
NvU8 ThreeDStruc;
NvU8 ThreeDDetail;
NvU8 MetadataPresent;
NvU8 MetadataType;
NvU8 Metadata[8]; // type determines length
} NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL;
#define NVT_3D_METADTATA_TYPE_PARALAX 0x00
@@ -2841,8 +2933,17 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL
NvU32 BaseVFP;
NvU32 ReducedBlanking;
NvU32 BaseRefreshRate;
NvU32 EnableQMS;
} NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL;
typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL
{
NvU32 minVTotal;
NvU32 targetRefreshRate;
NvBool bFixedVTotal;
NvBool bRefreshRateDivider;
}NVT_ADAPTIVE_SYNC_SDP_CTRL;
//***********************************
// the actual Auido/Video Infoframe
//***********************************
@@ -2915,7 +3016,6 @@ typedef struct tagNVT_VIDEO_INFOFRAME
NvU8 left_bar_high;
NvU8 right_bar_low;
NvU8 right_bar_high;
}NVT_VIDEO_INFOFRAME;
//
#define NVT_VIDEO_INFOFRAME_VERSION_1 1
@@ -2949,8 +3049,9 @@ typedef struct tagNVT_VIDEO_INFOFRAME
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_RGB 0
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr422 1
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr444 2
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this lline 4266
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this line 4266
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED 7
// CEA-861-F - Unix still used this one
#define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_MASK 0x60
#define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_SHIFT 0x5
@@ -3069,14 +3170,17 @@ typedef struct tagNVT_VIDEO_INFOFRAME
#define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_MASK 0xFF
#define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_SHIFT 0
//
#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_V4_MASK 0xF0
#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_V4_SHIFT 4
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_0 0
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_1 1
//
#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_MASK 0x0F
#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_SHIFT 0
//
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK 0xF0
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT 4
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3D65RGB 0
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3DCIRGB 1
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_BT2100_ICtCp 2
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_sRGB 3
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_defaultRGB 4
//
#define NVT_VIDEO_INFOFRAME_CONTENT_VIDEO 0
#define NVT_VIDEO_INFOFRAME_CONTENT_GRAPHICS 1
#define NVT_VIDEO_INFOFRAME_CONTENT_PHOTO 2
@@ -3474,6 +3578,33 @@ typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME
//
#define NVT_HDMI_VS_INFOFRAME_VERSION_1 1
#define NVT_HDMI_VS_HB0_MASK 0xFF
#define NVT_HDMI_VS_HB0_SHIFT 0x00
#define NVT_HDMI_VS_HB0_VALUE 0x01
#define NVT_HDMI_VS_HB1_MASK 0xFF
#define NVT_HDMI_VS_HB1_SHIFT 0x00
#define NVT_HDMI_VS_HB1_VALUE 0x01
#define NVT_HDMI_VS_HB2_MASK 0xFF
#define NVT_HDMI_VS_HB2_SHIFT 0x00
#define NVT_HDMI_VS_HB2_VALUE 0x06
#define NVT_HDMI_VS_BYTE1_OUI_MASK 0xff
#define NVT_HDMI_VS_BYTE1_OUI_SHIFT 0x00
#define NVT_HDMI_VS_BYTE1_OUI_VER_1_4 0x03
#define NVT_HDMI_VS_BYTE1_OUI_VER_2_0 0xD8
#define NVT_HDMI_VS_BYTE2_OUI_MASK 0xff
#define NVT_HDMI_VS_BYTE2_OUI_SHIFT 0x00
#define NVT_HDMI_VS_BYTE2_OUI_VER_1_4 0x0C
#define NVT_HDMI_VS_BYTE2_OUI_VER_2_0 0x5D
#define NVT_HDMI_VS_BYTE3_OUI_MASK 0xff
#define NVT_HDMI_VS_BYTE3_OUI_SHIFT 0x00
#define NVT_HDMI_VS_BYTE3_OUI_VER_1_4 0x00
#define NVT_HDMI_VS_BYTE3_OUI_VER_2_0 0xC4
//
#define NVT_HDMI_VS_BYTE4_RSVD_MASK 0x1f
#define NVT_HDMI_VS_BYTE4_RSVD_SHIFT 0x00
@@ -3500,6 +3631,10 @@ typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME
#define NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT 0x03
#define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES 0x00 // HDMI Metadata is not present
#define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES 0x01 // HDMI Metadata is present
#define NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK 0x02 // ALLM is field of length 1 bit at Bit Number 1
#define NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS 0x00
#define NVT_HDMI_VS_BYTE5_ALLM_MODE_EN 0x01
#define NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT 0x01 // ALLM is byte5 bit position 1, so shift 1 bit
#define NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK 0xf0
#define NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT 0x04
#define NVT_HDMI_VS_BYTE5_HDMI_3DS_NA 0xfe
@@ -3566,83 +3701,184 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME
NVT_EXTENDED_METADATA_PACKET_INFOFRAME_PAYLOAD Data;
} NVT_EXTENDED_METADATA_PACKET_INFOFRAME;
#define NVT_HDMI_EMP_BYTE1_RSVD_MASK 0x01
#define NVT_HDMI_EMP_BYTE1_RSVD_SHIFT 0
#define NVT_HDMI_EMP_BYTE1_RSVD_MASK 0x01
#define NVT_HDMI_EMP_BYTE1_RSVD_SHIFT 0
#define NVT_HDMI_EMP_BYTE1_SYNC_MASK 0x02
#define NVT_HDMI_EMP_BYTE1_SYNC_SHIFT 1
#define NVT_HDMI_EMP_BYTE1_SYNC_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_SYNC_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_SYNC_MASK 0x02
#define NVT_HDMI_EMP_BYTE1_SYNC_SHIFT 1
#define NVT_HDMI_EMP_BYTE1_SYNC_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_SYNC_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_VFR_MASK 0x04
#define NVT_HDMI_EMP_BYTE1_VFR_SHIFT 2
#define NVT_HDMI_EMP_BYTE1_VFR_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_VFR_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_VFR_MASK 0x04
#define NVT_HDMI_EMP_BYTE1_VFR_SHIFT 2
#define NVT_HDMI_EMP_BYTE1_VFR_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_VFR_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_AFR_MASK 0x08
#define NVT_HDMI_EMP_BYTE1_AFR_SHIFT 3
#define NVT_HDMI_EMP_BYTE1_AFR_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_AFR_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_AFR_MASK 0x08
#define NVT_HDMI_EMP_BYTE1_AFR_SHIFT 3
#define NVT_HDMI_EMP_BYTE1_AFR_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_AFR_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_MASK 0x30
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_SHIFT 4
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_PSEUDO_STATIC 0
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_DYNAMIC 1
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_UNIQUE 2
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_RSVD 3
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_MASK 0x30
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_SHIFT 4
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_PSEUDO_STATIC 0
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_DYNAMIC 1
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_UNIQUE 2
#define NVT_HDMI_EMP_BYTE1_DS_TYPE_RSVD 3
#define NVT_HDMI_EMP_BYTE1_END_MASK 0x40
#define NVT_HDMI_EMP_BYTE1_END_SHIFT 6
#define NVT_HDMI_EMP_BYTE1_END_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_END_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_END_MASK 0x40
#define NVT_HDMI_EMP_BYTE1_END_SHIFT 6
#define NVT_HDMI_EMP_BYTE1_END_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_END_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_NEW_MASK 0x80
#define NVT_HDMI_EMP_BYTE1_NEW_SHIFT 7
#define NVT_HDMI_EMP_BYTE1_NEW_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_NEW_ENABLE 1
#define NVT_HDMI_EMP_BYTE1_NEW_MASK 0x80
#define NVT_HDMI_EMP_BYTE1_NEW_SHIFT 7
#define NVT_HDMI_EMP_BYTE1_NEW_DISABLE 0
#define NVT_HDMI_EMP_BYTE1_NEW_ENABLE 1
#define NVT_HDMI_EMP_BYTE2_RSVD_MASK 0xff
#define NVT_HDMI_EMP_BYTE2_RSVD_SHIFT 0
#define NVT_HDMI_EMP_BYTE2_RSVD_MASK 0xff
#define NVT_HDMI_EMP_BYTE2_RSVD_SHIFT 0
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_MASK 0xff
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SHIFT 0
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VENDOR_SPECIFIC 0
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SPEC_DEFINED 1
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_CTA_DEFINED 2
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VESA_DEFINED 3
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_MASK 0xff
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SHIFT 0
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VENDOR_SPECIFIC 0
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SPEC_DEFINED 1
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_CTA_DEFINED 2
#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VESA_DEFINED 3
#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK 0x01
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK 0x01
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x01
#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT 1
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x01
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT 2
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_MASK 0xff
#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_MASK 0xff
#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD2_RB_MASK 0x04
#define NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT 2
#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD2_RB_MASK 0x04
#define NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT 2
#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03
#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03
#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_MASK 0xff
#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_PACKET_TYPE 0x22
#define NVT_DP_ADAPTIVE_SYNC_SDP_VERSION 0x2
#define NVT_DP_ADAPTIVE_SYNC_SDP_LENGTH 0x9
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK 0x3
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_VARIABLE 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_FIXED 1
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_NOT_REACHED 2
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_REACHED 3
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_MASK 0x4
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SHIFT 2
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_ENABLED 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_DISABLED 1
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_MASK 0x8
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_SHIFT 3
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_NO_UPDATE 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_UPDATE 1
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_MASK 0xf0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_SHIFT 4
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK 0x01
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_MASK 0x1c
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_SHIFT 2
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK 0x20
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT 5
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_DISABLE 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_ENABLE 1
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_MASK 0x40
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_SHIFT 6
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_DISABLE 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_ENABLE 1
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_MASK 0x80
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_SHIFT 7
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_DISABLE 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_ENABLE 1
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_SHIFT 0
typedef struct tagNVT_ADAPTIVE_SYNC_SDP_HEADER
{
NvU8 hb0;
NvU8 type;
NvU8 version;
NvU8 length;
}NVT_ADAPTIVE_SYNC_SDP_HEADER;
typedef struct tagNVT_ADAPTIVE_SYNC_SDP_PAYLOAD
{
NvU8 db0; // operatingMode
NvU8 db1; // minVTotalLSB
NvU8 db2; // minVTotalMSB
NvU8 db3; // targetRefreshRateLSB
NvU8 db4; // targetRefreshRateMSB, rsvd, targetRRDivider, frameInc/Dec Config
NvU8 db5; // frameDurationIncMs
NvU8 db6; // frameDurationDecreaseMs
NvU8 db7; // coastingVTotalPrLSB
NvU8 db8; // coastingVTotalPrMSB
NvU8 rsvd[23];
}NVT_ADAPTIVE_SYNC_SDP_PAYLOAD;
typedef struct tagADAPTIVE_SYNC_SDP
{
NVT_ADAPTIVE_SYNC_SDP_HEADER header;
NVT_ADAPTIVE_SYNC_SDP_PAYLOAD payload;
}NVT_ADAPTIVE_SYNC_SDP;
// the Vendor-Specific-Data-Block header
typedef struct tagNVT_CEA861_VSDB_HEADER
@@ -3814,7 +4050,7 @@ typedef struct tagNVT_HDMI_FORUM_VSDB_PAYLOAD
NvU8 CNMVRR : 1;
NvU8 CinemaVRR : 1;
NvU8 M_delta : 1;
NvU8 Rsvd_2 : 1;
NvU8 QMS : 1;
NvU8 FAPA_End_Extended : 1;
// sixth byte
@@ -3827,7 +4063,8 @@ typedef struct tagNVT_HDMI_FORUM_VSDB_PAYLOAD
NvU8 DSC_12bpc : 1;
NvU8 DSC_16bpc : 1;
NvU8 DSC_All_bpp : 1;
NvU8 Rsvd_3 : 2;
NvU8 QMS_TFR_min : 1;
NvU8 QMS_TFR_max : 1;
NvU8 DSC_Native_420 : 1;
NvU8 DSC_1p2 : 1;
// ninth byte
@@ -5344,13 +5581,11 @@ typedef enum
#define NVT_FLAG_NV_PREFERRED_TIMING 0x00040000
#define NVT_FLAG_DTD1_PREFERRED_TIMING 0x00080000
#define NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING 0x00100000
#define NVT_FLAG_CEA_PREFERRED_TIMING 0x00200000
#define NVT_FLAG_CTA_PREFERRED_TIMING 0x00200000
#define NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU 0x00400000
#define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20
#define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated
#define NVT_FLAG_DISPLAYID_T7_TIMING 0x02000000
#define NVT_FLAG_DISPLAYID_T8_TIMING 0x04000000
#define NVT_FLAG_DISPLAYID_T10_TIMING 0x08000000
#define NVT_FLAG_CTA_NATIVE_TIMING 0x02000000 // NVRDB defined
#define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2)
@@ -5377,8 +5612,10 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// DMT timing calculation
NVT_STATUS NvTiming_EnumDMT(NvU32 dmtId, NVT_TIMING *pT);
NVT_STATUS NvTiming_EnumStdTwoBytesCode(NvU16 std2ByteCodes, NVT_TIMING *pT);
NVT_STATUS NvTiming_CalcDMT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
NVT_STATUS NvTiming_CalcDMT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
// CVT timing calculation
NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
@@ -5427,9 +5664,7 @@ NvU32 NvTiming_DisplayID2ValidationMask(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo,
NVT_STATUS NvTiming_DisplayID2ValidationDataBlocks(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, NvBool bIsStrongValidation);
NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8 tag, NvU32 *dtdIndex);
NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo,
NvU8 *pProductName,
const NvU32 productNameLength);
NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo, NvU8 *pProductName, const NvU32 productNameLength);
NvU32 NvTiming_CalculateEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidsize);
NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion);
NVT_STATUS NvTiming_CalculateEDIDLimits(NVT_EDID_INFO *pEdidInfo, NVT_EDID_RANGE_LIMIT *pLimit);
@@ -5442,17 +5677,18 @@ NvU32 a_div_b(NvU32 a, NvU32 b);
NvU32 calculateCRC32(NvU8* pBuf, NvU32 bufsize);
void patchChecksum(NvU8* pBuf);
NvBool isChecksumValid(NvU8* pBuf);
NvU32 RRx1kToPclk (NVT_TIMING *pT);
NVT_STATUS NvTiming_ComposeCustTimingString(NVT_TIMING *pT);
// Infoframe composer
NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_VIDEO_INFOFRAME_CTRL *pCtrl);
NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_INFOFRAME_CTRL *pCtrl, NVT_VIDEO_INFOFRAME *pContext, NVT_VIDEO_INFOFRAME *p);
NVT_STATUS NvTiming_ConstructAudioInfoframe(NVT_AUDIO_INFOFRAME_CTRL *pCtrl, NVT_AUDIO_INFOFRAME *pContext, NVT_AUDIO_INFOFRAME *p);
NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pCtrl, NVT_VENDOR_SPECIFIC_INFOFRAME *p);
NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL *pCtrl, NVT_EXTENDED_METADATA_PACKET_INFOFRAME *p);
// Infoframe/SDP composer
NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_VIDEO_INFOFRAME_CTRL *pCtrl);
NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_INFOFRAME_CTRL *pCtrl, NVT_VIDEO_INFOFRAME *pContext, NVT_VIDEO_INFOFRAME *p);
NVT_STATUS NvTiming_ConstructAudioInfoframe(NVT_AUDIO_INFOFRAME_CTRL *pCtrl, NVT_AUDIO_INFOFRAME *pContext, NVT_AUDIO_INFOFRAME *p);
NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pCtrl, NVT_VENDOR_SPECIFIC_INFOFRAME *p);
NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL *pCtrl, NVT_EXTENDED_METADATA_PACKET_INFOFRAME *p);
void NvTiming_ConstructAdaptiveSyncSDP(const NVT_ADAPTIVE_SYNC_SDP_CTRL *pCtrl, NVT_ADAPTIVE_SYNC_SDP *p);
// Get specific timing from parsed EDID
NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT);
@@ -5460,15 +5696,22 @@ NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT);
#define NVT_IS_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_DTD)
#define NVT_IS_EXT_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_EXT_DTD)
#define NVT_IS_CTA861(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_861ST)
#define NVT_IS_CTA861_DID_T7(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T7)
#define NVT_IS_CTA861_DID_T8(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T8)
#define NVT_IS_CTA861_DID_T10(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T10)
#define NVT_IS_DTD1(d) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1))
#define NVT_IS_DTDn(d, n) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
#define NVT_IS_EXT_DTDn(d, n) ((NVT_IS_EXT_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
#define NVT_IS_DTD1(d) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1))
#define NVT_IS_DTDn(d, n) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
#define NVT_IS_EXT_DTDn(d, n) ((NVT_IS_EXT_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
#define NVT_IS_CTA861_DID_T7n(d, n) ((NVT_IS_CTA861_DID_T7((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
#define NVT_IS_CTA861_DID_T8_1(d) ((NVT_IS_CTA861_DID_T8((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1))
#define NVT_IS_CTA861_DID_T10n(d, n) ((NVT_IS_CTA861_DID_T10((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
#define NVT_DID20_TIMING_IS_CTA861(flag, status) ((NVT_IS_CTA861((status))) && (0 != (NVT_FLAG_DISPLAYID_2_0_TIMING & (flag))))
#define NVT_PREFERRED_TIMING_IS_DTD1(flag, status) ((NVT_IS_DTD1((status))) && (0 != (NVT_FLAG_DTD1_PREFERRED_TIMING & (flag))))
#define NVT_PREFERRED_TIMING_IS_DISPLAYID(flag) (0 != (NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING & flag))
#define NVT_PREFERRED_TIMING_IS_CEA(flag) (0 != (NVT_FLAG_CEA_PREFERRED_TIMING & flag))
#define NVT_PREFERRED_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_PREFERRED_TIMING & flag))
#define NVT_NATIVE_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_NATIVE_TIMING & flag))
#ifdef __cplusplus
}

12
src/common/modeset/timing/nvtiming_pvt.h
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,7 +68,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *pEdid, NvU32 size, NVT_EDID_CEA861_INF
void parse861ExtDetailedTiming(NvU8 *pEdidExt, NvU8 basicCaps, NVT_EDID_INFO *pInfo);
void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861HfScdb(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861, NvU32 *pTotalEdidExtensions);
@@ -81,8 +81,12 @@ void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsd
void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861DIDType7VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
void parseCta861DIDType8VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
NvBool isMatchedCTA861Timing(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
NvU32 isHdmi3DStereoType(NvU8 StereoStructureType);
NvU32 getCEA861TimingAspectRatio(NvU32 vic);
void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming);
@@ -96,7 +100,9 @@ NVT_STATUS getDisplayIdEDIDExtInfo(NvU8* pEdid, NvU32 edidSize, NVT_EDID_INFO* p
NVT_STATUS parseDisplayIdBlock(NvU8* pBlock, NvU8 max_length, NvU8* pLength, NVT_EDID_INFO* pEdidInfo);
NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo);
NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo);
NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes);
NVT_STATUS parseDisplayId20Timing7Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 count);
NVT_STATUS parseDisplayId20Timing8Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 codeType, NvU8 codeSize, NvU8 index, NvU8 count);
NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes, NvU8 count);
void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx);
void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx);
NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming);