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535.43.02

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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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27
src/common/modeset/timing/displayid20.h
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@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -275,7 +275,7 @@ typedef struct _tagDISPLAYID_2_0_TIMING_7_BLOCK
#define DISPLAYID_2_0_TIMING_DSC_PASSTHRU_TIMING 1
// the following fields apply to Timing Descriptors 7 (Not all of them are
// the following fields apply to Timing 7 Descriptors (Not all of them are
// used per descriptor, but the format is the same
#define DISPLAYID_2_0_TIMING_ASPECT_RATIO_1_1 0
#define DISPLAYID_2_0_TIMING_ASPECT_RATIO_5_4 1
@@ -308,29 +308,15 @@ typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK_HEADER
NvU8 data_bytes; // Values range from 1(0x01) to 248(0xF8)
} DISPLAYID_2_0_TIMING_8_BLOCK_HEADER;
typedef struct _tagDISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE
{
NvU8 timing_code;
} DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE;
typedef struct _tagDISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE
{
NvU8 timing_code[2];
} DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE;
#define DISPLAYID_2_0_TIMING_8_MAX_CODES 248
typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK
{
DISPLAYID_2_0_TIMING_8_BLOCK_HEADER header;
union
{
DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE timing_code_1[DISPLAYID_2_0_TIMING_8_MAX_CODES];
DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE timing_code_2[DISPLAYID_2_0_TIMING_8_MAX_CODES / 2];
};
NvU8 timingCode[DISPLAYID_2_0_TIMING_8_MAX_CODES];
} DISPLAYID_2_0_TIMING_8_BLOCK;
// the following fields apply to Timing 8 Descriptors
#define DISPLAYID_2_0_TIMING_CODE_DMT 0
#define DISPLAYID_2_0_TIMING_CODE_CTA_VIC 1
#define DISPLAYID_2_0_TIMING_CODE_HDMI_VIC 2
@@ -353,6 +339,7 @@ typedef struct _TAG_DISPLAYID_2_0_TIMING_9_DESCRIPTOR
NvU8 refresh_rate; // 1 Hz to 256 Hz
} DISPLAYID_2_0_TIMING_9_DESCRIPTOR;
// the following fields apply to Timing 9/10 Descriptors
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD 0
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1 1
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2 2
@@ -384,8 +371,8 @@ typedef struct _DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR
{
struct {
NvU8 timing_formula :3;
NvU8 early_vsync :1;
NvU8 rr1000div1001_or_hblank :1;
NvU8 early_vsync :1;
NvU8 rr1000div1001_or_hblank :1;
NvU8 stereo_support :2;
NvU8 ycc420_support :1;
} options;