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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000base.finn
// Source file: ctrl/ctrl0000/ctrl0000base.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000client.finn
// Source file: ctrl/ctrl0000/ctrl0000client.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000event.finn
// Source file: ctrl/ctrl0000/ctrl0000event.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
@@ -143,7 +143,8 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
* GPU instance numbers are assigned in bus-probe order beginning with
* zero and are limited to one less the number of GPUs in the system.
* [out] numaId
* This parameter returns the ID of NUMA node for the specified GPU.
* This parameter returns the ID of NUMA node for the specified GPU or
* the subscribed MIG partition when MIG is enabled.
* In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned.
*
* Possible status values returned are:

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

56
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000system.finn
// Source file: ctrl/ctrl0000/ctrl0000system.finn
//
#include "ctrl/ctrlxxxx.h"
@@ -296,8 +296,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
/* Generic types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U)
/* processor capabilities */
#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U)
@@ -322,47 +321,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U)
#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U)
/* feature mask (as opposed to bugs, requirements, etc.) */
#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CAPS
*
* This command returns the set of system capabilities in the
* form of an array of unsigned bytes. System capabilities include
* supported features and required workarounds for the system,
* each represented by a byte offset into the table and a bit
* position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the system caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */
typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01
/* size in bytes of system caps table */
#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO
*
@@ -419,13 +377,13 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
/* maximum name string length */
#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U)
#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U)
/* invalid id */
#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU)
#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU)
#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U)
@@ -1572,9 +1530,11 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS {
* Please note: as implied above, administrator privileges are
* required to modify security settings.
*/
#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */
#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */
#define GPS_MAX_COUNTERS_PER_BLOCK 32U
#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS {
NvU32 objHndl;
NvU32 blockId;

7
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
@@ -418,8 +418,7 @@ typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC 4
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"