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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h
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@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080acr.finn
// Source file: ctrl/ctrl2080/ctrl2080acr.finn
//

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080base.finn
// Source file: ctrl/ctrl2080/ctrl2080base.finn
//
#include "ctrl/ctrlxxxx.h"
@@ -92,6 +92,7 @@
#define NV2080_CTRL_GRMGR (0x38)
#define NV2080_CTRL_UCODE_FUZZER (0x39)
#define NV2080_CTRL_DMABUF (0x3A)
#define NV2080_CTRL_BIF (0x3B)
// per-OS categories start at highest category and work backwards
#define NV2080_CTRL_OS_WINDOWS (0x3F)

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080bios.finn
// Source file: ctrl/ctrl2080/ctrl2080bios.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn
// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
//

8
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080bus.finn
// Source file: ctrl/ctrl2080/ctrl2080bus.finn
//
#include "nvcfg_sdk.h"
@@ -1419,6 +1419,11 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
* NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
*/
/*
* in either self-hosted mode or
* externally-hostedmode.
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */
@@ -1545,6 +1550,7 @@ typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS {
NvU32 connectionType;
NvU32 peerId;
NvBool bEgmPeer;
NvBool bSpaAccessOnly;
NvBool bUseUuid;
NvU32 remoteGpuId;

14
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ce.finn
// Source file: ctrl/ctrl2080/ctrl2080ce.finn
//
@@ -98,8 +98,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02
#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04
/*
* NV2080_CTRL_CE_CAPS_CE_GRCE
@@ -133,10 +132,11 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
*
* NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL
* Set if the CE supports pipelined Block Linear
*
* NV2080_CTRL_CE_CAPS_CE_CC_SECURE
* Set if the CE is capable of encryption/decryption
*/
/*
* NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
*
@@ -298,7 +298,7 @@ typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {
#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_MAX_HSHUBS 5
#define NV2080_CTRL_CE_MAX_HSHUBS 32
#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h
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@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080cipher.finn
// Source file: ctrl/ctrl2080/ctrl2080cipher.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clk.finn
// Source file: ctrl/ctrl2080/ctrl2080clk.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn
// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dma.finn
// Source file: ctrl/ctrl2080/ctrl2080dma.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn
// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080event.finn
// Source file: ctrl/ctrl2080/ctrl2080event.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h
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@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
//

347
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fb.finn
// Source file: ctrl/ctrl2080/ctrl2080fb.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -419,27 +419,6 @@ typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS {
NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE];
} NV2080_CTRL_FB_GET_INFO_V2_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO
*
* This command returns tile addressing information.
*
* StartAddr
* This parameter returns BAR1 plus the size of the local FB.
* SpaceSize
* This parameter returns the BAR1 aperture size less the size of the
* local FB.
*
* Note that both parameters will contain zero if there is no system tile
* address space.
*/
#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */
typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO {
NV_DECLARE_ALIGNED(NvU64 StartAddr, 8);
NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8);
} NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO;
/*
* NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET
*
@@ -537,53 +516,8 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS;
/* valid flags parameter values */
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED
*
* This command specifies to RM if scanout compaction feature is allowed or
* not in the current configuration. In hybrid mode when dGPU is rendering the
* image, the dGPU blit to the scanout surface happens without mGPU's
* knowledge (directly to system memory), which results in stale compacted
* data resulting in corruption.
*
* This control call can be used to disable the compaction whenever the KMD
* (client) is switching to the pref mode in Hybrid i.e., whenever there is a
* possibility of dGPU doing a blit to mGpu scanout surface. Compaction can
* be enabled when system is back in hybrid power mode as mGpu will be
* rendering the image.
*
* allowCompaction
* This parameter specifies if the display compaction feature is allowed
* or not allowed.
* immediate
* This parameter specifies whether compaction has to be enabled or
* disabled immediately (based on the value of allowCompaction field) or
* during the next modeset.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_INVALID_PARAM_STRUCT
* NVOS_STATUS_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM
typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS {
NvU32 allowCompaction;
NvU32 immediate;
} NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS;
/* valid allowCompaction values */
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001U)
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000U)
/* valid immediate values */
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001U)
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
@@ -628,9 +562,9 @@ typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS {
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU)
@@ -1615,239 +1549,6 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS {
NvBool upper64KBCompbitSel;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of PutCompBits.
*
* @params[out] NvU32 *fcbits;
* Buffer to receive Fast Clear Bits.
* @params[out] NvU32 *compbits;
* Buffer to receive Compression Bits.
* @params[out] NvU32 *compCacheLine;
* Buffer to receive Comp Cache Line data.
* @params[in] NvU64 dataPhysicalStart;
* Start Address of Data
* @params[in] NvU64 surfaceOffset;
* Offset in the surface
* @params[in] NvU32 comptagLine;
* Compression Tag Line Number
* @params[in] NvU32 ROPTile_offset;
* Offset in the surface of the ROP tile.
* @params[in] NvBool upper64KBCompbitSel;
* Selects Upper or Lower 64K
* @params[in] NvBool getFcBits;
* Indicates if fast clear bits should be returned.
* @params[in] NvP64 derivedParams
* Actually a CompBitDerivedParams structure.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS {
NV_DECLARE_ALIGNED(NvU32 *fcbits, 8);
NV_DECLARE_ALIGNED(NvU32 *compbits, 8);
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
NvU32 comptagLine;
NvU32 ROPTile_offset;
NvBool upper64KBCompbitSel;
NvBool getFcBits;
NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of GetCompBits.
*
* @params[in] NvU32 fcbits;
* Buffer with Fast Clear Bits to write.
* @params[in] NvU32 compbits;
* Buffer to receive Compression Bits.
* @params[in] NvBool writeFc
* Indicates of Fast Clear Bits should be written.
* @params[in] NvU32 *compCacheLine;
* Buffer to receive Comp Cache Line data.
* @params[in] NvU64 dataPhysicalStart;
* Start Address of Data
* @params[in] NvU64 surfaceOffset;
* Offset in the surface
* @params[in] NvU32 comptagLine;
* Compression Tag Line Number
* @params[in] NvU32 ROPTile_offset;
* Offset in the surface of the ROP tile.
* @params[in] NvBool upper64KBCompbitSel;
* Selects Upper or Lower 64K
* @params[in] NvP64 derivedParams
* Actually a CompBitDerivedParams structure.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS {
NvU32 fcbits;
NvU32 compbits;
NvBool writeFc;
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
NvU32 comptagLine;
NvU32 ROPTile_offset;
NvBool upper64KBCompbitSel;
NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of ReadCompCacheLine.
*
* @paramsNvU32 *compCacheLine;
* Buffer for Comp Cache Line Read
* @paramsNvU32 comptagLine;
* Comp Tag Line Number to read
* @paramsNvU32 partition;
* FB Partition of the desired Comp Cache Line
* @paramsNvU32 slice;
* Slice of the desired Comp Cache Line
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS {
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NvU32 comptagLine;
NvU32 partition;
NvU32 slice;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of WriteCompCacheLine.
*
* @params[in] NvU32 *compCacheLine;
* Buffer for Comp Cache Line to Write
* @params[in] NvU32 comptagLine;
* Comp Tag Line Number to Write
* @params[in] NvU32 partition;
* FB Partition of the desired Comp Cache Line
* @params[in] NvU32 slice;
* Slice of the desired Comp Cache Line
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS {
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NvU32 comptagLine;
NvU32 partition;
NvU32 slice;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS < Deprecated >
*
* Used by PS (Performance Path, or Optimized path, or Per Slice version)
* to retrieve upper and lower Address of the CompCacheLine.
*
* @params[out] NvU64 *minCPUAddress;
* Minimum (lower bound) of the ComCacheLine.
* @params[out] NvU64 *minCPUAddress;
* Minimum (lower bound) of the ComCacheLine.
* @params[in] NvU32 comptagLine;
* CompTagLine to fetch the bounds of.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8);
NV_DECLARE_ALIGNED(NvU64 *maxCPUAddress, 8);
NvU32 comptagLine;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET < Deprecated >
*
* Used by PS (Performance Path, or Optimized path, or Per Slice version)
* to retrieve partition, slice and ROP Tile Offset of the passed in
* surface location.
*
* @params[out] NvU64 *part;
* Partition in which the target part of the surface resides.
* @params[out] NvU64 *slice;
* Slice in which the target part of the surface resides.
* @params[out] NvU64 *ropTileoffset;
* Offset to the start of the ROP Tile in which the target part of
* the surface resides.
* @params[in] NvU64 *dataPhysicalStart;
* Start address of data for which part/slice/offset is desired.
* @params[in] NvU64 surfaceOffset;
* Byte offset of data for which part/slice/offset is desired.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS {
NV_DECLARE_ALIGNED(NvU64 *part, 8);
NV_DECLARE_ALIGNED(NvU64 *slice, 8);
NV_DECLARE_ALIGNED(NvU64 *ropTileoffset, 8);
NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS < Deprecated >
*
* Used by PS (Performance Path, or Optimized path, or Per Slice version)
* to create a CompBitCopy::CompBitDerivedParams object
*
* @params[out] NvP64 derivedParams
* Actually a CompBitDerivedParams structure.
* @params[in] NvU32 comptagLine;
* Compression Tag Line Number
* @params[in] NvU32 ROPTile_offset;
* Offset in the surface of the ROP tile.
* @params[in] NvBool upper64KBCompbitSel;
* Selects Upper or Lower 64K
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
NvU32 comptagLine;
NvBool upper64KBCompbitSel;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 < Deprecated >
*
@@ -2876,8 +2577,9 @@ typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS {
/*
* NV2080_CTRL_CMD_FB_GET_NUMA_INFO
*
* This control command is used by clients to get per-subdevice NUMA memory
* information as assigned by the system.
* This control command is used by clients to get per-subdevice or
* subscribed MIG partition(when MIG is enabled) NUMA memory information as
* assigned by the system.
*
* numaNodeId[OUT]
* - Specifies the NUMA node ID.
@@ -2916,4 +2618,37 @@ typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8);
} NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT
*
* This control command is used by clients to get NV_SEMAPHORE_SURFACE layout/caps before allocation.
* A semaphore surface can be viewed as an array of independent semaphore entries.
*
* maxSubmittedSemaphoreValueOffset[OUT]
* - An offset of the max submitted value, relative to the semaphore surface entry start, if used.
* Used to emulate 64-bit semaphore values on chips where 64-bit semaphores are not supported.
*
* monitoredFenceThresholdOffset[OUT]
* - An offset of the monitored fence memory, relative to the semaphore surface entry start, if supported.
*
* size[OUT]
* - A size of a single semaphore surface entry.
*
* caps[OUT]
* - A mask of NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_* values.
*/
#define NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT (0x20801352U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED (0x00000001U)
#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED (0x00000002U)
#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID (0x52U)
typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 maxSubmittedSemaphoreValueOffset, 8);
NV_DECLARE_ALIGNED(NvU64 monitoredFenceThresholdOffset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 caps;
} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS;
/* _ctrl2080fb_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fla.finn
// Source file: ctrl/ctrl2080/ctrl2080fla.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fuse.finn
// Source file: ctrl/ctrl2080/ctrl2080fuse.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

55
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpu.finn
// Source file: ctrl/ctrl2080/ctrl2080gpu.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -103,11 +103,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU)
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU)
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000040U)
/* valid minor revision extended values */
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U)
@@ -198,6 +203,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U)
/* valid local EGM supported values */
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID 31:1
/* valid self hosted values */
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U)
/* valid CMP (Crypto Mining Processor) SKU values */
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U)
@@ -208,6 +223,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U)
/* valid resetless MIG device supported values */
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_GPU_GET_INFO
*
@@ -2585,7 +2604,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
@@ -2598,6 +2617,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH))
#define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U)
@@ -3264,7 +3284,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO {
NvU32 gfxGrCount;
NvU32 gpcCount;
NvU32 virtualGpcCount;
NvU32 grGpcCount;
NvU32 gfxGpcCount;
NvU32 veidCount;
NvU32 smCount;
NvU32 ceCount;
@@ -3322,7 +3342,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS {
#define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS {
NvU32 maxSupportedPageSize;
NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8);
} NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS;
@@ -3720,6 +3740,9 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
* bEnable [IN]
* - Set to NV_TRUE if the GPU partition has been activated.
* - Set to NV_FALSE if the GPU partition will be deactivated.
* fabricPartitionId [IN]
* - Set the fabric manager partition ID dring partition activation.
* - Ignored during partition deactivation.
*
* Possible status values returned are:
* NV_OK
@@ -3735,6 +3758,7 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS {
NvU32 gfid;
NvBool bEnable;
NvU32 fabricPartitionId;
} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS;
/*!
@@ -3763,6 +3787,23 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
NvU32 protection;
} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR
*
* @brief This command is similar to NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR
* but will be used to set the EGM fabric base addr associated with the gpu.
* Note: For EGM FLA, we will be making use of the existing control call i.e
* NV2080_CTRL_CMD_FLA_RANGE
*
*/
#define NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR (0x20800199U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x99U)
typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8);
} NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS;
/*
@@ -3788,7 +3829,7 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
*/
#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xA0U
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC0U
#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU)

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn
// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn
//

7
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gr.finn
// Source file: ctrl/ctrl2080/ctrl2080gr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -256,6 +256,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

52
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -79,4 +79,52 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
/*
* NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS
*
* This command reports the current GSP-RM heap usage statistics.
*
* managedSize
* The total size in bytes of the underlying heap. Note that not all memory
* will be allocatable, due to fragmentation and memory allocator/tracking
* overhead.
* current
* An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
* GSP-RM heap usage at the time this command is called.
* peak
* An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
* the "high water mark" of heap usage since GSP-RM was started.
*/
#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
*
* This record represents a set of heap measurements at a given point in time.
*
* allocatedSize
* Allocated memory size, in bytes. This value does not include overhead used
* by the underlying allocator for padding/metadata, but does include the
* NvPort memory tracking overhead.
* usableSize
* Allocated memory size excluding all metadata, in bytes. This value does
* not include the NvPort memory tracking overhead.
* memTrackOverhead
* Allocated memory size used for NvPort memory tracking.
*/
typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT {
NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8);
NV_DECLARE_ALIGNED(NvU64 usableSize, 8);
NV_DECLARE_ALIGNED(NvU64 memTrackOverhead, 8);
NvU32 allocationCount;
} NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT;
#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8);
} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS;
// _ctrl2080gsp_h_

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080illum.finn
// Source file: ctrl/ctrl2080/ctrl2080illum.finn
//

404
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080internal.finn
// Source file: ctrl/ctrl2080/ctrl2080internal.finn
//
#include "nvimpshared.h"
@@ -38,6 +38,7 @@
#include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */
#include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */
#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */
#include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrl90f1.h"
#include "ctrl/ctrl30f1.h"
@@ -152,6 +153,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
* This command sends access counter buffer pages allocated by CPU-RM
* to be setup and enabled in physical RM.
*
* accessCounterIndex
* Index of access counter buffer to register.
*
* bufferSize
* Size of the access counter buffer to register.
*
@@ -167,6 +171,7 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
#define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU)
typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS {
NvU32 accessCounterIndex;
NvU32 bufferSize;
NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8);
} NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS;
@@ -176,39 +181,19 @@ typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS {
*
* This command requests physical RM to disable the access counter buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */
/*
* NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER
*
* This command requests physical RM to service the access counter buffer.
* accessCounterIndex
* Index of access counter buffer to unregister.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */
#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE
*
* This command retrieves the access counter buffer size from physical RM.
*
* bufferSize[OUT]
* Size of the access counter buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU)
#define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS {
NvU32 bufferSize;
} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS {
NvU32 accessCounterIndex;
} NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
@@ -1362,7 +1347,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS {
NvU32 replayableFaultBufferSize;
NvU32 replayableShadowFaultBufferMetadataSize;
NvU32 nonReplayableFaultBufferSize;
NvU32 nonReplayableShadowFaultBufferMetadataSize;
} NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS;
/*!
@@ -1848,12 +1835,13 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 1500
#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000
#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU)
typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8);
NvU32 shadowFaultBufferSize;
NvU32 shadowFaultBufferMetadataSize;
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8);
NvU32 shadowFaultBufferType;
NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8);
@@ -2288,6 +2276,25 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS {
NvU8 hshubId;
} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG
*
* Program HSHUB for EGM peer id.
*
* egmPeerId[IN]
* EGM peer id to program in the HSHUB registers.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU)
typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS {
NvU32 egmPeerId;
} NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS;
/*
@@ -2880,6 +2887,8 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
* Handle to SYSMEM memlist object
* [in] gspFbAllocsSysOffset
* Offset in SYSMEM for GSP's FB Allocations
* [in] bEnteringGcoffState
* Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING
*
* Possible status values returned are:
* NV_OK
@@ -2897,6 +2906,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
NvHandle hClient;
NvHandle hSysMem;
NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
NvBool bEnteringGcoffState;
} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
/*!
@@ -3211,6 +3221,8 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS
*
* bEnable [IN]
* Enable or Reset the settings
* clientLimit [IN]
* Client requested limit
*
* Possible status values returned are:
* NV_OK
@@ -3225,6 +3237,7 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS
typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS {
NvBool bEnable;
NvU32 clientLimit;
} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS;
/*!
@@ -3467,4 +3480,335 @@ typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS {
NvBool gpioDirection; // out
} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS;
/* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA
*
* This command sets up ACPI DDC Edid data.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */
/* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */
#define MAX_EDID_SIZE_FROM_SBIOS 512U
typedef struct NV2080_CTRL_INTERNAL_EDID_DATA {
NvU32 status;
NvU32 acpiId;
NvU32 bufferSize;
NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS];
} NV2080_CTRL_INTERNAL_EDID_DATA;
#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU)
typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS {
NvU32 tableLen;
NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED
*
* This command intializes display ACPI child devices.
* This command accepts no parameters.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */
/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */
/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
*
* This structure provides the params for getting GPU Fabric Probe Internal
* Info from GSP to CPU RM
*
* numProbes[OUT]
* - Number of probe requests sent
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U)
typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 numProbes, 8);
} NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO
*
* This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS
* from GSP to CPU RM.
* This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
*
* This structure provides the params for starting GPU Fabric Probe
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*/
#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE
*
* This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE
*
* This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts no parameters
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE
*
* This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts no parameters
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */
/*!
* NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
*
* This structure provides the params for resuming GPU Fabric Probe
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*/
#define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U)
typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
} NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE
*
* This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE
*
* This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP.
* This command accepts no parameters
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO
*
* This command is an internal command sent from Kernel RM to Physical RM
* to get static conf compute info
*
* bIsBar1Trusted: [OUT]
* Is BAR1 trusted to access CPR
* bIsPcieTrusted: [OUT]
* Is PCIE trusted to access CPR
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
NvBool bIsBar1Trusted;
NvBool bIsPcieTrusted;
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
*
* This command is used by CPU-RM to perform memory operations using GSP
*
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_TIMEOUT_RETRY
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP {
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0,
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1,
} NV2080_CTRL_MEMMGR_MEMORY_OP;
typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO {
/*!
* Base physical address of the surface
*/
NV_DECLARE_ALIGNED(NvU64 baseAddr, 8);
/*!
* Size of the surface in bytes
*/
NV_DECLARE_ALIGNED(NvU64 size, 8);
/*!
* Offset in bytes into the surface where read/write must happen
*/
NV_DECLARE_ALIGNED(NvU64 offset, 8);
/*!
* Aperture where the surface is allocated
*/
NvU32 aperture;
/*!
* CPU caching attribute of the surface
*/
NvU32 cpuCacheAttrib;
} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO;
#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU)
typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS {
/*!
* Source surface info
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8);
/*!
* Destination surface info
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8);
/*!
* Size of the data to be transferred
*/
NV_DECLARE_ALIGNED(NvU64 transferSize, 8);
/*!
* To be set in case of memset
*/
NvU32 value;
/*!
* Memory op to be performed
*/
NV2080_CTRL_MEMMGR_MEMORY_OP memop;
} NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG
*
* This command is an internal command sent from Kernel RM to Physical RM
* to get local GPU's ATS config
*
* addrSysPhys : [OUT]
* System Physical Address
* addrWidth : [OUT]
* Address width value
* mask : [OUT]
* Mask value
* maskWidth : [OUT]
* Mask width value
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU)
typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS {
NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8);
NvU32 addrWidth;
NvU32 mask;
NvU32 maskWidth;
} NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG
*
* This command is an internal command sent from Kernel RM to Physical RM
* to set peer ATS config using the parameters passed in.
*
* peerId : [IN]
* Peer Id of the peer for which ATS config is to be programmed
* addrSysPhys : [IN]
* System Physical Address
* addrWidth : [IN]
* Address width value
* mask : [IN]
* Mask value
* maskWidth : [IN]
* Mask width value
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU)
typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS {
NvU32 peerId;
NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8);
NvU32 addrWidth;
NvU32 mask;
NvU32 maskWidth;
} NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO
*
* Get GPU EDPpeak Limit information
*
* limitMin [OUT]
* Minimum allowed limit value on EDPp policy on both AC and DC
* limitRated [OUT]
* Rated/default allowed limit value on EDPp policy on AC
* limitMax [OUT]
* Maximum allowed limit value on EDPp policy on AC
* limitCurr [OUT]
* Current resultant limit effective on EDPp policy on AC and DC
* limitBattRated [OUT]
* Default/rated allowed limit on EDPp policy on DC
* limitBattMax [OUT]
* Maximum allowed limit on EDPp policy on DC
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU)
typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS {
NvU32 limitMin;
NvU32 limitRated;
NvU32 limitMax;
NvU32 limitCurr;
NvU32 limitBattRated;
NvU32 limitBattMax;
} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS;
/* ctrl2080internal_h */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
//

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080mc.finn
// Source file: ctrl/ctrl2080/ctrl2080mc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -79,7 +79,6 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170)
/* valid ARCHITECTURE_T23X implementation values */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

20
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn
// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -2097,6 +2097,7 @@ typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerId;
NvU32 peerLinkMask;
NvBool bEgmPeer;
NvBool bNvswitchConn;
} NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
@@ -2972,5 +2973,22 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG
*
* This command is to check if a GPU has a reduced nvlink configuration
*
* [out] bReducedNvlinkConfig
* Link number which the sequence should be triggered
*/
#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x44U)
typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
NvBool bReducedNvlinkConfig;
} NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

4
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf.finn
// Source file: ctrl/ctrl2080/ctrl2080perf.finn
//
#include "nvfixedtypes.h"
@@ -460,7 +460,7 @@ typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMP
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72
#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \
NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \
sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \
NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL
/*!

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn
// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
//

41
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmu.finn
//
#include "nvtypes.h"
/*!
* @file
*
* @brief Enumeration of all PMU RMCTRL identifiers.
*/

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn
// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn
//

93
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h
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@@ -27,6 +27,97 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080power.finn
// Source file: ctrl/ctrl2080/ctrl2080power.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*!
* @brief GC6 flavor ids
*/
typedef enum NV2080_CTRL_GC6_FLAVOR_ID {
NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0,
NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1,
NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4,
} NV2080_CTRL_GC6_FLAVOR_ID;
/*
* NV2080_CTRL_CMD_GC6_ENTRY
*
* This command executes the steps of GC6 entry sequence
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED (non-fatal)
* NV_ERR_INVALID_STATE (non-fatal)
* NV_ERR_INVALID_ARGUMENT (non-fatal)
* NV_ERR_NOT_READY (non-fatal)
* NV_ERR_TIMEOUT
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GC6_ENTRY (0x2080270d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_GC6_ENTRY_PARAMS {
NV2080_CTRL_GC6_FLAVOR_ID flavorId;
NvU32 stepMask;
struct {
NvBool bIsRTD3Transition;
NvBool bIsRTD3CoreRailPowerCut;
NvBool bSkipPstateSanity;
} params;
} NV2080_CTRL_GC6_ENTRY_PARAMS;
/*
* NV2080_CTRL_CMD_GC6_EXIT
*
* This command executes the steps of GC6 exit sequence
*
* Possible status return values are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GC6_EXIT (0x2080270e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_GC6_EXIT_PARAMS {
NV2080_CTRL_GC6_FLAVOR_ID flavorId;
struct {
NvBool bIsGpuSelfWake;
NvBool bIsRTD3Transition;
NvBool bIsRTD3HotTransition; //output
} params;
} NV2080_CTRL_GC6_EXIT_PARAMS;
/*!
* @brief GC6 step ids
*/
typedef enum NV2080_CTRL_GC6_STEP_ID {
NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0,
NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1,
NV2080_CTRL_GC6_STEP_ID_MAX = 2,
} NV2080_CTRL_GC6_STEP_ID;
typedef struct NV2080_CTRL_GC6_FLAVOR_INFO {
NV2080_CTRL_GC6_FLAVOR_ID flavorId;
NvU32 stepMask;
} NV2080_CTRL_GC6_FLAVOR_INFO;
/* _ctrl2080power_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080rc.finn
// Source file: ctrl/ctrl2080/ctrl2080rc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

255
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h Normal file
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@@ -0,0 +1,255 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080spdm.finn
//
/*************************** SPDM COMMANDS ************************************/
/*!
* @brief SPDM Command Types
*
*/
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define RSVD7_SIZE 16
#define RSVD8_SIZE 2
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_INIT to GSP-RM before SPDM session start
*/
typedef struct RM_GSP_SPDM_CC_INIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU8 dmaIdx; // To indicate DMA engine which DMA idx is needed
NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
NvU32 addrSpace; // The memory type allocated by RM (SYS or FB ...)
NvU32 regionId; // If memory is in WPR, this is a WPR id.
NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
} RM_GSP_SPDM_CC_INIT_CTX;
typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX;
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_INIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_INIT_CTX ccInitCtx;
} RM_GSP_SPDM_CMD_CC_INIT;
typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT;
#define DEINIT_FLAGS_FORCE_CLEAR (0x1)
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_DEINIT to GSP-RM to end a session
*/
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
NvU32 flags;
} RM_GSP_SPDM_CC_DEINIT_CTX;
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX *PRM_GSP_SPDM_CC_DEINIT_CTX;
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_DEINIT_CTX ccDeinitCtx;
} RM_GSP_SPDM_CMD_CC_DEINIT;
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT;
/*!
* RM provides SPDM message request context, include header + corresponding payload
*/
typedef struct RM_GSP_SPDM_CC_CTRL_CTX {
NvU32 version;
NvU32 guestId; // To indicate CC client Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
NvU32 ctrlCode; // control code
NvU32 ctrlParam; // Associated with ctrlCode
} RM_GSP_SPDM_CC_CTRL_CTX;
typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX;
/*!
* RM provides the SPDM request info to GSP
*/
typedef struct RM_GSP_SPDM_CMD_CC_CTRL {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_CTRL_CTX ccCtrlCtx;
} RM_GSP_SPDM_CMD_CC_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA {
// Command must be first as this struct is the part of union
NvU8 cmdType;
NvU32 rsvd0[2];
NvU32 rsvd1;
char rsvd2[4];
char rsvd3[2];
char rsvd4[5];
char rsvd5[5];
char rsvd6[2];
char rsvd7[RSVD7_SIZE];
NvU32 rsvd8[RSVD8_SIZE];
} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
* other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior
* when paired with alignment directives on Linux and Windows.
*/
/*!
* A union of all SPDM Commands.
*/
typedef union RM_GSP_SPDM_CMD {
NvU8 cmdType;
RM_GSP_SPDM_CMD_CC_INIT ccInit;
RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit;
RM_GSP_SPDM_CMD_CC_CTRL ccCtrl;
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
} RM_GSP_SPDM_CMD;
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
/***************************** SPDM MESSAGES *********************************/
/*!
* SPDM Message Status
*/
/*!
* Returns the status for program CE keys to RM
*/
#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
/*!
* Returns the Error Status for Invalid Command
*/
#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF)
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
* other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior
* when paired with alignment directives on Linux and Windows.
*/
/*!
* SPDM message structure.
*/
typedef struct RM_GSP_SPDM_MSG {
NvU8 msgType;
NvU32 version;
NvU32 guestId;
NvU32 endpointId;
// status returned from GSP message infrastructure.
NvU32 status;
NvU32 rsvd1;
NvU32 rsvd2;
NvU32 rsvd3;
NvU32 rsvd4;
} RM_GSP_SPDM_MSG;
typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;
/*
* NV2080_CTRL_CMD_INTERNAL_SPDM_PARTITION
*
* This command does a partition switch to SPDM partition
*
*/
#define NV2080_CTRL_INTERNAL_SPDM_PARTITION (0x20800ad9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID (0xD9U)
typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS {
NvU8 index;
RM_GSP_SPDM_CMD cmd;
RM_GSP_SPDM_MSG msg;
} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h
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@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080spi.finn
// Source file: ctrl/ctrl2080/ctrl2080spi.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h
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@@ -25,6 +25,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
//

59
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080tmr.finn
// Source file: ctrl/ctrl2080/ctrl2080tmr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -151,16 +151,32 @@ typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE {
* for a given CPU clock type.
*
* cpuClkId
* This parameter specifies the source of the CPU clock. Legal values for
* this parameter include:
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME
* This clock id will provide real time in microseconds since
* 00:00:00 UTC on January 1, 1970.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API
* This clock id will provide time stamp that is constant-rate, high
* precision using platform API that is also available in the user mode.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC
* This clock id will provide time stamp using CPU's time stamp counter.
* This parameter specifies the source of the CPU clock. This parameter is
* composed of two fields:
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE
* This field specifies source ID of the CPU clock in question. Legal
* values for this parameter include:
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME
* This clock id will provide real time in microseconds since
* 00:00:00 UTC on January 1, 1970, as reported by the host OS.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API
* This clock id will provide time stamp that is constant-rate, high
* precision using platform API that is also available in the user
* mode.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC
* This clock id will provide time stamp using CPU's time stamp
* counter.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR
* This field specifies the processor whose clock should be used for the
* source. The control call and cpuClkId parameter remain named for the
* CPU specifically for legacy reasons. Not all processors will support
* all clock sources. Legal values for this parameter include:
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU
* The clock information will be fulfilled by the CPU. This value
* is defined to be 0 so that it is the default for backwards
* compatibility.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP
* The clock information will be fulfilled by the GSP.
*
* sampleCount
* This field specifies the number of clock samples to be taken.
@@ -188,10 +204,21 @@ typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8);
} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS;
/* Legal cpuClkId values */
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE 3:0
/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE values */
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS (0x00000004)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR 7:4
/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR values */
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU (0x00000000)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP (0x00000001)
/*!
* NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ
*
@@ -219,7 +246,7 @@ typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS {
* NV_ERR_INVALID_OPERATION
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */
/*!
* This struct contains bSetMaxFreq flag.

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
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@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn
// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080unix.finn
// Source file: ctrl/ctrl2080/ctrl2080unix.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080vfe.finn
// Source file: ctrl/ctrl2080/ctrl2080vfe.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn
// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080volt.finn
// Source file: ctrl/ctrl2080/ctrl2080volt.finn
//