535.43.02

2026-03-07 14:19:50 +00:00 · 2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
--- a/src/nvidia/generated/g_gpu_nvoc.h
+++ b/src/nvidia/generated/g_gpu_nvoc.h
@@ -7,7 +7,7 @@ extern "C" {
 #endif

 /*
- * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -73,6 +73,7 @@ typedef struct GPUATTACHARG GPUATTACHARG;
 #include "gpu/gpu_timeout.h"
 #include "gpu/gpu_access.h"
 #include "gpu/gpu_shared_data_map.h"
+#include "gpu/kern_gpu_power.h"

 #include "platform/acpi_common.h"
 #include "gpu/gpu_acpi_data.h"
@@ -299,7 +300,7 @@ typedef enum
    COMPUTE_BRANDING_TYPE_TESLA,
 } COMPUTE_BRANDING_TYPE;

-#define OOR_ARCH_DEF(x) \
+#define OOR_ARCH_DEF(x)                            \
    NV_ENUM_ENTRY(x, OOR_ARCH_X86_64,  0x00000000) \
    NV_ENUM_ENTRY(x, OOR_ARCH_PPC64LE, 0x00000001) \
    NV_ENUM_ENTRY(x, OOR_ARCH_ARM,     0x00000002) \
@@ -318,8 +319,61 @@ typedef struct
 {
    NvU32 classId;
    NvU32 instances;
+
+    /*!
+     * Pointer to the @ref NVOC_CLASS_INFO for the concrete class to instantiate
+     * for this child.
+     */
+    const NVOC_CLASS_INFO *pClassInfo;
 } GPUCHILDPRESENT;

+/*!
+ * @brief   Generates an entry for a list of @ref GPUCHILDPRESENT objects for a
+ *          class of the given name
+ *
+ * @param[in]   _childClassName
+ *  Name of the class for the entry
+ * @param[in]   _instances
+ *  Number of instances of the child that may be present; see
+ *  @ref GPUCHILDPRESENT::instances
+ *
+ * @return  An entry suitable for a list of @ref GPUCHILDPRESENT for the given
+ *          child of @ref OBJGPU
+ */
+#define GPU_CHILD_PRESENT(_childClassName, _instances) \
+    GPU_CHILD_PRESENT_POLYMORPHIC(_childClassName, (_instances), _childClassName)
+
+/*!
+ * @brief   Generates an entry for a list of @ref GPUCHILDPRESENT objects that
+ *          allows the @ref OBJGPU child to instantiate a sub-class of the base
+ *          @ref OBJGPU child class.
+ *
+ * @details The intention of this macro is to allow a list of
+ *          @ref GPUCHILDPRESENT to essentially state "this child should be
+ *          present with this concrete class type". This allows for different
+ *          @ref GPUCHILDPRESENT lists to request different classes with
+ *          different behavior via sub-classes, for the same basic @ref OBJGPU
+ *          child.
+ *
+ * @param[in]   _childClassName
+ *  Name of the base class at which @ref OBJGPU points
+ * @param[in]   _instances
+ *  Number of instances of the child that may be present; see
+ *  @ref GPUCHILDPRESENT::instances
+ * @param[in]   _concreteClassName
+ *   Name of the sub-class of _childClassName that should actually be
+ *   instantiated
+ *
+ * @return  An entry suitable for a list of @ref GPUCHILDPRESENT for the given
+ *          child of @ref OBJGPU with the given concrete class type.
+ */
+#define GPU_CHILD_PRESENT_POLYMORPHIC(_childClassName, _instances, _concreteClassName) \
+    { \
+        .classId = classId(_childClassName), \
+        .instances = (_instances), \
+        .pClassInfo = classInfo(_concreteClassName) \
+    }
+
 // GPU Child Order Flags
 #define GCO_LIST_INIT            NVBIT(0)    // entry is used for init ordering (DO NOT USE)
 #define GCO_LIST_LOAD            NVBIT(1)    // entry is used for load and postload ordering (DO NOT USE)
@@ -490,16 +544,6 @@ typedef struct
    NvU32                 PCIRevisionID;
    NvU32                 Subrevision;

-    //
-    // ImplentationExternal and ArchitectureExternal are only valid if they are
-    // not both zero.  They are used when we want to report a different
-    // arch/imp to an external client.  For example, MCP73 is almost the same
-    // as MCP67, so we report the MCP67 arch/imp to external clients of MCP73.
-    // (If an MCP73 client really needs to know that it is running on MCP73
-    // instead of MCP67, it should check capability bits.)
-    //
-    NvU32                 ImplementationExternal;
-    NvU32                 ArchitectureExternal;
 } GPUIDINFO;


@@ -509,7 +553,6 @@ typedef struct
    NvU32                 arch;
    NvU32                 majorRev;
    NvU32                 minorRev;
-    NvU32                 devIDStrap;
    NvU32                 minorExtRev;
 } PMCBOOT0;

@@ -519,7 +562,6 @@ typedef struct
    NvU32                 arch;
    NvU32                 majorRev;
    NvU32                 minorRev;
-    NvU32                 devIDStrap;
    NvU32                 minorExtRev;
 } PMCBOOT42;

@@ -740,6 +782,7 @@ typedef struct
    PSRIOV_P2P_INFO pP2PInfo;
    NvBool          bP2PAllocated;
    NvU32           maxP2pGfid;
+    NvU32           p2pFabricPartitionId;
 } _GPU_SRIOV_STATE;

 // Max # of instances for GPU children
@@ -844,11 +887,16 @@ struct OBJGPU {
    NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *);
    void (*__gpuReadDeviceId__)(struct OBJGPU *, NvU32 *, NvU32 *);
    NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool);
+    void (*__gpuDetermineSelfHostedMode__)(struct OBJGPU *);
+    void (*__gpuDetermineMIGSupport__)(struct OBJGPU *);
    NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *);
    NvBool (*__gpuIsSliCapableWithoutDisplay__)(struct OBJGPU *);
+    NvBool (*__gpuIsCCEnabledInHw__)(struct OBJGPU *);
+    NvBool (*__gpuIsDevModeEnabledInHw__)(struct OBJGPU *);
+    NvBool (*__gpuIsCtxBufAllocInPmaSupported__)(struct OBJGPU *);
    NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED;
    NvBool bVideoLinkDisabled;
-    GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo;
+    GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel;
    NvU32 moduleId;
    NvU8 nvswitchSupport;
    NvBool PDB_PROP_GPU_IN_STANDBY;
@@ -906,10 +954,13 @@ struct OBJGPU {
    NvBool PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH;
    NvBool PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL;
    NvBool PDB_PROP_GPU_IS_MOBILE;
+    NvBool PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC;
    NvBool PDB_PROP_GPU_RTD3_GC6_SUPPORTED;
    NvBool PDB_PROP_GPU_RTD3_GC6_ACTIVE;
    NvBool PDB_PROP_GPU_FAST_GC6_ACTIVE;
    NvBool PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED;
+    NvBool PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA;
+    NvBool PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED;
    NvBool PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED;
    NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERING;
    NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERED;
@@ -926,7 +977,6 @@ struct OBJGPU {
    NvBool PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS;
    NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU;
    NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA;
-    NvBool PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA;
    NvBool PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED;
    NvBool PDB_PROP_GPU_NV_USERMODE_ENABLED;
    NvBool PDB_PROP_GPU_IN_FATAL_ERROR;
@@ -935,6 +985,13 @@ struct OBJGPU {
    NvBool PDB_PROP_GPU_IS_MXM_3X;
    NvBool PDB_PROP_GPU_GSYNC_III_ATTACHED;
    NvBool PDB_PROP_GPU_QSYNC_II_ATTACHED;
+    NvBool PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322;
+    NvBool PDB_PROP_GPU_CC_FEATURE_CAPABLE;
+    NvBool PDB_PROP_GPU_APM_FEATURE_CAPABLE;
+    NvBool PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX;
+    NvBool PDB_PROP_GPU_SKIP_TABLE_CE_MAP;
+    NvBool PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF;
+    NvBool PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL;
    OS_GPU_INFO *pOsGpuInfo;
    OS_RM_CAPS *pOsRmCaps;
    NvU32 halImpl;
@@ -949,6 +1006,7 @@ struct OBJGPU {
    NvU32 subdeviceInstance;
    NvS32 numaNodeId;
    _GPU_UUID gpuUuid;
+    NvBool gspRmInitialized;
    _GPU_PCIE_PEER_CLIQUE pciePeerClique;
    NvU32 i2cPortForExtdev;
    GPUIDINFO idInfo;
@@ -1015,6 +1073,7 @@ struct OBJGPU {
    struct OBJGPUMON *pGpuMon;
    struct OBJSWENG *pSwEng;
    struct KernelFsp *pKernelFsp;
+    struct ConfidentialCompute *pConfCompute;
    struct KernelCcu *pKernelCcu;
    HWBC_LIST *pHWBCList;
    GPUCLDATA gpuClData;
@@ -1075,6 +1134,7 @@ struct OBJGPU {
    NvBool bIsVirtualWithSriov;
    NvU32 P2PPeerGpuCount;
    GPU_P2P_PEER_GPU_CAPS P2PPeerGpuCaps[32];
+    NvBool bIsSelfHosted;
    NvBool bStateLoading;
    NvBool bStateUnloading;
    NvBool bStateLoaded;
@@ -1113,6 +1173,7 @@ struct OBJGPU {
    NvBool bIsNvidiaNvs;
    NvBool bIsTitan;
    NvBool bIsTesla;
+    NvBool bIsAC;
    BRANDING_TYPE brandingCache;
    NvBool bComputePolicyTimesliceSupported;
    NvBool bGlobalPoisonFuseEnabled;
@@ -1125,6 +1186,7 @@ struct OBJGPU {
    NvBool bRecheckSliSupportAtResume;
    _GPU_SLI_PEER peer[2];
    NvBool bIsGspOwnedFaultBuffersEnabled;
+    _GPU_GC6_STATE gc6State;
 };

 #ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__
@@ -1154,6 +1216,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
 #define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GC6_SUPPORTED
 #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_CAST
 #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU
+#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST
+#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K
 #define PDB_PROP_GPU_INACCESSIBLE_BASE_CAST
 #define PDB_PROP_GPU_INACCESSIBLE_BASE_NAME PDB_PROP_GPU_INACCESSIBLE
 #define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_CAST
@@ -1194,12 +1258,18 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
 #define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED
 #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_CAST
 #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE
+#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_CAST
+#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_NAME PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC
 #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_CAST
 #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_NAME PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED
 #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_CAST
 #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_NAME PDB_PROP_GPU_RM_UNLINKED_SLI
+#define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_CAST
+#define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_NAME PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL
 #define PDB_PROP_GPU_IS_UEFI_BASE_CAST
 #define PDB_PROP_GPU_IS_UEFI_BASE_NAME PDB_PROP_GPU_IS_UEFI
+#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST
+#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP
 #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_CAST
 #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_NAME PDB_PROP_GPU_IN_SECONDARY_BUS_RESET
 #define PDB_PROP_GPU_OPTIMIZE_SPARSE_TEXTURE_BY_DEFAULT_BASE_CAST
@@ -1214,6 +1284,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
 #define PDB_PROP_GPU_IS_MOBILE_BASE_NAME PDB_PROP_GPU_IS_MOBILE
 #define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_CAST
 #define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_RTD3_GC6_ACTIVE
+#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_CAST
+#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_CC_FEATURE_CAPABLE
 #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_CAST
 #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_ENABLED
 #define PDB_PROP_GPU_PERSISTENT_SW_STATE_BASE_CAST
@@ -1274,12 +1346,16 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
 #define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X
 #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_CAST
 #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS
+#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_CAST
+#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_NAME PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322
 #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_CAST
 #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_NAME PDB_PROP_GPU_GSYNC_III_ATTACHED
 #define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_CAST
 #define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_NAME PDB_PROP_GPU_QSYNC_II_ATTACHED
 #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_CAST
 #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR04_PRESENT
+#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_CAST
+#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_NAME PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF
 #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_CAST
 #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE
 #define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_CAST
@@ -1302,6 +1378,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
 #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED
 #define PDB_PROP_GPU_EMULATION_BASE_CAST
 #define PDB_PROP_GPU_EMULATION_BASE_NAME PDB_PROP_GPU_EMULATION
+#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_CAST
+#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_APM_FEATURE_CAPABLE
 #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_CAST
 #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_NAME PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS
 #define PDB_PROP_GPU_PRIMARY_DEVICE_BASE_CAST
@@ -1316,8 +1394,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
 #define PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST_BASE_NAME PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST
 #define PDB_PROP_GPU_IS_LOST_BASE_CAST
 #define PDB_PROP_GPU_IS_LOST_BASE_NAME PDB_PROP_GPU_IS_LOST
-#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST
-#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K
+#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_CAST
+#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED
+#define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_CAST
+#define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_NAME PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX

 NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU**, Dynamic*, NvU32, va_list);

@@ -1362,10 +1442,20 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32,
 #define gpuReadDeviceId_HAL(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1)
 #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization)
 #define gpuGetFlaVasSize_HAL(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization)
+#define gpuDetermineSelfHostedMode(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu)
+#define gpuDetermineSelfHostedMode_HAL(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu)
+#define gpuDetermineMIGSupport(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu)
+#define gpuDetermineMIGSupport_HAL(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu)
 #define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu)
 #define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu)
 #define gpuIsSliCapableWithoutDisplay(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu)
 #define gpuIsSliCapableWithoutDisplay_HAL(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu)
+#define gpuIsCCEnabledInHw(pGpu) gpuIsCCEnabledInHw_DISPATCH(pGpu)
+#define gpuIsCCEnabledInHw_HAL(pGpu) gpuIsCCEnabledInHw_DISPATCH(pGpu)
+#define gpuIsDevModeEnabledInHw(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu)
+#define gpuIsDevModeEnabledInHw_HAL(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu)
+#define gpuIsCtxBufAllocInPmaSupported(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu)
+#define gpuIsCtxBufAllocInPmaSupported_HAL(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu)
 static inline NV_STATUS gpuConstructPhysical_56cd7a(struct OBJGPU *pGpu) {
    return NV_OK;
 }
@@ -1591,6 +1681,22 @@ static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical(struct OBJGPU *

 #define gpuPowerManagementResumePostLoadPhysical_HAL(pGpu) gpuPowerManagementResumePostLoadPhysical(pGpu)

+static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx_46f6a7(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) {
+    return NV_ERR_NOT_SUPPORTED;
+}
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx_46f6a7(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuInitializeMemDescFromPromotedCtx_HAL(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin)
+
 NV_STATUS gpuGetNameString_KERNEL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1);

 NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1);
@@ -1828,7 +1934,23 @@ static inline RmPhysAddr gpuGetDmaEndAddress(struct OBJGPU *pGpu) {

 #define gpuGetDmaEndAddress_HAL(pGpu) gpuGetDmaEndAddress(pGpu)

-static inline NV_STATUS gpuMarkDeviceForReset_46f6a7(struct OBJGPU *pGpu) {
+static inline NV_STATUS gpuSetStateResetRequired_395e98(struct OBJGPU *pGpu, NvU32 exceptType) {
+    return NV_ERR_NOT_SUPPORTED;
+}
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuSetStateResetRequired(struct OBJGPU *pGpu, NvU32 exceptType) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuSetStateResetRequired(pGpu, exceptType) gpuSetStateResetRequired_395e98(pGpu, exceptType)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuSetStateResetRequired_HAL(pGpu, exceptType) gpuSetStateResetRequired(pGpu, exceptType)
+
+static inline NV_STATUS gpuMarkDeviceForReset_395e98(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }

@@ -1839,12 +1961,12 @@ static inline NV_STATUS gpuMarkDeviceForReset(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }
 #else //__nvoc_gpu_h_disabled
-#define gpuMarkDeviceForReset(pGpu) gpuMarkDeviceForReset_46f6a7(pGpu)
+#define gpuMarkDeviceForReset(pGpu) gpuMarkDeviceForReset_395e98(pGpu)
 #endif //__nvoc_gpu_h_disabled

 #define gpuMarkDeviceForReset_HAL(pGpu) gpuMarkDeviceForReset(pGpu)

-static inline NV_STATUS gpuUnmarkDeviceForReset_46f6a7(struct OBJGPU *pGpu) {
+static inline NV_STATUS gpuUnmarkDeviceForReset_395e98(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }

@@ -1855,13 +1977,17 @@ static inline NV_STATUS gpuUnmarkDeviceForReset(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }
 #else //__nvoc_gpu_h_disabled
-#define gpuUnmarkDeviceForReset(pGpu) gpuUnmarkDeviceForReset_46f6a7(pGpu)
+#define gpuUnmarkDeviceForReset(pGpu) gpuUnmarkDeviceForReset_395e98(pGpu)
 #endif //__nvoc_gpu_h_disabled

 #define gpuUnmarkDeviceForReset_HAL(pGpu) gpuUnmarkDeviceForReset(pGpu)

-static inline NV_STATUS gpuIsDeviceMarkedForReset_46f6a7(struct OBJGPU *pGpu, NvBool *pbResetRequired) {
-    return NV_ERR_NOT_SUPPORTED;
+static inline NV_STATUS gpuIsDeviceMarkedForReset_82f166(struct OBJGPU *pGpu, NvBool *pbResetRequired) {
+    *pbResetRequired = ((NvBool)(0 != 0));
+    {
+        return NV_ERR_NOT_SUPPORTED;
+    }
+    ;
 }


@@ -1871,12 +1997,12 @@ static inline NV_STATUS gpuIsDeviceMarkedForReset(struct OBJGPU *pGpu, NvBool *p
    return NV_ERR_NOT_SUPPORTED;
 }
 #else //__nvoc_gpu_h_disabled
-#define gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset_46f6a7(pGpu, pbResetRequired)
+#define gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset_82f166(pGpu, pbResetRequired)
 #endif //__nvoc_gpu_h_disabled

 #define gpuIsDeviceMarkedForReset_HAL(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset(pGpu, pbResetRequired)

-static inline NV_STATUS gpuMarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu) {
+static inline NV_STATUS gpuMarkDeviceForDrainAndReset_395e98(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }

@@ -1887,12 +2013,12 @@ static inline NV_STATUS gpuMarkDeviceForDrainAndReset(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }
 #else //__nvoc_gpu_h_disabled
-#define gpuMarkDeviceForDrainAndReset(pGpu) gpuMarkDeviceForDrainAndReset_46f6a7(pGpu)
+#define gpuMarkDeviceForDrainAndReset(pGpu) gpuMarkDeviceForDrainAndReset_395e98(pGpu)
 #endif //__nvoc_gpu_h_disabled

 #define gpuMarkDeviceForDrainAndReset_HAL(pGpu) gpuMarkDeviceForDrainAndReset(pGpu)

-static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu) {
+static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset_395e98(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }

@@ -1903,13 +2029,17 @@ static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset(struct OBJGPU *pGpu) {
    return NV_ERR_NOT_SUPPORTED;
 }
 #else //__nvoc_gpu_h_disabled
-#define gpuUnmarkDeviceForDrainAndReset(pGpu) gpuUnmarkDeviceForDrainAndReset_46f6a7(pGpu)
+#define gpuUnmarkDeviceForDrainAndReset(pGpu) gpuUnmarkDeviceForDrainAndReset_395e98(pGpu)
 #endif //__nvoc_gpu_h_disabled

 #define gpuUnmarkDeviceForDrainAndReset_HAL(pGpu) gpuUnmarkDeviceForDrainAndReset(pGpu)

-static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset_46f6a7(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) {
-    return NV_ERR_NOT_SUPPORTED;
+static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset_244f65(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) {
+    *pbDrainRecommended = ((NvBool)(0 != 0));
+    {
+        return NV_ERR_NOT_SUPPORTED;
+    }
+    ;
 }


@@ -1919,7 +2049,7 @@ static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset(struct OBJGPU *pGpu, N
    return NV_ERR_NOT_SUPPORTED;
 }
 #else //__nvoc_gpu_h_disabled
-#define gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset_46f6a7(pGpu, pbDrainRecommended)
+#define gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset_244f65(pGpu, pbDrainRecommended)
 #endif //__nvoc_gpu_h_disabled

 #define gpuIsDeviceMarkedForDrainAndReset_HAL(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended)
@@ -1971,6 +2101,20 @@ static inline void gpuDestroyOverrides(struct OBJGPU *pGpu) {

 #define gpuDestroyOverrides_HAL(pGpu) gpuDestroyOverrides(pGpu)

+NV_STATUS gpuPowerOff_KERNEL(struct OBJGPU *pGpu);
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuPowerOff(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuPowerOff(pGpu) gpuPowerOff_KERNEL(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuPowerOff_HAL(pGpu) gpuPowerOff(pGpu)
+
 NV_STATUS gpuSetPower_GM107(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, NvU32 arg3);


@@ -2287,6 +2431,40 @@ static inline NV_STATUS gpuJtVersionSanityCheck(struct OBJGPU *pGpu) {

 #define gpuJtVersionSanityCheck_HAL(pGpu) gpuJtVersionSanityCheck(pGpu)

+static inline NvBool gpuCompletedGC6PowerOff_cbe027(struct OBJGPU *pGpu) {
+    return ((NvBool)(0 == 0));
+}
+
+NvBool gpuCompletedGC6PowerOff_GV100(struct OBJGPU *pGpu);
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NvBool gpuCompletedGC6PowerOff(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_FALSE;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuCompletedGC6PowerOff(pGpu) gpuCompletedGC6PowerOff_cbe027(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuCompletedGC6PowerOff_HAL(pGpu) gpuCompletedGC6PowerOff(pGpu)
+
+static inline NvBool gpuIsACPIPatchRequiredForBug2473619_491d52(struct OBJGPU *pGpu) {
+    return ((NvBool)(0 != 0));
+}
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NvBool gpuIsACPIPatchRequiredForBug2473619(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_FALSE;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuIsACPIPatchRequiredForBug2473619(pGpu) gpuIsACPIPatchRequiredForBug2473619_491d52(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuIsACPIPatchRequiredForBug2473619_HAL(pGpu) gpuIsACPIPatchRequiredForBug2473619(pGpu)
+
 NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu);

 NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu);
@@ -2448,6 +2626,58 @@ static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_I

 #define gpuDecodeDeviceInfoTableGroupId_HAL(pGpu, pEntry, pDeviceAccum) gpuDecodeDeviceInfoTableGroupId(pGpu, pEntry, pDeviceAccum)

+static inline NV_STATUS gpuGc6EntryPstateCheck_56cd7a(struct OBJGPU *pGpu) {
+    return NV_OK;
+}
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuGc6EntryPstateCheck(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuGc6EntryPstateCheck(pGpu) gpuGc6EntryPstateCheck_56cd7a(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuGc6EntryPstateCheck_HAL(pGpu) gpuGc6EntryPstateCheck(pGpu)
+
+static inline NV_STATUS gpuWaitGC6Ready_56cd7a(struct OBJGPU *pGpu) {
+    return NV_OK;
+}
+
+NV_STATUS gpuWaitGC6Ready_GM107(struct OBJGPU *pGpu);
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuWaitGC6Ready(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuWaitGC6Ready(pGpu) gpuWaitGC6Ready_56cd7a(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuWaitGC6Ready_HAL(pGpu) gpuWaitGC6Ready(pGpu)
+
+static inline NV_STATUS gpuPrePowerOff_56cd7a(struct OBJGPU *pGpu) {
+    return NV_OK;
+}
+
+NV_STATUS gpuPrePowerOff_GM107(struct OBJGPU *pGpu);
+
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuPrePowerOff(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuPrePowerOff(pGpu) gpuPrePowerOff_56cd7a(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+#define gpuPrePowerOff_HAL(pGpu) gpuPrePowerOff(pGpu)
+
 NV_STATUS gpuVerifyExistence_IMPL(struct OBJGPU *pGpu);


@@ -2851,6 +3081,28 @@ static inline NvU64 gpuGetFlaVasSize_DISPATCH(struct OBJGPU *pGpu, NvBool bNvswi
    return pGpu->__gpuGetFlaVasSize__(pGpu, bNvswitchVirtualization);
 }

+void gpuDetermineSelfHostedMode_PHYSICAL_GH100(struct OBJGPU *pGpu);
+
+static inline void gpuDetermineSelfHostedMode_b3696a(struct OBJGPU *pGpu) {
+    return;
+}
+
+void gpuDetermineSelfHostedMode_KERNEL_GH100(struct OBJGPU *pGpu);
+
+static inline void gpuDetermineSelfHostedMode_DISPATCH(struct OBJGPU *pGpu) {
+    pGpu->__gpuDetermineSelfHostedMode__(pGpu);
+}
+
+void gpuDetermineMIGSupport_GH100(struct OBJGPU *pGpu);
+
+static inline void gpuDetermineMIGSupport_b3696a(struct OBJGPU *pGpu) {
+    return;
+}
+
+static inline void gpuDetermineMIGSupport_DISPATCH(struct OBJGPU *pGpu) {
+    pGpu->__gpuDetermineMIGSupport__(pGpu);
+}
+
 NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(struct OBJGPU *pGpu);

 static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_491d52(struct OBJGPU *pGpu) {
@@ -2873,6 +3125,36 @@ static inline NvBool gpuIsSliCapableWithoutDisplay_DISPATCH(struct OBJGPU *pGpu)
    return pGpu->__gpuIsSliCapableWithoutDisplay__(pGpu);
 }

+NvBool gpuIsCCEnabledInHw_GH100(struct OBJGPU *pGpu);
+
+static inline NvBool gpuIsCCEnabledInHw_491d52(struct OBJGPU *pGpu) {
+    return ((NvBool)(0 != 0));
+}
+
+static inline NvBool gpuIsCCEnabledInHw_DISPATCH(struct OBJGPU *pGpu) {
+    return pGpu->__gpuIsCCEnabledInHw__(pGpu);
+}
+
+NvBool gpuIsDevModeEnabledInHw_GH100(struct OBJGPU *pGpu);
+
+static inline NvBool gpuIsDevModeEnabledInHw_491d52(struct OBJGPU *pGpu) {
+    return ((NvBool)(0 != 0));
+}
+
+static inline NvBool gpuIsDevModeEnabledInHw_DISPATCH(struct OBJGPU *pGpu) {
+    return pGpu->__gpuIsDevModeEnabledInHw__(pGpu);
+}
+
+NvBool gpuIsCtxBufAllocInPmaSupported_GA100(struct OBJGPU *pGpu);
+
+static inline NvBool gpuIsCtxBufAllocInPmaSupported_491d52(struct OBJGPU *pGpu) {
+    return ((NvBool)(0 != 0));
+}
+
+static inline NvBool gpuIsCtxBufAllocInPmaSupported_DISPATCH(struct OBJGPU *pGpu) {
+    return pGpu->__gpuIsCtxBufAllocInPmaSupported__(pGpu);
+}
+
 static inline PENGDESCRIPTOR gpuGetInitEngineDescriptors(struct OBJGPU *pGpu) {
    return pGpu->engineOrder.pEngineInitDescriptors;
 }
@@ -2930,22 +3212,6 @@ static inline RmPhysAddr gpuGetDmaStartAddress(struct OBJGPU *pGpu) {
    return pGpu->dmaStartAddress;
 }

-static inline NvBool gpuIsCCFeatureEnabled(struct OBJGPU *pGpu) {
-    return ((NvBool)(0 != 0));
-}
-
-static inline NvBool gpuIsApmFeatureEnabled(struct OBJGPU *pGpu) {
-    return ((NvBool)(0 != 0));
-}
-
-static inline NvBool gpuIsCCorApmFeatureEnabled(struct OBJGPU *pGpu) {
-    return ((NvBool)(0 != 0));
-}
-
-static inline NvBool gpuIsInCCorApmDevMode(struct OBJGPU *pGpu) {
-    return ((NvBool)(0 != 0));
-}
-
 static inline NV_STATUS gpuFreeEventHandle(struct OBJGPU *pGpu) {
    return NV_OK;
 }
@@ -3094,6 +3360,10 @@ static inline NvBool gpuIsVgxBranded(struct OBJGPU *pGpu) {
    return pGpu->bIsVgx;
 }

+static inline NvBool gpuIsACBranded(struct OBJGPU *pGpu) {
+    return pGpu->bIsAC;
+}
+
 static inline NvBool gpuIsNvidiaNvsBranded(struct OBJGPU *pGpu) {
    return pGpu->bIsNvidiaNvs;
 }
@@ -3114,6 +3384,10 @@ static inline NvBool gpuIsSriovCapable(struct OBJGPU *pGpu) {
    return pGpu->bSriovCapable;
 }

+static inline NvBool gpuIsSelfHosted(struct OBJGPU *pGpu) {
+    return pGpu->bIsSelfHosted;
+}
+
 static inline NvBool gpuIsGspOwnedFaultBuffersEnabled(struct OBJGPU *pGpu) {
    return pGpu->bIsGspOwnedFaultBuffersEnabled;
 }
@@ -3121,15 +3395,15 @@ static inline NvBool gpuIsGspOwnedFaultBuffersEnabled(struct OBJGPU *pGpu) {
 NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance);

 #define __nvoc_gpuConstruct(arg_pGpu, arg_gpuInstance) gpuConstruct_IMPL(arg_pGpu, arg_gpuInstance)
-NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1);
+NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1, NvU32 socChipId0);

 #ifdef __nvoc_gpu_h_disabled
-static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1) {
+static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1, NvU32 socChipId0) {
    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
    return NV_ERR_NOT_SUPPORTED;
 }
 #else //__nvoc_gpu_h_disabled
-#define gpuBindHalLegacy(pGpu, chipId0, chipId1) gpuBindHalLegacy_IMPL(pGpu, chipId0, chipId1)
+#define gpuBindHalLegacy(pGpu, chipId0, chipId1, socChipId0) gpuBindHalLegacy_IMPL(pGpu, chipId0, chipId1, socChipId0)
 #endif //__nvoc_gpu_h_disabled

 NV_STATUS gpuPostConstruct_IMPL(struct OBJGPU *pGpu, GPUATTACHARG *arg0);
@@ -3932,6 +4206,61 @@ static inline NV_STATUS gpuFindClientInfoWithPidIterator(struct OBJGPU *pGpu, Nv
 #define gpuFindClientInfoWithPidIterator(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo) gpuFindClientInfoWithPidIterator_IMPL(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo)
 #endif //__nvoc_gpu_h_disabled

+NvBool gpuIsCCFeatureEnabled_IMPL(struct OBJGPU *pGpu);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NvBool gpuIsCCFeatureEnabled(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_FALSE;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuIsCCFeatureEnabled(pGpu) gpuIsCCFeatureEnabled_IMPL(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+NvBool gpuIsApmFeatureEnabled_IMPL(struct OBJGPU *pGpu);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NvBool gpuIsApmFeatureEnabled(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_FALSE;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuIsApmFeatureEnabled(pGpu) gpuIsApmFeatureEnabled_IMPL(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+NvBool gpuIsCCorApmFeatureEnabled_IMPL(struct OBJGPU *pGpu);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NvBool gpuIsCCorApmFeatureEnabled(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_FALSE;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuIsCCorApmFeatureEnabled(pGpu) gpuIsCCorApmFeatureEnabled_IMPL(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+NvBool gpuIsCCDevToolsModeEnabled_IMPL(struct OBJGPU *pGpu);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NvBool gpuIsCCDevToolsModeEnabled(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_FALSE;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuIsCCDevToolsModeEnabled(pGpu) gpuIsCCDevToolsModeEnabled_IMPL(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+NvBool gpuIsOnTheBus_IMPL(struct OBJGPU *pGpu);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NvBool gpuIsOnTheBus(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_FALSE;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuIsOnTheBus(pGpu) gpuIsOnTheBus_IMPL(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
 NV_STATUS gpuEnterStandby_IMPL(struct OBJGPU *pGpu);

 #ifdef __nvoc_gpu_h_disabled
@@ -4041,6 +4370,39 @@ static inline NV_STATUS gpuSetGC6SBIOSCapabilities(struct OBJGPU *pGpu) {
 #define gpuSetGC6SBIOSCapabilities(pGpu) gpuSetGC6SBIOSCapabilities_IMPL(pGpu)
 #endif //__nvoc_gpu_h_disabled

+NV_STATUS gpuGc6Entry_IMPL(struct OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *arg0);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuGc6Entry(struct OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *arg0) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuGc6Entry(pGpu, arg0) gpuGc6Entry_IMPL(pGpu, arg0)
+#endif //__nvoc_gpu_h_disabled
+
+NV_STATUS gpuGc6EntryGpuPowerOff_IMPL(struct OBJGPU *pGpu);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuGc6EntryGpuPowerOff(struct OBJGPU *pGpu) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuGc6EntryGpuPowerOff(pGpu) gpuGc6EntryGpuPowerOff_IMPL(pGpu)
+#endif //__nvoc_gpu_h_disabled
+
+NV_STATUS gpuGc6Exit_IMPL(struct OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *arg0);
+
+#ifdef __nvoc_gpu_h_disabled
+static inline NV_STATUS gpuGc6Exit(struct OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *arg0) {
+    NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
+    return NV_ERR_NOT_SUPPORTED;
+}
+#else //__nvoc_gpu_h_disabled
+#define gpuGc6Exit(pGpu, arg0) gpuGc6Exit_IMPL(pGpu, arg0)
+#endif //__nvoc_gpu_h_disabled
+
 #undef PRIVATE_FIELD


@@ -4055,12 +4417,13 @@ NV_STATUS gpuGetByHandle(struct RsClient *pClient, NvHandle hResource, NvBool *p
 #define IS_GFID_VF(gfid)    (((NvU32)(gfid)) != GPU_GFID_PF)
 // Invalid P2P GFID
 #define INVALID_P2P_GFID    (0xFFFFFFFF)
+#define INVALID_FABRIC_PARTITION_ID (0xFFFFFFFF)

 //
 // Generates GPU child accessor macros (i.e.: GPU_GET_{ENG})
 //
 #define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \
-    static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return pGpu->gpuField; } \
+    static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return pGpu->gpuField; }      \
    ct_assert(numInstances == 1);

 #define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \
@@ -4141,7 +4504,6 @@ static NvU32 gpuGetNumCEs(struct OBJGPU *pGpu)
 // IS_SILICON       Real hardware
 // IS_VIRTUAL       RM is running within a guest VM
 // IS_GSP_CLIENT    RM is a GSP/DCE client with GPU support offloaded to GSP/DCE
-// IS_FW_CLIENT     RM is a firmware client with GPU support offloaded microprocessor
 //

 #define IS_EMULATION(pGpu)                 ((pGpu)->getProperty((pGpu), PDB_PROP_GPU_EMULATION))
@@ -4152,7 +4514,6 @@ static NvU32 gpuGetNumCEs(struct OBJGPU *pGpu)
 #define IS_SILICON(pGpu)                   (!(IS_EMULATION(pGpu) || IS_SIMULATION(pGpu)))
 #define IS_PASSTHRU(pGpu)                  ((pGpu)->bIsPassthru)
 #define IS_GSP_CLIENT(pGpu)                ((RMCFG_FEATURE_GSP_CLIENT_RM || RMCFG_FEATURE_DCE_CLIENT_RM) && (pGpu)->isGspClient)
-#define IS_FW_CLIENT(pGpu)                 IS_GSP_CLIENT(pGpu) // TODO to be removed
 #define IS_VIRTUAL(pGpu)                         NV_FALSE
 #define IS_VIRTUAL_WITH_SRIOV(pGpu)              NV_FALSE
 #define IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu)        NV_FALSE
@@ -4269,13 +4630,6 @@ VGPU_STATIC_INFO *gpuGetStaticInfo(struct OBJGPU *pGpu);
 GspStaticConfigInfo *gpuGetGspStaticInfo(struct OBJGPU *pGpu);
 #define GPU_GET_GSP_STATIC_INFO(pGpu) gpuGetGspStaticInfo(pGpu)

-
-#define IS_GPU_GC6_STATE_POWERED_ON(obj) NV_TRUE
-#define IS_GPU_GC6_STATE_EXITED(obj)     NV_FALSE
-#define IS_GPU_GC6_STATE_ENTERING(obj)   NV_FALSE
-#define IS_GPU_GC6_STATE_ENTERED(obj)    NV_FALSE
-#define IS_GPU_GC6_STATE_EXITING(obj)    NV_FALSE
-
 #endif // _OBJGPU_H_

 #ifdef __cplusplus