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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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535.43.02
This commit is contained in:
Andy Ritger
157
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
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157
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _CHANNEL_UTILS_H_
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#define _CHANNEL_UTILS_H_
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#include "core/core.h"
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#include "gpu/gpu.h"
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#include "gpu/mem_mgr/mem_mgr.h"
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#include "gpu/ce/kernel_ce.h"
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#include "gpu/bus/kern_bus.h"
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#include "core/prelude.h"
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#include "rmapi/rs_utils.h"
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#include "nvos.h"
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#include "class/cl906f.h"
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#include "class/cl906f.h"
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#include "class/cl906fsw.h"
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#include "class/clb0b5.h" // MAXWELL_DMA_COPY_A
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#include "class/clc0b5.h" // PASCAL_DMA_COPY_A
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#include "class/clc1b5.h" // PASCAL_DMA_COPY_B
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#include "class/clc3b5.h" // VOLTA_DMA_COPY_A
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#include "class/clc5b5.h" // TURING_DMA_COPY_A
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#include "class/clc6b5.h" // AMPERE_DMA_COPY_A
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#include "class/clc7b5.h" // AMPERE_DMA_COPY_B
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#include "class/clc8b5.h" // HOPPER_DMA_COPY_A
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#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A
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#include "nvctassert.h"
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#include "vgpu/vgpu_guest_pma_scrubber.h"
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#define RM_SUBCHANNEL 0x0
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#define NV_PUSH_METHOD(OpType, SubCh, Method, Count) \
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(DRF_DEF(906F, _DMA, _SEC_OP, OpType) | \
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DRF_NUM(906F, _DMA, _METHOD_ADDRESS, (Method) >> 2) | \
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DRF_NUM(906F, _DMA, _METHOD_SUBCHANNEL, (SubCh)) | \
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DRF_NUM(906F, _DMA, _METHOD_COUNT, (Count)))
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#define _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2) NV_ASSERT((a2) - (a1) == 4)
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#define NV_PUSH_DATA(Data) MEM_WR32(pPtr++, (Data))
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#define _NV_PUSH_INC_1U(SubCh, a1, d1, Count) \
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do \
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{ \
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NV_PUSH_DATA(NV_PUSH_METHOD(_INC_METHOD, SubCh, a1, Count)); \
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NV_PUSH_DATA(d1); \
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} while (0)
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#define NV_PUSH_INC_1U(SubCh, a1, d1) \
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do \
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{ \
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_NV_PUSH_INC_1U (SubCh, a1, d1, 1); \
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} while (0)
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#define NV_PUSH_INC_2U(SubCh, a1, d1, a2, d2) \
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do \
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{ \
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_NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \
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_NV_PUSH_INC_1U(SubCh, a1, d1, 2); \
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NV_PUSH_DATA(d2); \
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} while (0)
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#define NV_PUSH_INC_3U(SubCh, a1, d1, a2, d2, a3, d3) \
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do \
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{ \
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_NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \
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_NV_ASSERT_CONTIGUOUS_METHOD(a2, a3); \
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_NV_PUSH_INC_1U(SubCh, a1, d1, 3); \
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NV_PUSH_DATA(d2); \
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NV_PUSH_DATA(d3); \
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} while (0)
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#define NV_PUSH_INC_4U(SubCh, a1, d1, a2, d2, a3, d3, a4, d4) \
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do \
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{ \
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_NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \
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_NV_ASSERT_CONTIGUOUS_METHOD(a2, a3); \
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_NV_ASSERT_CONTIGUOUS_METHOD(a3, a4); \
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_NV_PUSH_INC_1U(SubCh, a1, d1, 4); \
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NV_PUSH_DATA(d2); \
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NV_PUSH_DATA(d3); \
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NV_PUSH_DATA(d4); \
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} while (0)
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#define READ_CHANNEL_PAYLOAD_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA + \
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channel->finishPayloadOffset)
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#define READ_CHANNEL_PB_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA + \
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channel->semaOffset)
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#define WRITE_CHANNEL_PB_SEMA(channel, val) MEM_WR32((NvU8*)channel->pbCpuVA + \
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channel->semaOffset, val);
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#define WRITE_CHANNEL_PAYLOAD_SEMA(channel,val) MEM_WR32((NvU8*)channel->pbCpuVA + \
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channel->finishPayloadOffset, val);
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//
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// This struct contains parameters needed to send a pushbuffer for a CE
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// operation. This interface only supports contiguous operations.
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//
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typedef struct
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{
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NvBool bCeMemcopy; // Whether this is a CE memcopy;
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// If set to false, this will be a memset operation
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NvU64 dstAddr; // Physical address of the source address
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NvU64 srcAddr; // Physical address of the source address; only valid for memcopy
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NvU32 size;
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NvU32 pattern; // Fixed pattern to memset to. Only valid for memset
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NvU32 payload; // Payload value used to release semaphore
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NvU64 clientSemaAddr;
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NV_ADDRESS_SPACE dstAddressSpace;
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NV_ADDRESS_SPACE srcAddressSpace;
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NvU32 dstCpuCacheAttrib;
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NvU32 srcCpuCacheAttrib;
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} CHANNEL_PB_INFO;
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NV_STATUS channelSetupIDs(OBJCHANNEL *pChannel, OBJGPU *pGpu, NvBool bUseVasForCeCopy, NvBool bMIGInUse);
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void channelSetupChannelBufferSizes(OBJCHANNEL *pChannel);
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// Needed for pushbuffer management
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NV_STATUS channelWaitForFreeEntry(OBJCHANNEL *pChannel, NvU32 *pPutIndex);
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NV_STATUS channelFillGpFifo(OBJCHANNEL *pChannel, NvU32 putIndex, NvU32 methodsLength);
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NvU32 channelFillPb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
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NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
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NvU32 channelFillPbFastScrub(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
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NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
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// Needed for work tracking
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NV_STATUS channelWaitForFinishPayload(OBJCHANNEL *pChannel, NvU64 targetPayload);
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NvU64 channelGetFinishPayload(OBJCHANNEL *pChannel);
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#endif // _CHANNEL_UTILS_H_
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