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525.105.17

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This commit is contained in:
Andy Ritger
2023-03-30 10:16:11 -07:00
parent e598191e8e
commit ebcc6656ff
100 changed files with 2912 additions and 1117 deletions
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4
src/common/displayport/inc/dp_connector.h
View File

@@ -213,6 +213,10 @@ namespace DisplayPort
virtual NvBool isDSCSupported() = 0;
virtual NvBool isDSCDecompressionSupported() = 0;
virtual NvBool isDSCPassThroughSupported() = 0;
virtual DscCaps getDscCaps() = 0;
//

1
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -447,6 +447,7 @@ namespace DisplayPort
bool getFECSupport();
NvBool isDSCPassThroughSupported();
NvBool isDSCSupported();
NvBool isDSCDecompressionSupported();
NvBool isDSCPossible();
bool isFECSupported();
bool readAndParseDSCCaps();

4
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -5539,7 +5539,8 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
if (existingDev && existingDev->isFakedMuxDevice() && !bIsMuxOnDgpu)
{
DP_LOG((" NotifyLongPulse ignored as mux is not pointing to dGPU and there is a faked device"));
DP_LOG((" NotifyLongPulse ignored as mux is not pointing to dGPU and there is a faked device. Marking detect complete"));
sink->notifyDetectComplete();
return;
}
@@ -6513,6 +6514,7 @@ void ConnectorImpl::createFakeMuxDevice(const NvU8 *buffer, NvU32 bufferSize)
// Initialize DSC state
newDev->dscCaps.bDSCSupported = true;
newDev->dscCaps.bDSCDecompressionSupported = true;
newDev->parseDscCaps(buffer, bufferSize);
dpMemCopy(newDev->rawDscCaps, buffer, DP_MIN(bufferSize, 16));
newDev->bDSCPossible = true;

33
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1508,7 +1508,11 @@ NvBool DeviceImpl::getDSCSupport()
{
if (FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DSC_SUPPORT, _YES, byte))
{
dscCaps.bDSCSupported = true;
dscCaps.bDSCDecompressionSupported = true;
}
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, byte))
{
dscCaps.bDSCPassThroughSupported = true;
}
}
@@ -1517,6 +1521,11 @@ NvBool DeviceImpl::getDSCSupport()
DP_LOG(("DP-DEV> DSC Support AUX READ failed for %s!", address.toString(sb)));
}
if (dscCaps.bDSCDecompressionSupported || dscCaps.bDSCPassThroughSupported)
{
dscCaps.bDSCSupported = true;
}
return dscCaps.bDSCSupported;
}
@@ -1636,6 +1645,11 @@ NvBool DeviceImpl::isDSCSupported()
return dscCaps.bDSCSupported;
}
NvBool DeviceImpl::isDSCDecompressionSupported()
{
return dscCaps.bDSCDecompressionSupported;
}
NvBool DeviceImpl::isDSCPassThroughSupported()
{
return dscCaps.bDSCPassThroughSupported;
@@ -1974,7 +1988,7 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
this->devDoingDscDecompression = this;
this->bDSCPossible = true;
}
else if (this->parent->isDSCSupported())
else if (this->parent->isDSCDecompressionSupported())
{
//
// This condition takes care of DSC capable sink devices
@@ -1987,12 +2001,15 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
}
else
{
// This condition takes care of branch device capable of DSC.
this->devDoingDscDecompression = this;
this->bDSCPossible = true;
if (this->isDSCDecompressionSupported())
{
// This condition takes care of branch device capable of DSC decoding.
this->devDoingDscDecompression = this;
this->bDSCPossible = true;
}
}
}
else if (this->parent && this->parent->isDSCSupported())
}
else if (this->parent && this->parent->isDSCDecompressionSupported())
{
//
// This condition takes care of sink devices not capable of DSC
@@ -2005,7 +2022,7 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
}
else
{
if (this->isDSCSupported())
if (this->isDSCDecompressionSupported())
{
this->bDSCPossible = true;
this->devDoingDscDecompression = this;

1
src/common/inc/displayport/displayport.h
View File

@@ -240,6 +240,7 @@ typedef enum
typedef struct DscCaps
{
NvBool bDSCSupported;
NvBool bDSCDecompressionSupported;
NvBool bDSCPassThroughSupported;
unsigned versionMajor, versionMinor;
unsigned rcBufferBlockSize;

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r528_37
#define NV_BUILD_BRANCH r528_79
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r528_37
#define NV_PUBLIC_BRANCH r528_79
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r528_37-265"
#define NV_BUILD_CHANGELIST_NUM (32376659)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r528_79-332"
#define NV_BUILD_CHANGELIST_NUM (32663405)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r525/r528_37-265"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32376659)
#define NV_BUILD_NAME "rel/gpu_drv/r525/r528_79-332"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32663405)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r528_37-4"
#define NV_BUILD_CHANGELIST_NUM (32375411)
#define NV_BUILD_BRANCH_VERSION "r528_79-9"
#define NV_BUILD_CHANGELIST_NUM (32663405)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "528.46"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32375411)
#define NV_BUILD_NAME "528.89"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32663405)
#define NV_BUILD_BRANCH_BASE_VERSION R525
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "525.89.02"
#define NV_VERSION_STRING "525.105.17"
#else

7
src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,11 @@
#ifndef __gh100_dev_fsp_addendum_h__
#define __gh100_dev_fsp_addendum_h__
#define NV_GFW_FSP_UCODE_VERSION NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(1)
#define NV_GFW_FSP_UCODE_VERSION_FULL 11:0
#define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8
#define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0
//
// RM uses channel 0 for FSP EMEM on GH100.
//

6
src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -64,5 +64,9 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gh100_dev_fsp_pri_h__

10
src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,14 @@
#ifndef __gh100_dev_gc6_island_h__
#define __gh100_dev_gc6_island_h__
#define NV_PGC6_SCI_SEC_TIMER_TIME_0 0x00118f54 /* RW-4R */
#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC 31:5 /* RWEUF */
#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1 0x00118f58 /* RW-4R */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC 28:0 /* RWEUF */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0 0x00118df4 /* RW-4R */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE 0:0 /* RWEVF */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_DONE 0x00000000 /* R-E-V */

8
src/common/modeset/timing/nvt_edid.c
View File

@@ -2098,8 +2098,8 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
// validate DTD blocks
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset];
while (pDTD->wDTPixelClock != 0 &&
(NvU8 *)pDTD - pExt < (int)sizeof(EIA861EXTENSION))
while ((pDTD->wDTPixelClock != 0) &&
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) - 1)))
{
if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS)
{
@@ -2342,8 +2342,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
// validate DTD blocks
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset];
while (pDTD->wDTPixelClock != 0 &&
(NvU8 *)pDTD - pExt < (int)sizeof(EIA861EXTENSION))
while ((pDTD->wDTPixelClock != 0) &&
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) -1)))
{
if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD);

13
src/common/modeset/timing/nvt_edidext_861.c
View File

@@ -397,7 +397,7 @@ void parse861ExtDetailedTiming(NvU8 *pEdidExt,
// Get all detailed timings in CEA ext block
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pEdidExt[pEIA861->offset];
while((NvU8 *)pDTD < (pEdidExt + sizeof(EDIDV1STRUC)) && // Check that we're not going beyond this extension block.
while((NvU8 *)pDTD + sizeof(DETAILEDTIMINGDESCRIPTOR) < (pEdidExt + sizeof(EDIDV1STRUC) - 1) &&
pDTD->wDTPixelClock != 0)
{
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
@@ -1237,6 +1237,12 @@ NVT_STATUS get861ExtInfo(NvU8 *p, NvU32 size, NVT_EDID_CEA861_INFO *p861info)
return NVT_STATUS_ERR;
}
// DTD offset sanity check
if (p[2] >= 1 && p[2] <= 3)
{
return NVT_STATUS_ERR;
}
// don't do anything further if p861info is NULL
if (p861info == NULL)
{
@@ -1299,6 +1305,11 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
tag = NVT_CEA861_GET_SHORT_DESCRIPTOR_TAG(p[i]);
payload = NVT_CEA861_GET_SHORT_DESCRIPTOR_SIZE(p[i]);
/*don't allow data colleciton totally size larger than [127 - 5 (tag, revision, offset, describing native video format, checksum)]*/
if ((i + payload > size) || (i + payload > 122))
{
return NVT_STATUS_ERR;
}
// move the pointer to the payload section or extended Tag Code
i++;

24
src/common/nvswitch/common/inc/soe/soeifcore.h
View File

@@ -74,14 +74,18 @@ enum
/*!
* Read VRs
* Needed to be in sync with chips_a defines
*/
RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES,
/*!
* Init PLM2 protected registers
*/
RM_SOE_CORE_CMD_INIT_L2_STATE
RM_SOE_CORE_CMD_INIT_L2_STATE,
/*!
* Read Power
*/
RM_SOE_CORE_CMD_GET_POWER_VALUES,
};
// Timeout for SOE reset callback function
@@ -153,6 +157,11 @@ typedef struct
NvU8 cmdType;
} RM_SOE_CORE_CMD_L2_STATE;
typedef struct
{
NvU8 cmdType;
} RM_SOE_CORE_CMD_GET_POWER;
typedef union
{
NvU8 cmdType;
@@ -164,6 +173,7 @@ typedef union
RM_SOE_CORE_CMD_NPORT_TPROD_STATE nportTprodState;
RM_SOE_CORE_CMD_GET_VOLTAGE getVoltage;
RM_SOE_CORE_CMD_L2_STATE l2State;
RM_SOE_CORE_CMD_GET_POWER getPower;
} RM_SOE_CORE_CMD;
@@ -176,9 +186,19 @@ typedef struct
NvU32 hvdd_mv;
} RM_SOE_CORE_MSG_GET_VOLTAGE;
typedef struct
{
NvU8 msgType;
NvU8 flcnStatus;
NvU32 vdd_w;
NvU32 dvdd_w;
NvU32 hvdd_w;
} RM_SOE_CORE_MSG_GET_POWER;
typedef union
{
NvU8 msgType;
RM_SOE_CORE_MSG_GET_VOLTAGE getVoltage;
RM_SOE_CORE_MSG_GET_POWER getPower;
} RM_SOE_CORE_MSG;
#endif // _SOECORE_H_

27
src/common/nvswitch/interface/ctrl_dev_nvswitch.h
View File

@@ -751,6 +751,19 @@ typedef struct
NvU32 hvdd_mv;
} NVSWITCH_CTRL_GET_VOLTAGE_PARAMS;
/*
* CTRL_NVSWITCH_GET_POWER
*
* Zero(0) indicates that a measurement is not available
* on the current platform.
*/
typedef struct
{
NvU32 vdd_w;
NvU32 dvdd_w;
NvU32 hvdd_w;
} NVSWITCH_GET_POWER_PARAMS;
/*
* CTRL_NVSWITCH_GET_ERRORS
*
@@ -3534,6 +3547,15 @@ typedef struct
#define NVSWITCH_CTRL_I2C_MESSAGE_LENGTH_MAX 256
typedef enum
{
NVSWITCH_I2C_ACQUIRER_NONE = 0,
NVSWITCH_I2C_ACQUIRER_UNKNOWN,
NVSWITCH_I2C_ACQUIRER_IOCTL, // e.g. MODS
NVSWITCH_I2C_ACQUIRER_EXTERNAL, // e.g. Linux Direct
} NVSWITCH_I2C_ACQUIRER;
/*
* CTRL_NVSWITCH_I2C_INDEXED
*
@@ -3816,8 +3838,9 @@ typedef struct
#define CTRL_NVSWITCH_CLEAR_COUNTERS 0x51
#define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52
#define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53
#define CTRL_NVSWITCH_GET_VOLTAGE 0x55
#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x54
#define CTRL_NVSWITCH_GET_VOLTAGE 0x54
#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x55
#define CTRL_NVSWITCH_GET_POWER 0x56
#ifdef __cplusplus
}

3
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -224,7 +224,8 @@
_op(NvlStatus, nvswitch_ctrl_set_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \
_op(NvlStatus, nvswitch_ctrl_therm_read_voltage, (nvswitch_device *device, NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch)
_op(NvlStatus, nvswitch_ctrl_therm_read_power, (nvswitch_device *device, NVSWITCH_GET_POWER_PARAMS *info), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) \
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
_op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \

7
src/common/nvswitch/kernel/inc/lr10/therm_lr10.h
View File

@@ -62,4 +62,11 @@ nvswitch_ctrl_therm_read_voltage_lr10
NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info
);
NvlStatus
nvswitch_ctrl_therm_read_power_lr10
(
nvswitch_device *device,
NVSWITCH_GET_POWER_PARAMS *info
);
#endif //_THERM_LR10_H_

8
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -497,8 +497,8 @@ typedef struct
NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \
}
#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1SEC_IN_NS)
#define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1MSEC_IN_NS)
#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1SEC_IN_NS)
#define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1MSEC_IN_NS)
// Struct used for passing around error masks in error handling functions
typedef struct
@@ -978,6 +978,7 @@ void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 l
void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link);
void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link);
void nvswitch_set_dlpl_interrupts_ls10(nvlink_link *link);
NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask);
void nvswitch_service_minion_all_links_ls10(nvswitch_device *device);
@@ -997,9 +998,6 @@ NvlStatus nvswitch_launch_ALI_ls10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_set_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p);
NvlStatus nvswitch_ctrl_get_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p);
void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link);
NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask);
void nvswitch_service_minion_all_links_ls10(nvswitch_device *device);
NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device);

17
src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h
View File

@@ -24,6 +24,21 @@
#ifndef _MINION_NVLINK_DEFINES_PUBLIC_H_
#define _MINION_NVLINK_DEFINES_PUBLIC_H_
//PAD REG READ API (Bug 2643883)
#define NV_MINION_UCODE_READUPHYPAD_ADDR 11:0
#define NV_MINION_UCODE_READUPHYPAD_LANE 15:12
//FIELD FOR DEBUG_MISC_i DATA REGISTERS
#define NV_MINION_DEBUG_MISC_0_LINK_STATE 7:0
#define NV_MINION_DEBUG_MISC_0_ISR_ID 15:8
#define NV_MINION_DEBUG_MISC_0_OTHER_DATA 31:16
// Recal values checks
#define NV_MINION_UCODE_L1_EXIT_MARGIN 100
#define NV_MINION_UCODE_L1_EXIT_MAX 200
#define NV_MINION_UCODE_RECOVERY_TIME 250
#define NV_MINION_UCODE_PEQ_TIME 96
// SUBCODES for DLCMD FAULT (uses DLCMDFAULR code) - dlCmdFault() - NVLINK_LINK_INT
typedef enum _MINION_STATUS
{
@@ -31,4 +46,6 @@ typedef enum _MINION_STATUS
MINION_ALARM_BUSY = 80,
} MINION_STATUS;
#define LINKSTATUS_EMERGENCY_SHUTDOWN 0x29
#define LINKSTATUS_INITPHASE1 0x24
#endif // _MINION_NVLINK_DEFINES_PUBLIC_H_

7
src/common/nvswitch/kernel/inc/ls10/therm_ls10.h
View File

@@ -56,4 +56,11 @@ nvswitch_ctrl_therm_read_voltage_ls10
nvswitch_device *device,
NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info
);
NvlStatus
nvswitch_ctrl_therm_read_power_ls10
(
nvswitch_device *device,
NVSWITCH_GET_POWER_PARAMS *info
);
#endif //_THERM_LS10_H_

10
src/common/nvswitch/kernel/inc/pmgr_nvswitch.h
View File

@@ -164,16 +164,6 @@ typedef struct
NvBool bBlockProtocol;
} NVSWITCH_I2C_HW_CMD, *PNVSWITCH_I2C_HW_CMD;
typedef enum
{
NVSWITCH_I2C_ACQUIRER_NONE = 0,
NVSWITCH_I2C_ACQUIRER_UNKNOWN,
NVSWITCH_I2C_ACQUIRER_IOCTL, // e.g. MODS
NVSWITCH_I2C_ACQUIRER_EXTERNAL, // e.g. Linux Direct
} NVSWITCH_I2C_ACQUIRER;
typedef enum {
i2cProfile_Standard,
i2cProfile_Fast,

6
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b,
0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2,
0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043,
0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200,
0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d,
0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb22438cf, 0xcfd90bc8, 0xf23ebc55, 0x2e5c0e40,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x0d4a5d7d, 0x9c31ffb3, 0x95bc604f, 0x40cc834d,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xf4188925, 0x3294f034, 0x06c315a3, 0x41c3e219,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x8cd89b95, 0x33df19d3, 0xaba62f3f, 0x5fd448c8,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

6
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b,
0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2,
0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043,
0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200,
0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d,
0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb22438cf, 0xcfd90bc8, 0xf23ebc55, 0x2e5c0e40,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x0d4a5d7d, 0x9c31ffb3, 0x95bc604f, 0x40cc834d,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xf4188925, 0x3294f034, 0x06c315a3, 0x41c3e219,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x8cd89b95, 0x33df19d3, 0xaba62f3f, 0x5fd448c8,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

10
src/common/nvswitch/kernel/lr10/therm_lr10.c
View File

@@ -314,3 +314,13 @@ nvswitch_ctrl_therm_read_voltage_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_ctrl_therm_read_power_lr10
(
nvswitch_device *device,
NVSWITCH_GET_POWER_PARAMS *info
)
{
return -NVL_ERR_NOT_SUPPORTED;
}

454
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -258,7 +258,7 @@ _nvswitch_initialize_route_interrupts
DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _EXTMCRID_ECC_LIMIT_ERR, _ENABLE) |
DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _RAM_ECC_LIMIT_ERR, _ENABLE) |
DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_MCRID_ERR, _ENABLE);
// NOTE: _MC_TRIGGER_ERR is debug-use only
// NOTE: _MC_TRIGGER_ERR is debug-use only
}
static void
@@ -456,8 +456,8 @@ _nvswitch_initialize_nport_interrupts_ls10
nvswitch_device *device
)
{
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NvU32 val;
val =
@@ -516,7 +516,7 @@ _nvswitch_initialize_nxbar_interrupts_ls10
DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1) |
DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, 1);
// Moving this L2 register access to SOE. Refer bug #3747687
// Moving this L2 register access to SOE. Refer bug #3747687
#if 0
NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, report_fatal);
#endif // 0
@@ -532,7 +532,7 @@ _nvswitch_initialize_nxbar_interrupts_ls10
* IRQMASK is used to read in mask of interrupts
* IRQDEST is used to read in enabled interrupts that are routed to the HOST
*
* IRQSTAT & IRQMASK gives the pending interrupting on this minion
* IRQSTAT & IRQMASK gives the pending interrupting on this minion
*
* @param[in] device MINION on this device
* @param[in] instance MINION instance
@@ -561,7 +561,7 @@ nvswitch_minion_service_falcon_interrupts_ls10
return -NVL_NOT_FOUND;
}
unhandled = pending;
unhandled = pending;
bit = DRF_NUM(_CMINION_FALCON, _IRQSTAT, _WDTMR, 1);
if (nvswitch_test_flags(pending, bit))
@@ -761,7 +761,7 @@ _nvswitch_service_priv_ring_ls10
if (pending != 0)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_PRIV_ERROR,
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_PRIV_ERROR,
"Fatal, Unexpected PRI error\n");
NVSWITCH_LOG_FATAL_DATA(device, _HW, _HW_HOST_PRIV_ERROR, 2, 0, NV_FALSE, &pending);
@@ -821,7 +821,7 @@ _nvswitch_collect_nport_error_info_ls10
}
while (register_start <= register_end);
*idx = i;
return NVL_SUCCESS;
}
@@ -2177,7 +2177,7 @@ _nvswitch_service_ingress_nonfatal_ls10_err_status_1:
NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FIRST_1,
report.raw_first & report.mask);
}
NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0, pending_0);
NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_1, pending_1);
@@ -4131,13 +4131,13 @@ _nvswitch_service_npg_fatal_ls10
NvU32 link;
pending = NVSWITCH_ENG_RD32(device, NPG, , npg, _NPG, _NPG_INTERRUPT_STATUS);
if (pending == 0)
{
return -NVL_NOT_FOUND;
}
mask =
mask =
DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _FATAL) |
DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _FATAL) |
DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _FATAL) |
@@ -4234,7 +4234,7 @@ _nvswitch_service_npg_nonfatal_ls10
return -NVL_NOT_FOUND;
}
mask =
mask =
DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _NONFATAL) |
DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _NONFATAL) |
DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _NONFATAL) |
@@ -4286,10 +4286,11 @@ static NvlStatus
_nvswitch_service_nvldl_fatal_ls10
(
nvswitch_device *device,
NvU32 nvlipt_instance
NvU32 nvlipt_instance,
NvU64 intrLinkMask
)
{
NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask, runtimeErrorMask = 0;
NvU64 enabledLinkMask, localLinkMask, localIntrLinkMask, runtimeErrorMask = 0;
NvU32 i;
nvlink_link *link;
NvU32 clocksMask = NVSWITCH_PER_LINK_CLOCK_SET(RXCLK) | NVSWITCH_PER_LINK_CLOCK_SET(TXCLK);
@@ -4297,11 +4298,22 @@ _nvswitch_service_nvldl_fatal_ls10
NVSWITCH_LINK_TRAINING_ERROR_INFO linkTrainingErrorInfo = { 0 };
NVSWITCH_LINK_RUNTIME_ERROR_INFO linkRuntimeErrorInfo = { 0 };
//
// The passed in interruptLinkMask should contain a link that is part of the
// given nvlipt instance
//
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance);
localEnabledLinkMask = enabledLinkMask & localLinkMask;
localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask;
FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask)
if (localIntrLinkMask == 0)
{
NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
return -NVL_BAD_ARGS;
}
FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
@@ -4343,7 +4355,7 @@ _nvswitch_service_nvldl_fatal_ls10
NVSWITCH_PRINT(device, ERROR,
"%s: NVLDL[0x%x, 0x%llx]: Unable to send Runtime Error bitmask: 0x%llx,\n",
__FUNCTION__,
nvlipt_instance, localLinkMask,
nvlipt_instance, localIntrLinkMask,
runtimeErrorMask);
}
@@ -4869,19 +4881,31 @@ NvlStatus
_nvswitch_service_nvltlc_fatal_ls10
(
nvswitch_device *device,
NvU32 nvlipt_instance
NvU32 nvlipt_instance,
NvU64 intrLinkMask
)
{
NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask;
NvU64 enabledLinkMask, localLinkMask, localIntrLinkMask;
NvU32 i;
nvlink_link *link;
NvlStatus status = -NVL_MORE_PROCESSING_REQUIRED;
//
// The passed in interruptLinkMask should contain a link that is part of the
// given nvlipt instance
//
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance);
localEnabledLinkMask = enabledLinkMask & localLinkMask;
localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask;
FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask)
if (localIntrLinkMask == 0)
{
NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
return -NVL_BAD_ARGS;
}
FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
@@ -5314,6 +5338,12 @@ _nvswitch_emit_link_errors_nvldl_fatal_link_ls10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_UP, "LTSSM Fault Up", NV_FALSE);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE);
}
}
static void
@@ -5342,6 +5372,12 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10
nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE);
NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate");
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_CRC_COUNTER, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_CRC_COUNTER, "RX CRC Error Rate");
}
}
static void
@@ -5437,11 +5473,11 @@ _nvswitch_deferred_link_state_check_ls10
void *fn_args
)
{
NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams =
NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams =
(NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS*)fn_args;
NvU32 nvlipt_instance = pErrorReportParams->nvlipt_instance;
NvU32 link = pErrorReportParams->link;
ls10_device *chip_device;
ls10_device *chip_device;
nvlink_link *pLink;
NvU64 linkState;
@@ -5532,13 +5568,13 @@ _nvswitch_deferred_link_errors_check_ls10
NvU32 nvlipt_instance = pErrorReportParams->nvlipt_instance;
NvU32 link = pErrorReportParams->link;
ls10_device *chip_device;
NvU32 pending, bit;
NvU32 pending;
chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
pending = chip_device->deferredLinkErrors[link].fatalIntrMask.dl;
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1);
if (nvswitch_test_flags(pending, bit))
if (FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1U, pending) ||
FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1U, pending) )
{
nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link);
}
@@ -5581,10 +5617,10 @@ _nvswitch_create_deferred_link_errors_task_ls10
pErrorReportParams->nvlipt_instance = nvlipt_instance;
pErrorReportParams->link = link;
status = nvswitch_task_create_args(device, (void*)pErrorReportParams,
status = nvswitch_task_create_args(device, (void*)pErrorReportParams,
&_nvswitch_deferred_link_errors_check_ls10,
NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE |
NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE |
NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS);
}
@@ -5645,7 +5681,7 @@ _nvswitch_service_nvldl_nonfatal_link_ls10
if (nvswitch_test_flags(pending, bit))
{
chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl |= bit;
_nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link);
_nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link);
nvswitch_clear_flags(&unhandled, bit);
}
@@ -5666,7 +5702,9 @@ _nvswitch_service_nvldl_nonfatal_link_ls10
bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_CRC_COUNTER, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_CRC_COUNTER, "RX CRC Counter");
chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl |= bit;
_nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link);
nvswitch_clear_flags(&unhandled, bit);
//
@@ -5698,20 +5736,33 @@ static NvlStatus
_nvswitch_service_nvldl_nonfatal_ls10
(
nvswitch_device *device,
NvU32 nvlipt_instance
NvU32 nvlipt_instance,
NvU64 intrLinkMask
)
{
NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask;
NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask;
NvU32 i;
nvlink_link *link;
NvlStatus status;
NvlStatus return_status = -NVL_NOT_FOUND;
NvU32 clocksMask = NVSWITCH_PER_LINK_CLOCK_SET(RXCLK) | NVSWITCH_PER_LINK_CLOCK_SET(TXCLK);
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance);
localEnabledLinkMask = enabledLinkMask & localLinkMask;
FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask)
//
// The passed in interruptLinkMask should contain a link that is part of the
// given nvlipt instance
//
localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance);
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask;
if (localIntrLinkMask == 0)
{
NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
return -NVL_BAD_ARGS;
}
FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
@@ -6084,20 +6135,28 @@ static NvlStatus
_nvswitch_service_nvltlc_nonfatal_ls10
(
nvswitch_device *device,
NvU32 nvlipt_instance
NvU32 nvlipt_instance,
NvU64 intrLinkMask
)
{
NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask;
NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask;
NvU32 i;
nvlink_link *link;
NvlStatus status;
NvlStatus return_status = NVL_SUCCESS;
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance);
localEnabledLinkMask = enabledLinkMask & localLinkMask;
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask;
FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask)
if (localIntrLinkMask == 0)
{
NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
return -NVL_BAD_ARGS;
}
FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask)
{
link = nvswitch_get_link(device, i);
if (link == NULL)
@@ -6199,6 +6258,16 @@ _nvswitch_service_nvlipt_lnk_status_ls10
nvswitch_corelib_training_complete_ls10(link);
nvswitch_init_buffer_ready(device, link, NV_TRUE);
}
else if (mode == NVLINK_LINKSTATE_FAULT)
{
//
// If we are here then a previous state transition caused
// the link to FAULT as there is no TL Link state requests
// that explicitly transitions a link to fault. If that is the
// case, set the DL interrupts so any errors can be handled
//
nvswitch_set_dlpl_interrupts_ls10(link);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@@ -6225,7 +6294,7 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10
{
ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
nvlink_link *link_info = nvswitch_get_link(device, link);
NvU32 lnkStateRequest, lnkStateStatus;
NvU32 lnkStateRequest, linkState;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, unhandled;
@@ -6253,26 +6322,21 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10
if (nvswitch_test_flags(pending, bit))
{
//
// Read back LINK_STATE_REQUESTS and LINK_STATE_STATUS registers
// If request == ACTIVE, LINK_STATE_STATUS == ACTIVE_PENDING, request == ERROR
// and there is a pending FAULT_UP interrupt then redo reset_and_drain since the
// last try failed
//
// Read back LINK_STATE_REQUESTS and TOP_LINK_STATE registers
// If request == ACTIVE and TOP_LINK_STATE == FAULT there is a pending
// fault on training so re-run reset_and_drain
// Mark that the defered link error mechanism as seeing a reset_and_train re-try so
// the deferred task needs to re-create itself instead of continuing with the linkstate
// checks
//
lnkStateStatus = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS);
linkState = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, NVLDL,
_NVLDL, _TOP_LINK_STATE);
lnkStateRequest = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber,
NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST);
if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) &&
!(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _STATUS, _REQUEST_SUCCESSFUL, lnkStateRequest) ||
FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _STATUS, _INIT, lnkStateRequest))&&
FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _ACTIVE_PENDING, lnkStateStatus) &&
DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1) & chip_device->deferredLinkErrors[link].fatalIntrMask.dl)
linkState == NV_NVLDL_TOP_LINK_STATE_STATE_FAULT)
{
chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE;
device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link));
@@ -6335,77 +6399,81 @@ static NvlStatus
_nvswitch_service_nvlipt_link_nonfatal_ls10
(
nvswitch_device *device,
NvU32 instance
NvU32 instance,
NvU64 intrLinkMask
)
{
NvU32 i, globalLink, bit, intrLink;
NvU32 interruptingLinks = 0;
NvU32 lnkStatusChangeLinks = 0;
NvlStatus status;
NvU64 link_enable_mask;
link_enable_mask = ((NvU64)device->regkeys.link_enable_mask2 << 32 |
(NvU64)device->regkeys.link_enable_mask);
for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i)
NvU32 i, intrLink;
NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask;
NvU64 interruptingLinks = 0;
NvU64 lnkStatusChangeLinks = 0;
NvlStatus status = NVL_SUCCESS;
NvlStatus retStatus = NVL_SUCCESS;
//
// The passed in interruptLinkMask should contain a link that is part of the
// given nvlipt instance
//
localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(instance);
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask;
if (localIntrLinkMask == 0)
{
globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i;
if ((NVBIT64(globalLink) & link_enable_mask) == 0)
NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
return -NVL_BAD_ARGS;
}
FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask)
{
if (NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT) != instance)
{
continue;
NVSWITCH_ASSERT(0);
break;
}
intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
intrLink = NVSWITCH_LINK_RD32(device, i, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
if(intrLink)
{
interruptingLinks |= NVBIT(i);
interruptingLinks |= NVBIT64(i);
}
intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS);
intrLink = NVSWITCH_LINK_RD32(device, i, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS);
if(intrLink)
{
lnkStatusChangeLinks |= NVBIT(i);
lnkStatusChangeLinks |= NVBIT64(i);
}
}
FOR_EACH_INDEX_IN_MASK_END;
if(lnkStatusChangeLinks)
{
for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i)
{
bit = NVBIT(i);
globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i;
if (nvswitch_test_flags(lnkStatusChangeLinks, bit))
{
if( _nvswitch_service_nvlipt_lnk_status_ls10(device, instance, globalLink) != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, WARN, "%s: Could not process nvlipt link status interrupt. Continuing. LinkId %d\n",
__FUNCTION__, globalLink);
}
}
}
}
if(interruptingLinks)
FOR_EACH_INDEX_IN_MASK(64, i, lnkStatusChangeLinks)
{
for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i)
if(_nvswitch_service_nvlipt_lnk_status_ls10(device, instance, i) != NVL_SUCCESS)
{
bit = NVBIT(i);
globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i;
if (nvswitch_test_flags(interruptingLinks, bit))
{
status = _nvswitch_service_nvlipt_lnk_nonfatal_ls10(device, instance, globalLink);
if (status != NVL_SUCCESS && status != -NVL_NOT_FOUND)
{
return -NVL_MORE_PROCESSING_REQUIRED;
}
}
NVSWITCH_PRINT(device, WARN, "%s: Could not process nvlipt link status interrupt. Continuing. LinkId %d\n",
__FUNCTION__, i);
}
return NVL_SUCCESS;
}
else
FOR_EACH_INDEX_IN_MASK_END;
FOR_EACH_INDEX_IN_MASK(64, i, interruptingLinks)
{
return -NVL_NOT_FOUND;
status = _nvswitch_service_nvlipt_lnk_nonfatal_ls10(device, instance, i);
if (status != NVL_SUCCESS && status != -NVL_NOT_FOUND)
{
retStatus = -NVL_MORE_PROCESSING_REQUIRED;
}
}
FOR_EACH_INDEX_IN_MASK_END;
return retStatus;
}
@@ -6431,7 +6499,7 @@ _nvswitch_service_minion_fatal_ls10
return -NVL_NOT_FOUND;
}
unhandled = pending;
unhandled = pending;
bit = DRF_NUM(_MINION, _MINION_INTR, _FALCON_STALL, 0x1);
if (nvswitch_test_flags(pending, bit))
@@ -6478,11 +6546,27 @@ _nvswitch_service_nvlw_nonfatal_ls10
)
{
NvlStatus status[3];
NvU32 reg;
NvU64 intrLinkMask = 0;
// TODO: @achaudhry invert handling so nvlipt_lnk is first
status[0] = _nvswitch_service_nvldl_nonfatal_ls10(device, instance);
status[1] = _nvswitch_service_nvltlc_nonfatal_ls10(device, instance);
status[2] = _nvswitch_service_nvlipt_link_nonfatal_ls10(device, instance);
reg = NVSWITCH_ENG_RD32_LS10(device, NVLW, instance, _NVLW, _TOP_INTR_1_STATUS);
intrLinkMask = DRF_VAL(_NVLW, _TOP_INTR_1_STATUS, _LINK, reg);
//
// Shift the mask of interrupting links from the local to the
// NVLW instance to a global mask
//
intrLinkMask = intrLinkMask << (NVSWITCH_LINKS_PER_NVLW_LS10*instance);
// If there is no pending link interrupts then there is nothing to service
if (intrLinkMask == 0)
{
return NVL_SUCCESS;
}
status[0] = _nvswitch_service_nvldl_nonfatal_ls10(device, instance, intrLinkMask);
status[1] = _nvswitch_service_nvltlc_nonfatal_ls10(device, instance, intrLinkMask);
status[2] = _nvswitch_service_nvlipt_link_nonfatal_ls10(device, instance, intrLinkMask);
if ((status[0] != NVL_SUCCESS) && (status[0] != -NVL_NOT_FOUND) &&
(status[1] != NVL_SUCCESS) && (status[1] != -NVL_NOT_FOUND) &&
@@ -6588,45 +6672,44 @@ static NvlStatus
_nvswitch_service_nvlipt_link_fatal_ls10
(
nvswitch_device *device,
NvU32 instance
NvU32 instance,
NvU64 intrLinkMask
)
{
NvU32 i, globalLink, bit, intrLink;
NvU32 interruptingLinks = 0;
NvU32 i, intrLink;
NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask;
NvlStatus status = NVL_SUCCESS;
//read in error status of current link
for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i)
//
// The passed in interruptLinkMask should contain a link that is part of the
// given nvlipt instance
//
localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(instance);
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask;
if (localIntrLinkMask == 0)
{
globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i;
intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
if(intrLink)
{
interruptingLinks |= NVBIT(i);
}
NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
return -NVL_BAD_ARGS;
}
if(interruptingLinks)
// read in error status of current link
FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask)
{
for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i)
intrLink = NVSWITCH_LINK_RD32(device, i, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
if (intrLink != 0)
{
bit = NVBIT(i);
globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i;
if (nvswitch_test_flags(interruptingLinks, bit))
if( _nvswitch_service_nvlipt_lnk_fatal_ls10(device, instance, i) != NVL_SUCCESS)
{
if( _nvswitch_service_nvlipt_lnk_fatal_ls10(device, instance, globalLink) != NVL_SUCCESS)
{
return -NVL_MORE_PROCESSING_REQUIRED;
}
status = -NVL_MORE_PROCESSING_REQUIRED;
}
}
return NVL_SUCCESS;
}
else
{
return -NVL_NOT_FOUND;
}
FOR_EACH_INDEX_IN_MASK_END;
return status;
}
static NvlStatus
@@ -6637,14 +6720,39 @@ _nvswitch_service_nvlw_fatal_ls10
)
{
NvlStatus status[6];
NvU64 intrLinkMask = 0;
NvU32 reg;
reg = NVSWITCH_ENG_RD32_LS10(device, NVLW, instance, _NVLW, _TOP_INTR_0_STATUS);
intrLinkMask = DRF_VAL(_NVLW, _TOP_INTR_0_STATUS, _LINK, reg);
//
// Shift the mask of interrupting links from the local to the
// NVLW instance to a global mask
//
intrLinkMask = intrLinkMask << (NVSWITCH_LINKS_PER_NVLW_LS10*instance);
status[0] = device->hal.nvswitch_service_minion_link(device, instance);
status[1] = _nvswitch_service_nvldl_fatal_ls10(device, instance);
status[2] = _nvswitch_service_nvltlc_fatal_ls10(device, instance);
status[3] = _nvswitch_service_minion_fatal_ls10(device, instance);
status[4] = _nvswitch_service_nvlipt_common_fatal_ls10(device, instance);
status[5] = _nvswitch_service_nvlipt_link_fatal_ls10(device, instance);
status[1] = _nvswitch_service_minion_fatal_ls10(device, instance);
status[2] = _nvswitch_service_nvlipt_common_fatal_ls10(device, instance);
//
// If there is a pending link interrupt on this nvlw instance then service
// those interrupts in the handlers below. Otherwise, mark the status's
// as success as there is nothing to service
//
if (intrLinkMask != 0)
{
status[3] = _nvswitch_service_nvldl_fatal_ls10(device, instance, intrLinkMask);
status[4] = _nvswitch_service_nvltlc_fatal_ls10(device, instance, intrLinkMask);
status[5] = _nvswitch_service_nvlipt_link_fatal_ls10(device, instance, intrLinkMask);
}
else
{
status[3] = NVL_SUCCESS;
status[4] = NVL_SUCCESS;
status[5] = NVL_SUCCESS;
}
if (status[0] != NVL_SUCCESS && status[0] != -NVL_NOT_FOUND &&
status[1] != NVL_SUCCESS && status[1] != -NVL_NOT_FOUND &&
@@ -7068,7 +7176,8 @@ nvswitch_service_nvldl_fatal_link_ls10
{
ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
NvU32 pending, bit, unhandled;
NvBool bSkipIntrClear = NV_FALSE;
NvU32 dlDeferredIntrLinkMask = 0;
NvBool bRequireResetAndDrain = NV_FALSE;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
@@ -7119,13 +7228,6 @@ nvswitch_service_nvldl_fatal_link_ls10
nvswitch_clear_flags(&unhandled, bit);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_PROTOCOL, 1);
if (nvswitch_test_flags(pending, bit))
{
@@ -7155,22 +7257,19 @@ nvswitch_service_nvldl_fatal_link_ls10
}
//
// Note: LTSSM_FAULT_UP must be the last interrupt serviced in the NVLDL
// Note: LTSSM_FAULT_{UP/DOWN} must be the last interrupt serviced in the NVLDL
// Fatal tree. The last step of handling this interrupt is going into the
// reset_and_drain flow for the given link which will shutdown and reset
// the link. The reset portion will also wipe away any link state including
// pending DL interrupts. In order to log all error before wiping that state,
// service all other interrupts before this one
//
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1);
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1);
if (nvswitch_test_flags(pending, bit))
{
chip_device->deferredLinkErrors[link].fatalIntrMask.dl |= bit;
_nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link);
dlDeferredIntrLinkMask |= bit;
nvswitch_clear_flags(&unhandled, bit);
device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link));
//
// Since reset and drain will reset the link, including clearing
@@ -7178,7 +7277,46 @@ nvswitch_service_nvldl_fatal_link_ls10
// where link clocks will not be on after reset and drain so there
// maybe PRI errors on writing to the register
//
bSkipIntrClear = NV_TRUE;
bRequireResetAndDrain = NV_TRUE;
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1);
if (nvswitch_test_flags(pending, bit))
{
dlDeferredIntrLinkMask |= bit;
nvswitch_clear_flags(&unhandled, bit);
//
// Since reset and drain will reset the link, including clearing
// pending interrupts, skip the clear write below. There are cases
// where link clocks will not be on after reset and drain so there
// maybe PRI errors on writing to the register
//
bRequireResetAndDrain = NV_TRUE;
}
if (bRequireResetAndDrain)
{
//
// If there is a link state callback enabled for this link then
// we hit a consecutive FAULT_UP error. set bResetAndDrainRetry
// so the current callback on completion can create a new
// callback to retry the link state check to account for the added
// delay caused by taking a 2nd fault and having to re-train
//
// If there is no callback enabled then set the error mask
// and create the link errors deferred task.
//
if (chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled)
{
chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE;
}
else
{
chip_device->deferredLinkErrors[link].fatalIntrMask.dl = dlDeferredIntrLinkMask;
_nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link);
}
device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link));
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@@ -7190,7 +7328,7 @@ nvswitch_service_nvldl_fatal_link_ls10
report.raw_enable ^ pending);
}
if (!bSkipIntrClear)
if (!bRequireResetAndDrain)
{
NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR, pending);
}
@@ -7244,7 +7382,7 @@ nvswitch_service_minion_link_ls10
}
unhandled = pending;
FOR_EACH_INDEX_IN_MASK(32, localLinkIdx, pending)
{
link = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + localLinkIdx;
@@ -7308,7 +7446,7 @@ nvswitch_service_minion_link_ls10
case NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR:
NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link Negotiation Config Err Interrupt", NV_FALSE);
break;
case NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT:
case NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT:
NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link BADINIT interrupt", NV_FALSE);
break;
case NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL:

20
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@@ -1230,12 +1230,29 @@ nvswitch_init_dlpl_interrupts_ls10
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR, 0xffffffff);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_SW2, 0xffffffff);
// Set the interrupt bits
nvswitch_set_dlpl_interrupts_ls10(link);
// Setup error rate thresholds
nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE);
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE);
}
void
nvswitch_set_dlpl_interrupts_ls10
(
nvlink_link *link
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
// Stall tree routes to INTR_A which is connected to NVLIPT fatal tree
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_STALL_EN,
DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_REPLAY, _DISABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_RECOVERY_SHORT, _DISABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_FAULT_UP, _ENABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_FAULT_DOWN, _ENABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_RAM, _ENABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_INTERFACE, _ENABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_SUBLINK_CHANGE, _DISABLE) |
@@ -1262,9 +1279,6 @@ nvswitch_init_dlpl_interrupts_ls10
DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_CRC_COUNTER, _ENABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_PROTOCOL, _DISABLE) |
DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _MINION_REQUEST, _DISABLE));
nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE);
nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE);
}
static NvU32

142
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -1103,11 +1103,6 @@ nvswitch_link_disable_interrupts_ls10
instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10;
localLinkIdx = link % NVSWITCH_LINKS_PER_NVLIPT_LS10;
NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT,
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x0) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x0) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x0));
NVSWITCH_ENG_WR32(device, NVLW, , instance, _NVLW, _LINK_INTR_0_MASK(localLinkIdx),
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) |
@@ -1138,31 +1133,26 @@ _nvswitch_link_reset_interrupts_ls10
NvU32 eng_instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10;
NvU32 localLinkNum = link % NVSWITCH_LINKS_PER_NVLIPT_LS10;
NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT,
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x1) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x1) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x1));
NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_0_MASK(localLinkNum),
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x1) |
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _CORRECTABLE, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x1) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x0));
NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_0_MASK(localLinkNum),
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x1) |
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _CORRECTABLE, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x1) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x0));
NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_1_MASK(localLinkNum),
DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _FATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _NONFATAL, 0x1) |
DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _CORRECTABLE, 0x1) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x1));
NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_1_MASK(localLinkNum),
DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _FATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _NONFATAL, 0x1) |
DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _CORRECTABLE, 0x1) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x1));
NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_2_MASK(localLinkNum),
DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _FATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _NONFATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _CORRECTABLE, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR0, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR1, 0x0));
NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_2_MASK(localLinkNum),
DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _FATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _NONFATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _CORRECTABLE, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR0, 0x0) |
DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR1, 0x0));
// NVLIPT_LNK
regval = NVSWITCH_LINK_RD32_LS10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _INTR_CONTROL_LINK);
@@ -1357,6 +1347,10 @@ nvswitch_reset_and_drain_links_ls10
NvU32 link_state;
NvU32 stat_data;
NvU32 link_intr_subcode;
NvBool bKeepPolling;
NvBool bIsLinkInEmergencyShutdown;
NvBool bAreDlClocksOn;
NVSWITCH_TIMEOUT timeout;
if (link_mask == 0)
{
@@ -1425,10 +1419,9 @@ nvswitch_reset_and_drain_links_ls10
if (status != NVL_SUCCESS)
{
nvswitch_destroy_link(link_info);
return status;
}
return -NVL_ERR_INVALID_STATE;
continue;
}
//
@@ -1438,10 +1431,42 @@ nvswitch_reset_and_drain_links_ls10
//
// Step 3.0 :
// Prior to starting port reset, perform unilateral shutdown on the
// LS10 side of the link, in case the links are not shutdown.
// Prior to starting port reset, ensure the links is in emergency shutdown
//
nvswitch_execute_unilateral_link_shutdown_ls10(link_info);
bIsLinkInEmergencyShutdown = NV_FALSE;
nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout);
do
{
bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
status = nvswitch_minion_get_dl_status(device, link_info->linkNumber,
NV_NVLSTAT_UC01, 0, &stat_data);
if (status != NVL_SUCCESS)
{
continue;
}
link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data);
bIsLinkInEmergencyShutdown = (link_state == LINKSTATUS_EMERGENCY_SHUTDOWN) ?
NV_TRUE:NV_FALSE;
if (bIsLinkInEmergencyShutdown == NV_TRUE)
{
break;
}
}
while(bKeepPolling);
if (bIsLinkInEmergencyShutdown == NV_FALSE)
{
NVSWITCH_PRINT(device, ERROR,
"%s: link %d failed to enter emergency shutdown\n",
__FUNCTION__, link);
continue;
}
nvswitch_corelib_clear_link_state_ls10(link_info);
//
@@ -1483,6 +1508,10 @@ nvswitch_reset_and_drain_links_ls10
{
link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data);
}
else
{
continue;
}
if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) &&
(link_intr_subcode == MINION_ALARM_BUSY))
@@ -1515,9 +1544,8 @@ nvswitch_reset_and_drain_links_ls10
if (status != NVL_SUCCESS)
{
nvswitch_destroy_link(link_info);
return status;
}
return status;
continue;
}
//
@@ -1538,12 +1566,15 @@ nvswitch_reset_and_drain_links_ls10
status = nvlink_lib_register_link(device->nvlink_device, link_info);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to register link: 0x%x with the corelib\n",
__FUNCTION__, link);
nvswitch_destroy_link(link_info);
return status;
continue;
}
//
// Launch ALI training to re-initialize and train the links
// Step 9.0: Launch ALI training to re-initialize and train the links
// nvswitch_launch_ALI_link_training(device, link_info);
//
// Request active, but don't block. FM will come back and check
@@ -1558,7 +1589,44 @@ nvswitch_reset_and_drain_links_ls10
NVSWITCH_PRINT(device, ERROR,
"%s: TL link state request to active for ALI failed for link: 0x%x\n",
__FUNCTION__, link);
continue;
}
bAreDlClocksOn = NV_FALSE;
nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout);
do
{
bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
status = nvswitch_minion_get_dl_status(device, link_info->linkNumber,
NV_NVLSTAT_UC01, 0, &stat_data);
if (status != NVL_SUCCESS)
{
continue;
}
link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data);
bAreDlClocksOn = (link_state != LINKSTATUS_INITPHASE1) ?
NV_TRUE:NV_FALSE;
if (bAreDlClocksOn == NV_TRUE)
{
break;
}
}
while(bKeepPolling);
if (!bAreDlClocksOn)
{
NVSWITCH_PRINT(device, ERROR,
"%s: link: 0x%x doesn't have the TX/RX clocks on, skipping setting DL interrupts!\n",
__FUNCTION__, link);
continue;
}
nvswitch_set_dlpl_interrupts_ls10(link_info);
}
FOR_EACH_INDEX_IN_MASK_END;

7
src/common/nvswitch/kernel/ls10/pmgr_ls10.c
View File

@@ -301,7 +301,12 @@ nvswitch_ctrl_i2c_indexed_ls10
}
return nvswitch_ctrl_i2c_indexed_lr10(device, pParams);
}
if (pParams->port == NVSWITCH_I2C_PORT_I2CA)
{
pParams->flags = FLD_SET_DRF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _100KHZ, pParams->flags);
}
if (pI2c->soeI2CSupported)
{
return soeI2CAccess_HAL(device, pParams);

8
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -480,14 +480,6 @@ nvswitch_init_soe_ls10
return status;
}
//
// Set TRACEPC to stack mode for better ucode trace
// In Vulcan CR firmware, this is set to reduced mode in the SOE's manifest
//
data = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL);
data = FLD_SET_DRF(_PRISCV, _RISCV_TRACECTL, _MODE, _STACK, data);
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, data);
// Sanity the command and message queues as a final check
if (_nvswitch_soe_send_test_cmd(device) != NV_OK)
{

85
src/common/nvswitch/kernel/ls10/therm_ls10.c
View File

@@ -460,7 +460,7 @@ nvswitch_therm_soe_callback_ls10
}
//
// nvswitch_therm_read_voltage
// nvswitch_ctrl_therm_read_voltage
//
// Temperature and voltage are only available on SKUs which have thermal and
// voltage sensors.
@@ -543,3 +543,86 @@ nvswitch_ctrl_therm_read_voltage_ls10
return NVL_SUCCESS;
}
//
// nvswitch_ctrl_therm_read_power
//
// Power is only available on SKUs which have thermal and
// voltage sensors.
//
NvlStatus
nvswitch_ctrl_therm_read_power_ls10
(
nvswitch_device *device,
NVSWITCH_GET_POWER_PARAMS *pParams
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc;
NV_STATUS status;
NvU8 flcnStatus;
RM_FLCN_CMD_SOE cmd;
RM_FLCN_MSG_SOE msg;
RM_SOE_CORE_CMD_GET_POWER *pGetPowerCmd;
NVSWITCH_TIMEOUT timeout;
if (!nvswitch_is_soe_supported(device))
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (pParams == NULL)
{
return -NVL_BAD_ARGS;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(pParams, 0, sizeof(NVSWITCH_GET_POWER_PARAMS));
nvswitch_os_memset(&cmd, 0, sizeof(RM_FLCN_CMD_SOE));
nvswitch_os_memset(&msg, 0, sizeof(RM_FLCN_MSG_SOE));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, GET_POWER);
msg.hdr.unitId = RM_SOE_UNIT_CORE;
msg.hdr.size = RM_SOE_MSG_SIZE(CORE, GET_POWER);
pGetPowerCmd = &cmd.cmd.core.getPower;
pGetPowerCmd->cmdType = RM_SOE_CORE_CMD_GET_POWER_VALUES;
cmdSeqDesc = 0;
nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
(PRM_FLCN_MSG)&msg, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to read power 0x%x\n",
__FUNCTION__, status);
return -NVL_ERR_INVALID_STATE;
}
flcnStatus = msg.msg.core.getPower.flcnStatus;
if (flcnStatus != FLCN_OK)
{
if (flcnStatus == FLCN_ERR_MORE_PROCESSING_REQUIRED)
{
return -NVL_MORE_PROCESSING_REQUIRED;
}
else
{
return -NVL_ERR_GENERIC;
}
}
pParams->vdd_w = msg.msg.core.getPower.vdd_w;
pParams->dvdd_w = msg.msg.core.getPower.dvdd_w;
pParams->hvdd_w = msg.msg.core.getPower.hvdd_w;
return NVL_SUCCESS;
}

36
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -3253,13 +3253,26 @@ _nvswitch_ctrl_get_board_part_number
NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p
)
{
if (!nvswitch_is_inforom_supported(device))
if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device))
{
NVSWITCH_PRINT(device, ERROR, "InfoROM is not supported\n");
return -NVL_ERR_NOT_SUPPORTED;
}
NVSWITCH_PRINT(device, INFO,
"%s: Skipping retrieval of board part number on FSF\n",
__FUNCTION__);
return device->hal.nvswitch_ctrl_get_board_part_number(device, p);
nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR));
return NVL_SUCCESS;
}
else
{
if (!nvswitch_is_inforom_supported(device))
{
NVSWITCH_PRINT(device, ERROR, "InfoROM is not supported\n");
return -NVL_ERR_NOT_SUPPORTED;
}
return device->hal.nvswitch_ctrl_get_board_part_number(device, p);
}
}
static NvlStatus
@@ -4732,6 +4745,16 @@ _nvswitch_ctrl_therm_read_voltage
return device->hal.nvswitch_ctrl_therm_read_voltage(device, info);
}
static NvlStatus
_nvswitch_ctrl_therm_read_power
(
nvswitch_device *device,
NVSWITCH_GET_POWER_PARAMS *info
)
{
return device->hal.nvswitch_ctrl_therm_read_power(device, info);
}
NvlStatus
nvswitch_lib_ctrl
(
@@ -5071,6 +5094,9 @@ nvswitch_lib_ctrl
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_VOLTAGE,
_nvswitch_ctrl_therm_read_voltage,
NVSWITCH_CTRL_GET_VOLTAGE_PARAMS);
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER,
_nvswitch_ctrl_therm_read_power,
NVSWITCH_GET_POWER_PARAMS);
default:
nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd);

2
src/common/nvswitch/kernel/smbpbi_nvswitch.c
View File

@@ -90,8 +90,10 @@ nvswitch_smbpbi_post_init
if (status == NVL_SUCCESS)
{
#if defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
nvswitch_lib_smbpbi_log_sxid(device, NVSWITCH_ERR_NO_ERROR,
"NVSWITCH SMBPBI server is online.");
#endif // defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
NVSWITCH_PRINT(device, INFO, "%s: SMBPBI POST INIT completed\n", __FUNCTION__);
}

24
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -3701,6 +3701,9 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
* bEnable [IN]
* - Set to NV_TRUE if the GPU partition has been activated.
* - Set to NV_FALSE if the GPU partition will be deactivated.
* fabricPartitionId [IN]
* - Set the fabric manager partition ID dring partition activation.
* - Ignored during partition deactivation.
*
* Possible status values returned are:
* NV_OK
@@ -3716,6 +3719,7 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS {
NvU32 gfid;
NvBool bEnable;
NvU32 fabricPartitionId;
} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS;
/*!
@@ -4112,4 +4116,24 @@ typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS
#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U)
typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS;
/*
* NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2
*
* This command returns NVENC software sessions information for the associate GPU.
* This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have
* embedded pointers.
*
* Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information.
*/
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xA9U)
typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS {
NvU32 sessionInfoTblEntry;
NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES];
} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS;
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */
/* _ctrl2080gpu_h_ */

63
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
View File

@@ -76,4 +76,67 @@ typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS {
NvBool bMemoryProfilingPermitted;
} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM
*
* Internal logic for PMA Stream Free
*/
#define NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM (0xb0cc0206) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U)
typedef struct NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS {
/*!
* [in] The PMA channel index associated with a given PMA stream.
*/
NvU32 pmaChannelIdx;
} NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS
*
* Get the maximum number of PMA channels
*/
#define NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS (0xb0cc0207) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS {
/*!
* [out] Max number of PMA channels
*/
NvU32 maxPmaChannels;
} NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES
*
* Internally bind PM resources.
*/
#define NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES (0xb0cc0208) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x8" */
/*!
* NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES
*
* Internally unbind PM resources.
*/
#define NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES (0xb0cc0209) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x9" */
/*!
* NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY
*
* Reserve legacy HWPM resources
*/
#define NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY (0xb0cc020a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0xaU)
typedef struct NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS {
/*!
* [in] Enable ctxsw for HWPM.
*/
NvBool ctxsw;
} NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS;
/* _ctrlb0ccinternal_h_ */