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560.35.03

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This commit is contained in:
Gaurav Juvekar
2024-08-19 10:46:21 -07:00
parent 315fd96d2d
commit ed4be64962
25 changed files with 156 additions and 51 deletions
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6
src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,4 +40,8 @@
#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NONE 0x00000000
#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001
#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION 5:5
#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_DISABLE 0x00000000
#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_ENABLE 0x00000001
#endif // NVGSP_PROXY_REG_H

1
src/nvidia/generated/g_gpu_mgr_nvoc.h
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@@ -137,6 +137,7 @@ typedef struct CONF_COMPUTE_CAPS
NvBool bAcceptClientRequest;
NvBool bMultiGpuProtectedPcieModeEnabled;
NvBool bFatalFailure;
NvBool bNvlEncryptionEnabled;
} CONF_COMPUTE_CAPS;
//

2
src/nvidia/generated/g_kernel_nvlink_nvoc.h
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@@ -311,6 +311,7 @@ struct KernelNvlink {
NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
// Data members
NvU32 gspProxyRegkeys;
struct KernelIoctrl *PRIVATE_FIELD(pKernelIoctrl)[3];
NvU32 PRIVATE_FIELD(ioctrlMask);
NvU32 PRIVATE_FIELD(ipVerNvlink);
@@ -444,6 +445,7 @@ struct KernelNvlink_PRIVATE {
NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
// Data members
NvU32 gspProxyRegkeys;
struct KernelIoctrl *pKernelIoctrl[3];
NvU32 ioctrlMask;
NvU32 ipVerNvlink;

8
src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c
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@@ -41,6 +41,8 @@
#include "published/hopper/gh100/dev_riscv_pri.h"
#include "published/hopper/gh100/dev_vm.h"
#include "gpu/nvlink/kernel_nvlink.h"
#define RISCV_BR_ADDR_ALIGNMENT (8)
const char*
@@ -409,6 +411,12 @@ kgspSetupGspFmcArgs_GH100
pGspFmcBootParams->initParams.regkeys = pCC->gspProxyRegkeys;
}
KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
if (pKernelNvlink != NULL)
{
pGspFmcBootParams->initParams.regkeys |= pKernelNvlink->gspProxyRegkeys;
}
pGspFmcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0);
pGspFmcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta);
pGspFmcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor);

33
src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c
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@@ -28,6 +28,9 @@
#include "nvrm_registry.h"
#include "os/os.h"
#include "gpu/conf_compute/conf_compute.h"
#include "gsp/gsp_proxy_reg.h"
/*!
* @brief Apply NVLink overrides from Registry
*
@@ -278,12 +281,34 @@ knvlinkApplyRegkeyOverrides_IMPL
if (NV_OK == osReadRegistryDword(pGpu,
NV_REG_STR_RM_NVLINK_ENCRYPTION, &regdata))
{
//
// Nvlink Encryption PDB PROP is set when Nvlink Encryption regkey has been enabled AND
// either we are running in MODS or CC is enabled
//
if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_ENCRYPTION, _MODE, _ENABLE, regdata))
{
pKernelNvlink->setProperty(pGpu, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
NV_PRINTF(LEVEL_INFO,
"Nvlink Encryption is enabled\n");
}
if (RMCFG_FEATURE_MODS_FEATURES)
{
pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
pKernelNvlink->gspProxyRegkeys = DRF_DEF(GSP, _PROXY_REG, _NVLINK_ENCRYPTION, _ENABLE);
NV_PRINTF(LEVEL_INFO,
"Nvlink Encryption is enabled via regkey\n");
return NV_OK;
}
else
{
ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu);
NvBool bCCFeatureEnabled = (pCC != NULL) && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED);
if (bCCFeatureEnabled)
{
pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
pKernelNvlink->gspProxyRegkeys = DRF_DEF(GSP, _PROXY_REG, _NVLINK_ENCRYPTION, _ENABLE);
NV_PRINTF(LEVEL_INFO,
"Nvlink Encryption is enabled via regkey\n");
return NV_OK;
}
}
}
}
return NV_OK;

33
src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
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@@ -189,6 +189,36 @@ _gpumgrDetermineConfComputeCapabilities
return NV_OK;
}
static NV_STATUS
_gpumgrDetermineNvlinkEncryptionCapabilities
(
OBJGPUMGR *pGpuMgr,
OBJGPU *pGpu
)
{
NvBool bNvlEncryptionEnabled = NV_FALSE;
KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
bNvlEncryptionEnabled = (pKernelNvlink != NULL) &&
pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED);
// First GPU
if (ONEBITSET(pGpuMgr->gpuAttachMask))
{
pGpuMgr->ccCaps.bNvlEncryptionEnabled = bNvlEncryptionEnabled;
}
else
{
//
// If one of the GPUs is not NVLE capable, the system as a whole
// is not NVLE capable
//
NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bNvlEncryptionEnabled ==
bNvlEncryptionEnabled, NV_ERR_INVALID_STATE);
}
return NV_OK;
}
static void
_gpumgrCacheClearMIGGpuIdInfo(NvU32 gpuId)
{
@@ -1417,6 +1447,9 @@ gpumgrAttachGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg)
// Determine conf compute params
NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineConfComputeCapabilities(pGpuMgr, pGpu));
// Determine nvlink encryption params
NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineNvlinkEncryptionCapabilities(pGpuMgr, pGpu));
if (!IS_GSP_CLIENT(pGpu))
pGpuMgr->gpuMonolithicRmMask |= NVBIT(gpuInstance);

1
src/nvidia/src/kernel/platform/cpu.c
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@@ -178,6 +178,7 @@ void RmInitCpuInfo(void)
case AARCH64_VENDOR_PART(FUJITSU, A64FX):
case AARCH64_VENDOR_PART(PHYTIUM, FT2000):
case AARCH64_VENDOR_PART(PHYTIUM, S2500):
case AARCH64_VENDOR_PART(PHYTIUM, S5000):
case AARCH64_VENDOR_PART(AMPERE, ALTRA):
case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN96XX):
case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN98XX):

1
src/nvidia/src/kernel/platform/cpu_arm_def.h
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@@ -88,6 +88,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val);
#define CP_MIDR_PRIMARY_PART_NUM_A64FX 0x001
#define CP_MIDR_PRIMARY_PART_NUM_FT2000 0x662
#define CP_MIDR_PRIMARY_PART_NUM_S2500 0x663
#define CP_MIDR_PRIMARY_PART_NUM_S5000 0x862
#define CP_MIDR_PRIMARY_PART_NUM_ALTRA 0x000
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1

1
src/nvidia/src/kernel/rmapi/client_resource.c
View File

@@ -2541,6 +2541,7 @@ _controllerParseStaticTable_v22
switch (header.version)
{
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24:
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23:
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22:
{