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535.154.05

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This commit is contained in:
Bernhard Stoeckner
2024-01-16 14:59:49 +01:00
parent 7165299dee
commit ee55481a49
25 changed files with 209 additions and 27 deletions
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20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r537_94
#define NV_BUILD_BRANCH r538_10
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r537_94
#define NV_PUBLIC_BRANCH r538_10
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_94-386"
#define NV_BUILD_CHANGELIST_NUM (33606179)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r538_10-414"
#define NV_BUILD_CHANGELIST_NUM (33694617)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_94-386"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33606179)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r538_10-414"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33694617)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r537_94-2"
#define NV_BUILD_CHANGELIST_NUM (33602158)
#define NV_BUILD_BRANCH_VERSION "r538_10-3"
#define NV_BUILD_CHANGELIST_NUM (33691963)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "537.99"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33602158)
#define NV_BUILD_NAME "538.15"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33691963)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.146.02"
#define NV_VERSION_STRING "535.154.05"
#else

1
src/common/shared/inc/nvdevid.h
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@@ -630,6 +630,7 @@ enum {
, CS_INTEL_1B81
, CS_INTEL_18DC
, CS_INTEL_7A04
, CS_AMPERE_AMPEREONE
, CS_MAX_PCIE
};

17
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@@ -89,6 +89,7 @@ CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc)
CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc)
CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc)
CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc)
CHIPSET_SETUP_FUNC(Ampere_AmpereOne_setupFunc)
CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc)
CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc)
CHIPSET_SETUP_FUNC(Nvidia_TH500_setupFunc)
@@ -265,6 +266,14 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL},
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc},
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
///////////////////////////////////////////////////////////////////////////////////////////////////
@@ -363,6 +372,14 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] =
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx
{PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian
{PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
{PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
{PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
{PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
{PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
{PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
{PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
{PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
// last element must have chipset CS_UNKNOWN (zero)
{0, 0, CS_UNKNOWN}

76
src/nvidia/generated/g_nv_name_released.h
View File

@@ -833,6 +833,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x20F6, 0x180a, 0x103c, "NVIDIA A800 40GB Active" },
{ 0x20F6, 0x180a, 0x10de, "NVIDIA A800 40GB Active" },
{ 0x20F6, 0x180a, 0x17aa, "NVIDIA A800 40GB Active" },
{ 0x20FD, 0x17f8, 0x10de, "NVIDIA AX800" },
{ 0x2182, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660 Ti" },
{ 0x2184, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660" },
{ 0x2187, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650 SUPER" },
@@ -987,6 +988,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x25FA, 0x0000, 0x0000, "NVIDIA RTX A2000 Embedded GPU" },
{ 0x25FB, 0x0000, 0x0000, "NVIDIA RTX A500 Embedded GPU" },
{ 0x2684, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090" },
{ 0x2685, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 D" },
{ 0x26B1, 0x16a1, 0x1028, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B1, 0x16a1, 0x103c, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" },
@@ -1000,6 +1002,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B5, 0x17da, 0x10de, "NVIDIA L40" },
{ 0x26B9, 0x1851, 0x10de, "NVIDIA L40S" },
{ 0x26B9, 0x18cf, 0x10de, "NVIDIA L40S" },
{ 0x26BA, 0x1957, 0x10de, "NVIDIA L20" },
{ 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
{ 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" },
@@ -1020,6 +1023,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x27B2, 0x181b, 0x103c, "NVIDIA RTX 4000 Ada Generation" },
{ 0x27B2, 0x181b, 0x10de, "NVIDIA RTX 4000 Ada Generation" },
{ 0x27B2, 0x181b, 0x17aa, "NVIDIA RTX 4000 Ada Generation" },
{ 0x27B6, 0x1933, 0x10de, "NVIDIA L2" },
{ 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" },
{ 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" },
{ 0x27BA, 0x0000, 0x0000, "NVIDIA RTX 4000 Ada Generation Laptop GPU" },
@@ -2046,6 +2050,78 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B9, 0x18af, 0x10DE, "NVIDIA L40S-16C" },
{ 0x26B9, 0x18b0, 0x10DE, "NVIDIA L40S-24C" },
{ 0x26B9, 0x18b1, 0x10DE, "NVIDIA L40S-48C" },
{ 0x26BA, 0x1909, 0x10DE, "NVIDIA L20-1B" },
{ 0x26BA, 0x190a, 0x10DE, "NVIDIA L20-2B" },
{ 0x26BA, 0x190b, 0x10DE, "NVIDIA L20-1Q" },
{ 0x26BA, 0x190c, 0x10DE, "NVIDIA L20-2Q" },
{ 0x26BA, 0x190d, 0x10DE, "NVIDIA L20-3Q" },
{ 0x26BA, 0x190e, 0x10DE, "NVIDIA L20-4Q" },
{ 0x26BA, 0x190f, 0x10DE, "NVIDIA L20-6Q" },
{ 0x26BA, 0x1910, 0x10DE, "NVIDIA L20-8Q" },
{ 0x26BA, 0x1911, 0x10DE, "NVIDIA L20-12Q" },
{ 0x26BA, 0x1912, 0x10DE, "NVIDIA L20-16Q" },
{ 0x26BA, 0x1913, 0x10DE, "NVIDIA L20-24Q" },
{ 0x26BA, 0x1914, 0x10DE, "NVIDIA L20-48Q" },
{ 0x26BA, 0x1915, 0x10DE, "NVIDIA L20-1A" },
{ 0x26BA, 0x1916, 0x10DE, "NVIDIA L20-2A" },
{ 0x26BA, 0x1917, 0x10DE, "NVIDIA L20-3A" },
{ 0x26BA, 0x1918, 0x10DE, "NVIDIA L20-4A" },
{ 0x26BA, 0x1919, 0x10DE, "NVIDIA L20-6A" },
{ 0x26BA, 0x191a, 0x10DE, "NVIDIA L20-8A" },
{ 0x26BA, 0x191b, 0x10DE, "NVIDIA L20-12A" },
{ 0x26BA, 0x191c, 0x10DE, "NVIDIA L20-16A" },
{ 0x26BA, 0x191d, 0x10DE, "NVIDIA L20-24A" },
{ 0x26BA, 0x191e, 0x10DE, "NVIDIA L20-48A" },
{ 0x26BA, 0x191f, 0x10DE, "NVIDIA GeForce RTX 3050" },
{ 0x26BA, 0x1920, 0x10DE, "NVIDIA GeForce RTX 3060" },
{ 0x26BA, 0x1921, 0x10DE, "NVIDIA L20-1" },
{ 0x26BA, 0x1922, 0x10DE, "NVIDIA L20-2" },
{ 0x26BA, 0x1923, 0x10DE, "NVIDIA L20-3" },
{ 0x26BA, 0x1924, 0x10DE, "NVIDIA L20-4" },
{ 0x26BA, 0x1925, 0x10DE, "NVIDIA L20-6" },
{ 0x26BA, 0x1926, 0x10DE, "NVIDIA L20-8" },
{ 0x26BA, 0x1927, 0x10DE, "NVIDIA L20-12" },
{ 0x26BA, 0x1928, 0x10DE, "NVIDIA L20-16" },
{ 0x26BA, 0x1929, 0x10DE, "NVIDIA L20-24" },
{ 0x26BA, 0x192a, 0x10DE, "NVIDIA L20-48" },
{ 0x26BA, 0x192b, 0x10DE, "NVIDIA L20-4C" },
{ 0x26BA, 0x192c, 0x10DE, "NVIDIA L20-6C" },
{ 0x26BA, 0x192d, 0x10DE, "NVIDIA L20-8C" },
{ 0x26BA, 0x192e, 0x10DE, "NVIDIA L20-12C" },
{ 0x26BA, 0x192f, 0x10DE, "NVIDIA L20-16C" },
{ 0x26BA, 0x1930, 0x10DE, "NVIDIA L20-24C" },
{ 0x26BA, 0x1931, 0x10DE, "NVIDIA L20-48C" },
{ 0x27B6, 0x1938, 0x10DE, "NVIDIA L2-1B" },
{ 0x27B6, 0x1939, 0x10DE, "NVIDIA L2-2B" },
{ 0x27B6, 0x193a, 0x10DE, "NVIDIA L2-1Q" },
{ 0x27B6, 0x193b, 0x10DE, "NVIDIA L2-2Q" },
{ 0x27B6, 0x193c, 0x10DE, "NVIDIA L2-3Q" },
{ 0x27B6, 0x193d, 0x10DE, "NVIDIA L2-4Q" },
{ 0x27B6, 0x193e, 0x10DE, "NVIDIA L2-6Q" },
{ 0x27B6, 0x193f, 0x10DE, "NVIDIA L2-8Q" },
{ 0x27B6, 0x1940, 0x10DE, "NVIDIA L2-12Q" },
{ 0x27B6, 0x1941, 0x10DE, "NVIDIA L2-24Q" },
{ 0x27B6, 0x1942, 0x10DE, "NVIDIA L2-1A" },
{ 0x27B6, 0x1943, 0x10DE, "NVIDIA L2-2A" },
{ 0x27B6, 0x1944, 0x10DE, "NVIDIA L2-3A" },
{ 0x27B6, 0x1945, 0x10DE, "NVIDIA L2-4A" },
{ 0x27B6, 0x1946, 0x10DE, "NVIDIA L2-6A" },
{ 0x27B6, 0x1947, 0x10DE, "NVIDIA L2-8A" },
{ 0x27B6, 0x1948, 0x10DE, "NVIDIA L2-12A" },
{ 0x27B6, 0x1949, 0x10DE, "NVIDIA L2-24A" },
{ 0x27B6, 0x194a, 0x10DE, "NVIDIA L2-1" },
{ 0x27B6, 0x194b, 0x10DE, "NVIDIA L2-2" },
{ 0x27B6, 0x194c, 0x10DE, "NVIDIA L2-3" },
{ 0x27B6, 0x194d, 0x10DE, "NVIDIA L2-4" },
{ 0x27B6, 0x194e, 0x10DE, "NVIDIA L2-6" },
{ 0x27B6, 0x194f, 0x10DE, "NVIDIA L2-8" },
{ 0x27B6, 0x1950, 0x10DE, "NVIDIA L2-12" },
{ 0x27B6, 0x1951, 0x10DE, "NVIDIA L2-24" },
{ 0x27B6, 0x1952, 0x10DE, "NVIDIA L2-4C" },
{ 0x27B6, 0x1953, 0x10DE, "NVIDIA L2-6C" },
{ 0x27B6, 0x1954, 0x10DE, "NVIDIA L2-8C" },
{ 0x27B6, 0x1955, 0x10DE, "NVIDIA L2-12C" },
{ 0x27B6, 0x1956, 0x10DE, "NVIDIA L2-24C" },
{ 0x27B8, 0x172f, 0x10DE, "NVIDIA L4-1B" },
{ 0x27B8, 0x1730, 0x10DE, "NVIDIA L4-2B" },
{ 0x27B8, 0x1731, 0x10DE, "NVIDIA L4-1Q" },

3
src/nvidia/inc/kernel/rmapi/rmapi_utils.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,6 +25,7 @@
#include "rmapi/rmapi.h"
//
// Alloc a client, device and subdevice handle for a gpu
//

10
src/nvidia/interface/nvrm_registry.h
View File

@@ -1919,4 +1919,14 @@
#define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_DISABLE 0
#define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE 1
//
// Type DWORD
// This regkey force-disables write-combine iomap allocations, used for chipsets where
// write-combine is broken.
//
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC "RmForceDisableIomapWC"
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES 0x00000001
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 0x00000000
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_DEFAULT NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO
#endif // NVRM_REGISTRY_H

8
src/nvidia/src/kernel/platform/chipset/chipset.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -82,6 +82,12 @@ clInitPropertiesFromRegistry_IMPL(OBJGPU *pGpu, OBJCL *pCl)
}
}
if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC, &data32) == NV_OK)
&& (data32 == NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES))
{
pCl->setProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC, NV_TRUE);
}
pOS->osQADbgRegistryInit(pOS);
}

12
src/nvidia/src/kernel/platform/chipset/chipset_info.c
View File

@@ -1301,6 +1301,18 @@ Arm_NeoverseN1_setupFunc
return NV_OK;
}
// Ampere AmpereOne Setup Function
static NV_STATUS
Ampere_AmpereOne_setupFunc
(
OBJCL *pCl
)
{
// TODO Need to check if any more PDB properties should be set
pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE);
return NV_OK;
}
void
csGetInfoStrings
(

1
src/nvidia/src/kernel/platform/cpu.c
View File

@@ -186,6 +186,7 @@ void RmInitCpuInfo(void)
break;
case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2):
case AARCH64_VENDOR_PART(ARM, NEOVERSE_V2):
case AARCH64_VENDOR_PART(AMPERE_2, AMPEREONE):
pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC;
break;
default:

2
src/nvidia/src/kernel/platform/cpu_arm_def.h
View File

@@ -57,6 +57,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val);
#define CP_MIDR_IMPLEMENTER_FUJITSU 0x46
#define CP_MIDR_IMPLEMENTER_PHYTIUM 0x70
#define CP_MIDR_IMPLEMENTER_AMPERE 0x81
#define CP_MIDR_IMPLEMENTER_AMPERE_2 0XC0
#define CP_CSSELR_DATA_CACHE 0
#define CP_CSSELR_INSTRUCTION_CACHE 1
@@ -91,6 +92,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val);
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1
#define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49
#define CP_MIDR_PRIMARY_PART_NUM_AMPEREONE 0xac3
// Cache Size Identification Register
#define CP_CCSIDR "ccsidr_el1"

8
src/nvidia/src/kernel/rmapi/control.c
View File

@@ -274,7 +274,9 @@ serverControlApiCopyIn
rmStatus = embeddedParamCopyIn(pEmbeddedParamCopies, pRmCtrlParams);
if (rmStatus != NV_OK)
{
return rmStatus;
}
pCookie->bFreeEmbeddedCopy = NV_TRUE;
return NV_OK;
@@ -487,8 +489,9 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams
}
// error check parameters
if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) ||
((paramsSize == 0) && (pUserParams != (NvP64) 0)))
if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) ||
((paramsSize == 0) && (pUserParams != (NvP64) 0))
)
{
NV_PRINTF(LEVEL_WARNING, "bad params: ptr " NvP64_fmt " size: 0x%x\n",
pUserParams, paramsSize);
@@ -519,6 +522,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams
}
getCtrlInfoStatus = rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight);
if (getCtrlInfoStatus == NV_OK)
{
//

2
src/nvidia/src/kernel/rmapi/rmapi_cache.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/nvidia/src/kernel/rmapi/rmapi_utils.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a