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This commit is contained in:
Gaurav Juvekar
2024-05-08 07:57:54 -07:00
parent c042c7903d
commit f4bdce9a0a
22 changed files with 141 additions and 28 deletions
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3
src/nvidia/arch/nvalloc/common/inc/nvcst.h
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@@ -247,7 +247,8 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD, "Mellanox BlueField", Mellanox_BlueField_setupFunc},
{PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2", NULL},
{PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL},
{PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3", Mellanox_BlueField3_setupFunc},
{PCI_VENDOR_ID_MELLANOX, 0xA2DA, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3 Crypto enabled", Mellanox_BlueField3_setupFunc},
{PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3 Crypto disabled", Mellanox_BlueField3_setupFunc},
{PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc},
{PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL},

1
src/nvidia/generated/g_nv_name_released.h
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@@ -797,6 +797,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1FF0, 0x1612, 0x17aa, "NVIDIA T1000 8GB" },
{ 0x1FF2, 0x1613, 0x1028, "NVIDIA T400 4GB" },
{ 0x1FF2, 0x1613, 0x103c, "NVIDIA T400 4GB" },
{ 0x1FF2, 0x18ff, 0x103c, "NVIDIA T400E" },
{ 0x1FF2, 0x8a80, 0x103c, "NVIDIA T400 4GB" },
{ 0x1FF2, 0x1613, 0x10de, "NVIDIA T400 4GB" },
{ 0x1FF2, 0x1613, 0x17aa, "NVIDIA T400 4GB" },

2
src/nvidia/generated/g_profiler_v2_nvoc.h
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@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

8
src/nvidia/interface/nvrm_registry.h
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@@ -1957,5 +1957,13 @@
#define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ON_RETRY 0x00000000
#define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ALWAYS 0x00000001
//
// Type: Dword
// This regkey overrides the state of the GR scrubber channel and determines
// whether it should be created or not.
//
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL "RmForceGrScrubberChannel"
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_DISABLE 0x00000000
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_ENABLE 0x00000001
#endif // NVRM_REGISTRY_H

2
src/nvidia/src/kernel/gpu/device.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

6
src/nvidia/src/kernel/gpu/fifo/kernel_channel.c
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@@ -822,7 +822,9 @@ kchannelConstruct_IMPL
cleanup);
// Set up pNotifyActions
_kchannelSetupNotifyActions(pKernelChannel, pResourceRef->externalClassId);
NV_ASSERT_OK_OR_GOTO(status,
_kchannelSetupNotifyActions(pKernelChannel, pResourceRef->externalClassId),
cleanup);
bNotifyActionsSetup = NV_TRUE;
// Initialize the userd length
@@ -4494,7 +4496,7 @@ kchannelCtrlRotateSecureChannelIv_PHYSICAL
)
{
NV_STATUS status;
NV_PRINTF(LEVEL_INFO, "Rotating IV in GSP-RM.\n");
// CPU-side encrypt IV corresponds to GPU-side decrypt IV.

28
src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c
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@@ -23,11 +23,37 @@
#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED
#include "kernel/gpu/gr/kernel_graphics.h"
#include "gpu_mgr/gpu_mgr.h"
#include "kernel/gpu/mem_mgr/mem_mgr.h"
#include "kernel/gpu/gr/kernel_graphics_manager.h"
#include "kernel/gpu/gr/kernel_graphics.h"
#include "kernel/gpu/device/device.h"
#include "kernel/gpu/subdevice/subdevice.h"
#include "kernel/rmapi/rmapi_utils.h"
#include "kernel/core/locks.h"
#include "kernel/gpu/mem_sys/kern_mem_sys.h"
#include "kernel/mem_mgr/gpu_vaspace.h"
#include "kernel/gpu/mem_mgr/mem_mgr.h"
#include "virtualization/hypervisor/hypervisor.h"
#include "kernel/gpu/mem_mgr/heap.h"
#include "gpu/mem_mgr/virt_mem_allocator.h"
#include "gpu/mmu/kern_gmmu.h"
#include "platform/sli/sli.h"
#include "rmapi/rs_utils.h"
#include "rmapi/client.h"
#include "nvrm_registry.h"
#include "gpu/mem_mgr/heap.h"
#include "ctrl/ctrl0080/ctrl0080fifo.h"
#include "class/cla06f.h"
#include "class/cl90f1.h" // FERMI_VASPACE_A
#include "class/cl003e.h" // NV01_MEMORY_SYSTEM
#include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL
#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER
#include "class/clc36f.h" // VOLTA_CHANNEL_GPFIFO_A
#include "class/clc46f.h" // TURING_CHANNEL_GPFIFO_A
/*!
* @brief Allocate common local/global buffers that are required by the graphics context
*

8
src/nvidia/src/kernel/gpu/gr/kernel_graphics.c
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@@ -95,6 +95,12 @@ static NV_STATUS _kgraphicsMapGlobalCtxBuffer(OBJGPU *pGpu, KernelGraphics *pKer
KernelGraphicsContext *, GR_GLOBALCTX_BUFFER, NvBool bIsReadOnly);
static NV_STATUS _kgraphicsPostSchedulingEnableHandler(OBJGPU *, void *);
static void
_kgraphicsInitRegistryOverrides(OBJGPU *pGpu, KernelGraphics *pKernelGraphics)
{
return;
}
NV_STATUS
kgraphicsConstructEngine_IMPL
(
@@ -213,6 +219,7 @@ kgraphicsConstructEngine_IMPL
NV_ASSERT_OK_OR_RETURN(fecsCtxswLoggingInit(pGpu, pKernelGraphics, &pKernelGraphics->pFecsTraceInfo));
_kgraphicsInitRegistryOverrides(pGpu, pKernelGraphics);
return NV_OK;
}
@@ -349,6 +356,7 @@ kgraphicsStatePreUnload_IMPL
NvU32 flags
)
{
fecsBufferUnmap(pGpu, pKernelGraphics);
// Release global buffers used as part of the gr context, when not in S/R

3
src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c
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@@ -326,7 +326,8 @@ vaspaceapiConstruct_IMPL
memmgrIsPmaInitialized(pMemoryManager) &&
memmgrAreClientPageTablesPmaManaged(pMemoryManager) &&
!(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED) &&
!(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_FLA))
!(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_FLA) &&
!(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED))
{
flags |= VASPACE_FLAGS_PTETABLE_PMA_MANAGED;
}

5
src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -9585,8 +9585,7 @@ void nvGpuOpsPagingChannelsUnmap(struct gpuAddressSpace *srcVaSpace,
return;
}
status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_NONE, hClient, NULL, 2,
device->deviceInstance, srcVaSpace->device->deviceInstance, &acquiredLocks);
status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_NONE, hClient, NULL, &acquiredLocks);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR,