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575.64

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This commit is contained in:
Maneet Singh
2025-06-16 19:28:19 -07:00
parent 30e15d79de
commit fade1f7b20
35 changed files with 50249 additions and 49935 deletions
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20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r576_41
#define NV_BUILD_BRANCH r575_00
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r576_41
#define NV_PUBLIC_BRANCH r575_00
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r576_41-183"
#define NV_BUILD_CHANGELIST_NUM (36029171)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r575_00-212"
#define NV_BUILD_CHANGELIST_NUM (36105353)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r575/r576_41-183"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36029171)
#define NV_BUILD_NAME "rel/gpu_drv/r575/r575_00-212"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36105353)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r576_41-8"
#define NV_BUILD_CHANGELIST_NUM (36020778)
#define NV_BUILD_BRANCH_VERSION "r575_00-160"
#define NV_BUILD_CHANGELIST_NUM (36104828)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "576.60"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36020778)
#define NV_BUILD_NAME "576.76"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36104828)
#define NV_BUILD_BRANCH_BASE_VERSION R575
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "575.57.08"
#define NV_VERSION_STRING "575.64"
#else

104
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -2537,6 +2537,9 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS {
NvU8 ee_ls;
NvU8 ee;
NvU8 ase;
NvBool ee_nmxas;
NvU8 nmxas_e;
NvU8 ps_e_ext;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS;
@@ -2599,6 +2602,14 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
NvU16 fec_override_admin_800g_8x;
NvU16 fec_override_admin_100g_1x;
NvU16 fec_override_admin_200g_2x;
NvBool tx_crc_plr_vld;
NvBool tx_crc_plr_override_to_default;
NvBool plr_reject_mode_override_to_default;
NvU16 nvlink_fec_override_admin_nvl_phy6;
NvU16 fec_override_admin_800g_4x;
NvU16 fec_override_admin_1600g_8x;
NvU16 fec_override_admin_200g_1x;
NvU16 fec_override_admin_400g_2x;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC (0x20803055U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID" */
@@ -2618,6 +2629,12 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS {
NvU16 l1_hw_active_time;
NvU16 l1_hw_inactive_time;
NvU8 qem[8];
NvBool l0_rx_cap_adv;
NvBool l0_rx_req_en;
NvBool l0_tx_cap_adv;
NvBool l0_tx_req_en;
NvBool l0_all_queues_are_import;
NvU16 l0_hw_inactive_time;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM (0x20803056U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID" */
@@ -2699,6 +2716,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS {
NvU8 local_port;
NvBool m_lane_m;
NvBool rxtx;
NvBool mod_lab_map;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT (0x20803065U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID" */
@@ -2726,6 +2744,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS {
NvU8 local_port;
NvU8 page_select;
NvU8 module_info_ext;
NvU8 module_ind_type;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT (0x20803068U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID" */
@@ -2795,6 +2814,9 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS {
NvU8 swid;
NvU8 plane_ind;
NvU8 phy_status_admin;
NvBool ee_nmxas;
NvU8 nmxas_e;
NvU8 ps_e_ext;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR (0x2080306cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID" */
@@ -2827,6 +2849,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS {
NvU8 pnat;
NvU8 local_port;
NvU8 lp_msb;
NvBool conf_mod;
} NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID (0x2080306eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID" */
@@ -2932,6 +2955,8 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS {
NvU8 lp_msb;
NvU8 local_port;
NvU16 lb_en;
NvBool lb_cap_mode_idx;
NvBool lb_link_mode_idx;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS (0x20803074U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID" */
@@ -3040,6 +3065,8 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS {
NvU8 critical_inactive_time;
NvU8 critical_active_time;
NvBool cc;
NvBool l0_all_queues_are_import;
NvBool ge;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR (0x2080307dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID" */
@@ -3422,6 +3449,81 @@ typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS {
NvBool bEncryptEnSet;
} NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTASV2 (0x20803093U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID (0x93U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvU8 xdr_lt_c2c_en;
NvU8 xdr_lt_c2m_en;
NvU8 kr_ext_req;
NvU8 lt_ext_neg_type;
NvU8 lt_ext_timeout_admin;
NvU8 prbs_type_admin;
NvBool ber_cnt_mlsd_dis;
NvU8 num_of_iter_admin;
NvU16 iter_time_admin;
NvU8 ber_target_coef_admin;
NvU8 ber_target_magnitude_admin;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLLM_5NM (0x20803094U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS_MESSAGE_ID (0x94U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool c_db;
NvBool br_lanes;
NvU8 port_type;
NvU8 lane;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvBool peq_cap;
NvU16 peq_interval_period;
} NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS (0x20803090U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID (0x90U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS {
NV2080_CTRL_NVLINK_PRM_DATA prm;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRM (0x20803091U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID (0x91U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 ovrd_no_neg_bhvr;
NvU8 plane_ind;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvU8 no_neg_bhvr;
NvU8 wd_logic_re_lock_res;
NvU8 module_datapath_full_toggle;
NvU8 module_tx_disable;
NvU8 host_serdes_feq;
NvU8 host_logic_re_lock;
NvU16 link_down_timeout;
NvU8 draining_timeout;
NvU8 wd_module_full_toggle;
NvU8 wd_module_tx_disable;
NvU8 wd_host_serdes_feq;
NvU8 wd_host_logic_re_lock;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS;
/* _ctrl2080nvlink_h_ */

19
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -615,25 +615,6 @@ ENTRY(0x2238, 0x16B7, 0x10de, "NVIDIA A10M-5C"),
ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),

8
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -17,7 +17,6 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B7, 0x1804, 0x20B7, 0x1532 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x230E, 0x20DF, 0x230E, 0x20DF },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -120,13 +119,6 @@ static const struct {
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1499}, // NVIDIA H20L-1-15CME
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1500}, // NVIDIA H20L-1-15C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1501}, // NVIDIA H20L-1-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1502}, // NVIDIA H20L-2-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1503}, // NVIDIA H20L-3-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1504}, // NVIDIA H20L-4-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1505}, // NVIDIA H20L-7-120C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C