575.64

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 575.57.08.
+version 575.64.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-575.57.08 driver release.  This can be achieved by installing
+575.64 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -185,7 +185,7 @@ table below).
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/575.57.08/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/575.64/README/kernel_open.html
 
 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.
@@ -968,14 +968,28 @@ Subsystem Device ID.
 | NVIDIA GeForce RTX 5070 Ti                              | 2C05           |
 | NVIDIA GeForce RTX 5090 Laptop GPU                      | 2C18           |
 | NVIDIA GeForce RTX 5080 Laptop GPU                      | 2C19           |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 1028 2051 |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 103C 2051 |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 10DE 2051 |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 17AA 2051 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 1028 2052 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 103C 2052 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 10DE 2052 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 17AA 2052 |
+| NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU     | 2C38           |
+| NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU     | 2C39           |
 | NVIDIA GeForce RTX 5090 Laptop GPU                      | 2C58           |
 | NVIDIA GeForce RTX 5080 Laptop GPU                      | 2C59           |
 | NVIDIA GeForce RTX 5060 Ti                              | 2D04           |
 | NVIDIA GeForce RTX 5060                                 | 2D05           |
 | NVIDIA GeForce RTX 5070 Laptop GPU                      | 2D18           |
 | NVIDIA GeForce RTX 5060 Laptop GPU                      | 2D19           |
+| NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU     | 2D39           |
 | NVIDIA GeForce RTX 5070 Laptop GPU                      | 2D58           |
 | NVIDIA GeForce RTX 5060 Laptop GPU                      | 2D59           |
+| NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU     | 2DB8           |
+| NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU      | 2DB9           |
 | NVIDIA GeForce RTX 5070                                 | 2F04           |
 | NVIDIA GeForce RTX 5070 Ti Laptop GPU                   | 2F18           |
+| NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU     | 2F38           |
 | NVIDIA GeForce RTX 5070 Ti Laptop GPU                   | 2F58           |

kernel-open/Kbuild

@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
 ccflags-y += -I$(src)
 ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
-ccflags-y += -DNV_VERSION_STRING=\"575.57.08\"
+ccflags-y += -DNV_VERSION_STRING=\"575.64\"
 
 ifneq ($(SYSSRCHOST1X),)
  ccflags-y += -I$(SYSSRCHOST1X)

kernel-open/common/inc/nv-mm.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -297,9 +297,21 @@ static inline struct rw_semaphore *nv_mmap_get_lock(struct mm_struct *mm)
 #endif
 }
 
+#define NV_CAN_CALL_VMA_START_WRITE 1
+
+#if !NV_CAN_CALL_VMA_START_WRITE
+/*
+ * Commit 45ad9f5290dc updated vma_start_write() to call __vma_start_write().
+ */
+void nv_vma_start_write(struct vm_area_struct *);
+#endif
+
 static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
 {
-#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
+#if !NV_CAN_CALL_VMA_START_WRITE
+    nv_vma_start_write(vma);
+    ACCESS_PRIVATE(vma, __vm_flags) |= flags;
+#elif defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
     vm_flags_set(vma, flags);
 #else
     vma->vm_flags |= flags;
@@ -308,7 +320,10 @@ static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
 
 static inline void nv_vm_flags_clear(struct vm_area_struct *vma, vm_flags_t flags)
 {
-#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
+#if !NV_CAN_CALL_VMA_START_WRITE
+    nv_vma_start_write(vma);
+    ACCESS_PRIVATE(vma, __vm_flags) &= ~flags;
+#elif defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
     vm_flags_clear(vma, flags);
 #else
     vma->vm_flags &= ~flags;

kernel-open/conftest.sh

@@ -7604,7 +7604,7 @@ compile_test() {
             CODE="
             #include <linux/mmzone.h>
             int conftest_page_pgmap(void) {
-                return page_pgmap(NULL);
+                return page_pgmap();
             }"
 
             compile_check_conftest "$CODE" "NV_PAGE_PGMAP_PRESENT" "" "functions"

kernel-open/nvidia-drm/nvidia-drm-sources.mk

@@ -38,6 +38,7 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available
 NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_fd_to_handle
 NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_handle_to_fd
 NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync
+NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl___vma_start_write
 
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group

kernel-open/nvidia-uvm/uvm_ats_faults.c

@@ -757,6 +757,20 @@ NV_STATUS uvm_ats_service_access_counters(uvm_gpu_va_space_t *gpu_va_space,
                          &ats_context->access_counters.accessed_mask,
                          &ats_context->prefetch_state.residency_mask);
 
+    // Pretend that pages that are already resident at the destination GPU were
+    // migrated now. This makes sure that the access counter is cleared even if
+    // the accessed pages, were already resident on the target.
+    // TODO: Bug 5296998: [uvm][ats] Not clearing stale access counter
+    //                     notifications can lead to missed migrations
+    // The same problem of stale notification exists for migration to other
+    // locations than local vidmem. However, stale notifications to data
+    // migrated to another remote location are identical to those triggered
+    // by accessing memory that cannot or should not be migrated.
+    if (uvm_id_equal(ats_context->residency_id, gpu_va_space->gpu->id)) {
+        uvm_page_mask_copy(&ats_context->access_counters.migrated_mask,
+                           &ats_context->prefetch_state.residency_mask);
+    }
+
     for_each_va_block_subregion_in_mask(subregion, &ats_context->access_counters.accessed_mask, region) {
         NV_STATUS status;
         NvU64 start = base + (subregion.first * PAGE_SIZE);
@@ -769,7 +783,7 @@ NV_STATUS uvm_ats_service_access_counters(uvm_gpu_va_space_t *gpu_va_space,
 
         status = service_ats_requests(gpu_va_space, vma, start, length, access_type, service_type, ats_context);
 
-        // clear access counters if pages were migrated or migration needs to
+        // Clear access counters if pages were migrated or migration needs to
         // be retried
         if (status == NV_OK || status == NV_ERR_BUSY_RETRY)
             uvm_page_mask_region_fill(migrated_mask, subregion);

kernel-open/nvidia/nv-mmap.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -847,3 +847,75 @@ void NV_API_CALL nv_set_safe_to_mmap_locked(
 
     nvl->safe_to_mmap = safe_to_mmap;
 }
+
+#if !NV_CAN_CALL_VMA_START_WRITE
+static NvBool nv_vma_enter_locked(struct vm_area_struct *vma, NvBool detaching)
+{
+    NvU32 tgt_refcnt = VMA_LOCK_OFFSET;
+    NvBool interrupted = NV_FALSE;
+    if (!detaching)
+    {
+        tgt_refcnt++;
+    }
+    if (!refcount_add_not_zero(VMA_LOCK_OFFSET, &vma->vm_refcnt))
+    {
+        return NV_FALSE;
+    }
+
+    rwsem_acquire(&vma->vmlock_dep_map, 0, 0, _RET_IP_);
+    prepare_to_rcuwait(&vma->vm_mm->vma_writer_wait);
+
+    for (;;)
+    {
+        set_current_state(TASK_UNINTERRUPTIBLE);
+        if (refcount_read(&vma->vm_refcnt) == tgt_refcnt)
+            break;
+
+        if (signal_pending_state(TASK_UNINTERRUPTIBLE, current))
+        {
+            interrupted = NV_TRUE;
+            break;
+        }
+
+        schedule();
+    }
+
+    // This is an open-coded version of finish_rcuwait().
+    rcu_assign_pointer(vma->vm_mm->vma_writer_wait.task, NULL);
+    __set_current_state(TASK_RUNNING);
+
+    if (interrupted)
+    {
+        // Clean up on error: release refcount and dep_map
+        refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
+        rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
+        return NV_FALSE;
+    }
+
+    lock_acquired(&vma->vmlock_dep_map, _RET_IP_);
+    return NV_TRUE;
+}
+
+/*
+ * Helper function to handle VMA locking and refcount management.
+ */
+void nv_vma_start_write(struct vm_area_struct *vma)
+{
+    NvU32 mm_lock_seq;
+    NvBool locked;
+    if (__is_vma_write_locked(vma, &mm_lock_seq))
+        return;
+
+    locked = nv_vma_enter_locked(vma, NV_FALSE);
+
+    WRITE_ONCE(vma->vm_lock_seq, mm_lock_seq);
+    if (locked)
+    {
+        NvBool detached;
+        detached = refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
+        rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
+        WARN_ON_ONCE(detached);
+    }
+}
+EXPORT_SYMBOL(nv_vma_start_write);
+#endif // !NV_CAN_CALL_VMA_START_WRITE

kernel-open/nvidia/nvidia.Kbuild

@@ -240,6 +240,7 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl___platform_driver_regis
 NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present___platform_driver_register
 NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_hrtimer_setup
 NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync
+NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl___vma_start_write
 
 NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops
 NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops

src/common/inc/nvBldVer.h

@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r576_41
+    #define NV_BUILD_BRANCH             r575_00
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r576_41
+    #define NV_PUBLIC_BRANCH             r575_00
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r575/r576_41-183"
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r575/r575_00-212"
-#define NV_BUILD_CHANGELIST_NUM         (36029171)
+#define NV_BUILD_CHANGELIST_NUM         (36105353)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r575/r576_41-183"
+#define NV_BUILD_NAME                   "rel/gpu_drv/r575/r575_00-212"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36029171)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36105353)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r576_41-8"
+#define NV_BUILD_BRANCH_VERSION         "r575_00-160"
-#define NV_BUILD_CHANGELIST_NUM         (36020778)
+#define NV_BUILD_CHANGELIST_NUM         (36104828)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "576.60"
+#define NV_BUILD_NAME                   "576.76"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36020778)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36104828)
 #define NV_BUILD_BRANCH_BASE_VERSION    R575
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "575.57.08"
+#define NV_VERSION_STRING               "575.64"
 
 #else
 

src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -2537,6 +2537,9 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS {
     NvU8                        ee_ls;
     NvU8                        ee;
     NvU8                        ase;
+    NvBool                      ee_nmxas;
+    NvU8                        nmxas_e;
+    NvU8                        ps_e_ext;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS;
 
 
@@ -2599,6 +2602,14 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
     NvU16                       fec_override_admin_800g_8x;
     NvU16                       fec_override_admin_100g_1x;
     NvU16                       fec_override_admin_200g_2x;
+    NvBool                      tx_crc_plr_vld;
+    NvBool                      tx_crc_plr_override_to_default;
+    NvBool                      plr_reject_mode_override_to_default;
+    NvU16                       nvlink_fec_override_admin_nvl_phy6;
+    NvU16                       fec_override_admin_800g_4x;
+    NvU16                       fec_override_admin_1600g_8x;
+    NvU16                       fec_override_admin_200g_1x;
+    NvU16                       fec_override_admin_400g_2x;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC (0x20803055U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID" */
@@ -2618,6 +2629,12 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS {
     NvU16                       l1_hw_active_time;
     NvU16                       l1_hw_inactive_time;
     NvU8                        qem[8];
+    NvBool                      l0_rx_cap_adv;
+    NvBool                      l0_rx_req_en;
+    NvBool                      l0_tx_cap_adv;
+    NvBool                      l0_tx_req_en;
+    NvBool                      l0_all_queues_are_import;
+    NvU16                       l0_hw_inactive_time;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM (0x20803056U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID" */
@@ -2699,6 +2716,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS {
     NvU8                        local_port;
     NvBool                      m_lane_m;
     NvBool                      rxtx;
+    NvBool                      mod_lab_map;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT (0x20803065U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID" */
@@ -2726,6 +2744,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS {
     NvU8                        local_port;
     NvU8                        page_select;
     NvU8                        module_info_ext;
+    NvU8                        module_ind_type;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT (0x20803068U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID" */
@@ -2795,6 +2814,9 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS {
     NvU8                        swid;
     NvU8                        plane_ind;
     NvU8                        phy_status_admin;
+    NvBool                      ee_nmxas;
+    NvU8                        nmxas_e;
+    NvU8                        ps_e_ext;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR (0x2080306cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID" */
@@ -2827,6 +2849,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS {
     NvU8                        pnat;
     NvU8                        local_port;
     NvU8                        lp_msb;
+    NvBool                      conf_mod;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID (0x2080306eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID" */
@@ -2932,6 +2955,8 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS {
     NvU8                        lp_msb;
     NvU8                        local_port;
     NvU16                       lb_en;
+    NvBool                      lb_cap_mode_idx;
+    NvBool                      lb_link_mode_idx;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS (0x20803074U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID" */
@@ -3040,6 +3065,8 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS {
     NvU8                        critical_inactive_time;
     NvU8                        critical_active_time;
     NvBool                      cc;
+    NvBool                      l0_all_queues_are_import;
+    NvBool                      ge;
 } NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS;
 
 #define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR (0x2080307dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID" */
@@ -3422,6 +3449,81 @@ typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS {
     NvBool bEncryptEnSet;
 } NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS;
 
+#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTASV2 (0x20803093U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID (0x93U)
+
+typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS {
+    NvBool                      bWrite;
+    NV2080_CTRL_NVLINK_PRM_DATA prm;
+    NvU8                        lp_msb;
+    NvU8                        pnat;
+    NvU8                        local_port;
+    NvU8                        xdr_lt_c2c_en;
+    NvU8                        xdr_lt_c2m_en;
+    NvU8                        kr_ext_req;
+    NvU8                        lt_ext_neg_type;
+    NvU8                        lt_ext_timeout_admin;
+    NvU8                        prbs_type_admin;
+    NvBool                      ber_cnt_mlsd_dis;
+    NvU8                        num_of_iter_admin;
+    NvU16                       iter_time_admin;
+    NvU8                        ber_target_coef_admin;
+    NvU8                        ber_target_magnitude_admin;
+} NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLLM_5NM (0x20803094U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS_MESSAGE_ID (0x94U)
+
+typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS {
+    NvBool                      bWrite;
+    NV2080_CTRL_NVLINK_PRM_DATA prm;
+    NvBool                      c_db;
+    NvBool                      br_lanes;
+    NvU8                        port_type;
+    NvU8                        lane;
+    NvU8                        lp_msb;
+    NvU8                        pnat;
+    NvU8                        local_port;
+    NvBool                      peq_cap;
+    NvU16                       peq_interval_period;
+} NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS (0x20803090U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID (0x90U)
+
+typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS {
+    NV2080_CTRL_NVLINK_PRM_DATA prm;
+} NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRM (0x20803091U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID (0x91U)
+
+typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS {
+    NvBool                      bWrite;
+    NV2080_CTRL_NVLINK_PRM_DATA prm;
+    NvU8                        ovrd_no_neg_bhvr;
+    NvU8                        plane_ind;
+    NvU8                        lp_msb;
+    NvU8                        pnat;
+    NvU8                        local_port;
+    NvU8                        no_neg_bhvr;
+    NvU8                        wd_logic_re_lock_res;
+    NvU8                        module_datapath_full_toggle;
+    NvU8                        module_tx_disable;
+    NvU8                        host_serdes_feq;
+    NvU8                        host_logic_re_lock;
+    NvU16                       link_down_timeout;
+    NvU8                        draining_timeout;
+    NvU8                        wd_module_full_toggle;
+    NvU8                        wd_module_tx_disable;
+    NvU8                        wd_host_serdes_feq;
+    NvU8                        wd_host_logic_re_lock;
+} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS;
+
 
 /* _ctrl2080nvlink_h_ */
 

src/common/shared/inc/g_vgpu_chip_flags.h

@@ -615,25 +615,6 @@ ENTRY(0x2238, 0x16B7, 0x10de, "NVIDIA A10M-5C"),
 ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
 ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
 ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
-ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
-ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
-ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
-ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
-ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
-ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
-ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
-ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
-ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
-ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
-ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
-ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
-ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
-ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
-ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
-ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
-ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
-ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
-ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
 ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
 ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
 ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),

src/common/shared/inc/g_vgpu_resman_specific.h

@@ -17,7 +17,6 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
         { 0x20B7, 0x1804, 0x20B7, 0x1532 },
         { 0x20B9, 0x157F, 0x20B7, 0x1532 },
         { 0x20FD, 0x17F8, 0x20F5, 0x0 },
-        { 0x230E, 0x20DF, 0x230E, 0x20DF },
         { 0x2324, 0x17A8, 0x2324, 0x17A6 },
         { 0x2329, 0x198C, 0x2329, 0x198B },
         { 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -120,13 +119,6 @@ static const struct {
     {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU                                                                         , 1094}, // GRID A800-4-20C
     {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU                                                                             , 1095}, // GRID A800-7-40C
     {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU                                                                 , 1091}, // GRID A800-1-10C
-    {0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1499}, // NVIDIA H20L-1-15CME
-    {0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU                                                                     , 1500}, // NVIDIA H20L-1-15C
-    {0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU                                                                 , 1501}, // NVIDIA H20L-1-30C
-    {0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU                                                                      , 1502}, // NVIDIA H20L-2-30C
-    {0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU                                                                    , 1503}, // NVIDIA H20L-3-60C
-    {0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU                                                                         , 1504}, // NVIDIA H20L-4-60C
-    {0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU                                                                             , 1505}, // NVIDIA H20L-7-120C
     {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
     {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU                                                                     , 1062}, // NVIDIA H100L-1-12C
     {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU                                                                 , 1063}, // NVIDIA H100L-1-24C

src/nvidia-modeset/include/nvkms-flip.h

@@ -102,7 +102,8 @@ void nvIdleLayerChannels(NVDevEvoRec *pDevEvo,
     NvU32 layerMaskPerSdApiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]);
 
 void nvEvoClearSurfaceUsage(NVDevEvoRec *pDevEvo,
-                            NVSurfaceEvoPtr pSurfaceEvo);
+                            NVSurfaceEvoPtr pSurfaceEvo,
+                            const NvBool skipSync);
 
 NvBool nvIdleBaseChannelOneApiHead(NVDispEvoRec *pDispEvo, NvU32 apiHead,
                                    NvBool *pStoppedBase);

src/nvidia-modeset/src/nvkms-flip.c

@@ -1227,13 +1227,14 @@ void nvIdleLayerChannels(NVDevEvoRec *pDevEvo,
  * in-flight methods flip away from this surface.
  */
 void nvEvoClearSurfaceUsage(NVDevEvoRec *pDevEvo,
-                            NVSurfaceEvoPtr pSurfaceEvo)
+                            NVSurfaceEvoPtr pSurfaceEvo,
+                            const NvBool skipSync)
 {
     NvU32 head;
 
     /*
      * If the core channel is no longer allocated, we don't need to
-     * sync. This assumes the channels are allocated/deallocated
+     * clear usage/sync. This assumes the channels are allocated/deallocated
      * together.
      */
     if (pDevEvo->core) {
@@ -1242,16 +1243,20 @@ void nvEvoClearSurfaceUsage(NVDevEvoRec *pDevEvo,
             pDevEvo->hal->ClearSurfaceUsage(pDevEvo, pSurfaceEvo);
         }
 
-        nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__);
+        /* HALs with ClearSurfaceUsage() require sync to ensure completion. */
+        if (!skipSync ||
+            (pDevEvo->hal->ClearSurfaceUsage != NULL)) {
+            nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__);
 
-        for (head = 0; head < pDevEvo->numHeads; head++) {
+            for (head = 0; head < pDevEvo->numHeads; head++) {
-            NvU32 layer;
+                NvU32 layer;
 
-            for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) {
+                for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) {
-                NVEvoChannelPtr pChannel =
+                    NVEvoChannelPtr pChannel =
-                    pDevEvo->head[head].layer[layer];
+                        pDevEvo->head[head].layer[layer];
 
-                nvRMSyncEvoChannel(pDevEvo, pChannel, __LINE__);
+                    nvRMSyncEvoChannel(pDevEvo, pChannel, __LINE__);
+                }
             }
         }
     }

src/nvidia-modeset/src/nvkms-surface.c

@@ -1162,14 +1162,14 @@ void nvEvoDecrementSurfaceRefCntsWithSync(NVDevEvoPtr pDevEvo,
 
     if (pSurfaceEvo->rmRefCnt == 0) {
         /*
-         * Don't sync if this surface was registered as not requiring display
+         * Don't clear usage/sync if this surface was registered as not
-         * hardware access, to WAR timeouts that result from OGL unregistering
+         * requiring display hardware access, to WAR timeouts that result from
-         * a deferred request fifo causing a sync here that may timeout if
+         * OGL unregistering a deferred request fifo causing a sync here that
-         * GLS hasn't had the opportunity to release semaphores with pending
+         * may timeout if GLS hasn't had the opportunity to release semaphores
-         * flips. (Bug 2050970)
+         * with pending flips. (Bug 2050970)
          */
-        if (!skipSync && pSurfaceEvo->requireDisplayHardwareAccess) {
+        if (pSurfaceEvo->requireDisplayHardwareAccess) {
-            nvEvoClearSurfaceUsage(pDevEvo, pSurfaceEvo);
+            nvEvoClearSurfaceUsage(pDevEvo, pSurfaceEvo, skipSync);
         }
 
         FreeSurfaceEvoRm(pDevEvo, pSurfaceEvo);

src/nvidia/arch/nvalloc/common/inc/oob/smbpbi_priv.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2010-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -47,33 +47,13 @@
 #define NV_MSGBOX_CMD_ERR_MORE_PROCESSING_REQUIRED              0x000000F0
 
 //
-// Alternative encodings of the command word
+// Alternative encodings of the command word.
-// These are distinguished by a non-zero value in the 29:29 bit,
+// These were distinguished by a non-zero value in the 29:29 bit.
-// previously known as _RSVD.
+// Bit 29 is now reserved and must be 0 i.e. only standard requests will be processed
+// and debug requests would fail.
 //
 #define NV_MSGBOX_CMD_ENCODING                               29:29
 #define NV_MSGBOX_CMD_ENCODING_STANDARD                 0x00000000
-#define NV_MSGBOX_CMD_ENCODING_DEBUG                    0x00000001
-
-// Debug command structure
-#define NV_MSGBOX_DEBUG_CMD_OPCODE                             1:0
-#define NV_MSGBOX_DEBUG_CMD_OPCODE_READ_PRIV            0x00000000
-
-#define NV_MSGBOX_DEBUG_CMD_ARG                               23:2
-
-/* Utility command constructor macros */
-
-#define NV_MSGBOX_DEBUG_CMD(opcode, arg)                    \
-        (                                                   \
-            DRF_DEF(_MSGBOX, _DEBUG_CMD, _OPCODE, opcode) | \
-            DRF_NUM(_MSGBOX, _DEBUG_CMD, _ARG, (arg))     | \
-            DRF_DEF(_MSGBOX, _CMD, _STATUS, _NULL)        | \
-            DRF_DEF(_MSGBOX, _CMD, _ENCODING, _DEBUG)     | \
-            DRF_DEF(_MSGBOX, _CMD, _INTR, _PENDING)         \
-        )
-
-#define NV_MSGBOX_DEBUG_CMD_READ_PRIV(offset) \
-    NV_MSGBOX_DEBUG_CMD(_READ_PRIV, (offset) >> 2)
 
 #endif // _SMBPBI_PRIV_H_
 

src/nvidia/generated/g_kernel_channel_group_nvoc.h

@@ -16,7 +16,7 @@ extern "C" {
 #endif
 
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a

src/nvidia/generated/g_kernel_gsp_nvoc.c

@@ -910,7 +910,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner *
     {
         if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: GB202 | GB203 | GB205 | GB206 | GB207 | GB20B */ 
         {
-            pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_1bb8e3;
+            pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ad951d;
         }
         else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 
         {

src/nvidia/generated/g_kernel_gsp_nvoc.h

@@ -1397,8 +1397,8 @@ static inline NvU32 kgspGetNonWprHeapSize_d505ea(struct OBJGPU *pGpu, struct Ker
     return 2097152;
 }
 
-static inline NvU32 kgspGetNonWprHeapSize_1bb8e3(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
+static inline NvU32 kgspGetNonWprHeapSize_ad951d(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
-    return 2228224;
+    return 2293760;
 }
 
 static inline NvU32 kgspGetNonWprHeapSize_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {

src/nvidia/generated/g_mem_mgr_nvoc.c

@@ -390,9 +390,21 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p
     }
 
     // Hal field -- bUseVirtualCopyOnSuspend
-    if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000003UL) )) /* RmVariantHal: VF | PF_KERNEL_ONLY */ 
+    if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ 
     {
-        pThis->bUseVirtualCopyOnSuspend = NV_TRUE;
+        if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 
+        {
+            pThis->bUseVirtualCopyOnSuspend = NV_FALSE;
+        }
+        // default
+        else
+        {
+            pThis->bUseVirtualCopyOnSuspend = NV_TRUE;
+        }
+    }
+    else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ 
+    {
+        pThis->bUseVirtualCopyOnSuspend = NV_FALSE;
     }
 }
 

src/nvidia/generated/g_nv_name_released.h

@@ -5433,16 +5433,30 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2C05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti" },
     { 0x2C18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
     { 0x2C19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
+    { 0x2C31, 0x2051, 0x1028, "NVIDIA RTX PRO 4500 Blackwell" },
+    { 0x2C31, 0x2051, 0x103c, "NVIDIA RTX PRO 4500 Blackwell" },
+    { 0x2C31, 0x2051, 0x10de, "NVIDIA RTX PRO 4500 Blackwell" },
+    { 0x2C31, 0x2051, 0x17aa, "NVIDIA RTX PRO 4500 Blackwell" },
+    { 0x2C34, 0x2052, 0x1028, "NVIDIA RTX PRO 4000 Blackwell" },
+    { 0x2C34, 0x2052, 0x103c, "NVIDIA RTX PRO 4000 Blackwell" },
+    { 0x2C34, 0x2052, 0x10de, "NVIDIA RTX PRO 4000 Blackwell" },
+    { 0x2C34, 0x2052, 0x17aa, "NVIDIA RTX PRO 4000 Blackwell" },
+    { 0x2C38, 0x0000, 0x0000, "NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU" },
+    { 0x2C39, 0x0000, 0x0000, "NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU" },
     { 0x2C58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
     { 0x2C59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
     { 0x2D04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Ti" },
     { 0x2D05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060" },
     { 0x2D18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
     { 0x2D19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
+    { 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
     { 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
     { 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
+    { 0x2DB8, 0x0000, 0x0000, "NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU" },
+    { 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
     { 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
     { 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
+    { 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" },
     { 0x2F58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
     { 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" },
     { 0x13BD, 0x11cd, 0x10DE, "GRID M10-1B" },
@@ -6038,25 +6052,6 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" },
     { 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" },
     { 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" },
-    { 0x230E, 0x20f5, 0x10DE, "NVIDIA H20L-1-15CME" },
-    { 0x230E, 0x20f6, 0x10DE, "NVIDIA H20L-1-15C" },
-    { 0x230E, 0x20f7, 0x10DE, "NVIDIA H20L-1-30C" },
-    { 0x230E, 0x20f8, 0x10DE, "NVIDIA H20L-2-30C" },
-    { 0x230E, 0x20f9, 0x10DE, "NVIDIA H20L-3-60C" },
-    { 0x230E, 0x20fa, 0x10DE, "NVIDIA H20L-4-60C" },
-    { 0x230E, 0x20fb, 0x10DE, "NVIDIA H20L-7-120C" },
-    { 0x230E, 0x20fc, 0x10DE, "NVIDIA H20L-4C" },
-    { 0x230E, 0x20fd, 0x10DE, "NVIDIA H20L-5C" },
-    { 0x230E, 0x20fe, 0x10DE, "NVIDIA H20L-6C" },
-    { 0x230E, 0x20ff, 0x10DE, "NVIDIA H20L-8C" },
-    { 0x230E, 0x2100, 0x10DE, "NVIDIA H20L-10C" },
-    { 0x230E, 0x2101, 0x10DE, "NVIDIA H20L-12C" },
-    { 0x230E, 0x2102, 0x10DE, "NVIDIA H20L-15C" },
-    { 0x230E, 0x2103, 0x10DE, "NVIDIA H20L-20C" },
-    { 0x230E, 0x2104, 0x10DE, "NVIDIA H20L-30C" },
-    { 0x230E, 0x2105, 0x10DE, "NVIDIA H20L-40C" },
-    { 0x230E, 0x2106, 0x10DE, "NVIDIA H20L-60C" },
-    { 0x230E, 0x2107, 0x10DE, "NVIDIA H20L-120C" },
     { 0x2321, 0x1853, 0x10DE, "NVIDIA H100L-1-12CME" },
     { 0x2321, 0x1854, 0x10DE, "NVIDIA H100L-1-12C" },
     { 0x2321, 0x1855, 0x10DE, "NVIDIA H100L-1-24C" },

src/nvidia/generated/g_subdevice_nvoc.c

@@ -8901,6 +8901,66 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
 #endif
     },
     {               /*  [584] */
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*pFunc=*/      (void (*)(void)) NULL,
+#else
+        /*pFunc=*/      (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccess_IMPL,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*flags=*/      0x44u,
+        /*accessRight=*/0x0u,
+        /*methodId=*/   0x20803090u,
+        /*paramSize=*/  sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS),
+        /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
+#if NV_PRINTF_STRINGS_ALLOWED
+        /*func=*/       "subdeviceCtrlCmdNvlinkPRMAccess"
+#endif
+    },
+    {               /*  [585] */
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*pFunc=*/      (void (*)(void)) NULL,
+#else
+        /*pFunc=*/      (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*flags=*/      0x44u,
+        /*accessRight=*/0x0u,
+        /*methodId=*/   0x20803091u,
+        /*paramSize=*/  sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS),
+        /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
+#if NV_PRINTF_STRINGS_ALLOWED
+        /*func=*/       "subdeviceCtrlCmdNvlinkPRMAccessPPRM"
+#endif
+    },
+    {               /*  [586] */
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*pFunc=*/      (void (*)(void)) NULL,
+#else
+        /*pFunc=*/      (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*flags=*/      0x44u,
+        /*accessRight=*/0x0u,
+        /*methodId=*/   0x20803093u,
+        /*paramSize=*/  sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS),
+        /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
+#if NV_PRINTF_STRINGS_ALLOWED
+        /*func=*/       "subdeviceCtrlCmdNvlinkPRMAccessPTASV2"
+#endif
+    },
+    {               /*  [587] */
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*pFunc=*/      (void (*)(void)) NULL,
+#else
+        /*pFunc=*/      (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+        /*flags=*/      0x44u,
+        /*accessRight=*/0x0u,
+        /*methodId=*/   0x20803094u,
+        /*paramSize=*/  sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS),
+        /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
+#if NV_PRINTF_STRINGS_ALLOWED
+        /*func=*/       "subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM"
+#endif
+    },
+    {               /*  [588] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -8915,7 +8975,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlcnGetDmemUsage"
 #endif
     },
-    {               /*  [585] */
+    {               /*  [589] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -8930,7 +8990,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlcnGetEngineArch"
 #endif
     },
-    {               /*  [586] */
+    {               /*  [590] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -8945,7 +9005,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlcnUstreamerQueueInfo"
 #endif
     },
-    {               /*  [587] */
+    {               /*  [591] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -8960,7 +9020,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlcnUstreamerControlGet"
 #endif
     },
-    {               /*  [588] */
+    {               /*  [592] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -8975,7 +9035,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlcnUstreamerControlSet"
 #endif
     },
-    {               /*  [589] */
+    {               /*  [593] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -8990,7 +9050,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlcnGetCtxBufferInfo"
 #endif
     },
-    {               /*  [590] */
+    {               /*  [594] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9005,7 +9065,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlcnGetCtxBufferSize"
 #endif
     },
-    {               /*  [591] */
+    {               /*  [595] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9020,7 +9080,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdEccGetClientExposedCounters"
 #endif
     },
-    {               /*  [592] */
+    {               /*  [596] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9035,7 +9095,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdEccGetVolatileCounts"
 #endif
     },
-    {               /*  [593] */
+    {               /*  [597] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9050,7 +9110,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlaRange"
 #endif
     },
-    {               /*  [594] */
+    {               /*  [598] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10244u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9065,7 +9125,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlaSetupInstanceMemBlock"
 #endif
     },
-    {               /*  [595] */
+    {               /*  [599] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10004u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9080,7 +9140,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlaGetRange"
 #endif
     },
-    {               /*  [596] */
+    {               /*  [600] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x108u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9095,7 +9155,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdFlaGetFabricMemStats"
 #endif
     },
-    {               /*  [597] */
+    {               /*  [601] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40549u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9110,7 +9170,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdGspGetFeatures"
 #endif
     },
-    {               /*  [598] */
+    {               /*  [602] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9125,7 +9185,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdGspGetRmHeapStats"
 #endif
     },
-    {               /*  [599] */
+    {               /*  [603] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9140,7 +9200,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdGpuGetVgpuHeapStats"
 #endif
     },
-    {               /*  [600] */
+    {               /*  [604] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x248u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9155,7 +9215,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdLibosGetHeapStats"
 #endif
     },
-    {               /*  [601] */
+    {               /*  [605] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x248u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9170,7 +9230,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdGrmgrGetGrFsInfo"
 #endif
     },
-    {               /*  [602] */
+    {               /*  [606] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9185,7 +9245,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt"
 #endif
     },
-    {               /*  [603] */
+    {               /*  [607] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9200,7 +9260,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdOsUnixAllowDisallowGcoff"
 #endif
     },
-    {               /*  [604] */
+    {               /*  [608] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9215,7 +9275,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdOsUnixAudioDynamicPower"
 #endif
     },
-    {               /*  [605] */
+    {               /*  [609] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xbu)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9230,7 +9290,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus"
 #endif
     },
-    {               /*  [606] */
+    {               /*  [610] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9245,7 +9305,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdOsUnixUpdateTgpStatus"
 #endif
     },
-    {               /*  [607] */
+    {               /*  [611] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9260,7 +9320,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask"
 #endif
     },
-    {               /*  [608] */
+    {               /*  [612] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9275,7 +9335,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask"
 #endif
     },
-    {               /*  [609] */
+    {               /*  [613] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9290,7 +9350,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType"
 #endif
     },
-    {               /*  [610] */
+    {               /*  [614] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9305,7 +9365,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu"
 #endif
     },
-    {               /*  [611] */
+    {               /*  [615] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9320,7 +9380,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo"
 #endif
     },
-    {               /*  [612] */
+    {               /*  [616] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9335,7 +9395,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage"
 #endif
     },
-    {               /*  [613] */
+    {               /*  [617] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1d0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9350,7 +9410,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity"
 #endif
     },
-    {               /*  [614] */
+    {               /*  [618] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9365,7 +9425,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources"
 #endif
     },
-    {               /*  [615] */
+    {               /*  [619] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9380,7 +9440,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding"
 #endif
     },
-    {               /*  [616] */
+    {               /*  [620] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9395,7 +9455,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport"
 #endif
     },
-    {               /*  [617] */
+    {               /*  [621] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9410,7 +9470,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig"
 #endif
     },
-    {               /*  [618] */
+    {               /*  [622] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9425,7 +9485,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalFreeStates"
 #endif
     },
-    {               /*  [619] */
+    {               /*  [623] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9440,7 +9500,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalGetFrameRateLimiterStatus"
 #endif
     },
-    {               /*  [620] */
+    {               /*  [624] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9455,7 +9515,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalSetVgpuHeterogeneousMode"
 #endif
     },
-    {               /*  [621] */
+    {               /*  [625] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9470,7 +9530,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMigTimesliceMode"
 #endif
     },
-    {               /*  [622] */
+    {               /*  [626] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9485,7 +9545,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdGetAvailableHshubMask"
 #endif
     },
-    {               /*  [623] */
+    {               /*  [627] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9500,7 +9560,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlSetEcThrottleMode"
 #endif
     },
-    {               /*  [624] */
+    {               /*  [628] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10bu)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9515,7 +9575,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
         /*func=*/       "subdeviceCtrlCmdRusdGetSupportedFeatures"
 #endif
     },
-    {               /*  [625] */
+    {               /*  [629] */
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
@@ -9841,7 +9901,7 @@ NV_STATUS __nvoc_up_thunk_Notifier_subdeviceGetOrAllocNotifShare(struct Subdevic
 
 const struct NVOC_EXPORT_INFO __nvoc_export_info__Subdevice = 
 {
-    /*numEntries=*/     626,
+    /*numEntries=*/     630,
     /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice
 };
 
@@ -10581,6 +10641,26 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
     pThis->__subdeviceCtrlCmdNvlinkGetNvleLids__ = &subdeviceCtrlCmdNvlinkGetNvleLids_IMPL;
 #endif
 
+    // subdeviceCtrlCmdNvlinkPRMAccessPTASV2 -- exported (id=0x20803093)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+    pThis->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__ = &subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL;
+#endif
+
+    // subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM -- exported (id=0x20803094)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+    pThis->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__ = &subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL;
+#endif
+
+    // subdeviceCtrlCmdNvlinkPRMAccessPPRM -- exported (id=0x20803091)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+    pThis->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__ = &subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL;
+#endif
+
+    // subdeviceCtrlCmdNvlinkPRMAccess -- exported (id=0x20803090)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
+    pThis->__subdeviceCtrlCmdNvlinkPRMAccess__ = &subdeviceCtrlCmdNvlinkPRMAccess_IMPL;
+#endif
+
     // subdeviceCtrlCmdNvlinkGetPlatformInfo -- exported (id=0x20803083)
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
     pThis->__subdeviceCtrlCmdNvlinkGetPlatformInfo__ = &subdeviceCtrlCmdNvlinkGetPlatformInfo_IMPL;
@@ -11182,6 +11262,16 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
     pThis->__subdeviceCtrlCmdKGrSetGpcTileMap__ = &subdeviceCtrlCmdKGrSetGpcTileMap_IMPL;
 #endif
+} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s).
+
+// Vtable initialization 2/3
+static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
+    RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
+    const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
+    PORT_UNREFERENCED_VARIABLE(pThis);
+    PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
+    PORT_UNREFERENCED_VARIABLE(rmVariantHal);
+    PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
 
     // subdeviceCtrlCmdKGrCtxswSmpcMode -- exported (id=0x2080120e)
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
@@ -11202,16 +11292,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x118u)
     pThis->__subdeviceCtrlCmdKGrGetGlobalSmOrder__ = &subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL;
 #endif
-} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s).
-
-// Vtable initialization 2/3
-static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
-    RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
-    const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
-    PORT_UNREFERENCED_VARIABLE(pThis);
-    PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
 
     // subdeviceCtrlCmdKGrSetCtxswPreemptionMode -- exported (id=0x20801210)
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x348u)
@@ -12503,6 +12583,16 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
     pThis->__subdeviceCtrlCmdInternalRecoverAllComputeContexts__ = &subdeviceCtrlCmdInternalRecoverAllComputeContexts_IMPL;
 #endif
+} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s).
+
+// Vtable initialization 3/3
+static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
+    RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
+    const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
+    PORT_UNREFERENCED_VARIABLE(pThis);
+    PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
+    PORT_UNREFERENCED_VARIABLE(rmVariantHal);
+    PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
 
     // subdeviceCtrlCmdInternalGetSmcMode -- exported (id=0x20800a4c)
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
@@ -12523,16 +12613,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
     pThis->__subdeviceCtrlCmdInternalBusFlushWithSysmembar__ = &subdeviceCtrlCmdInternalBusFlushWithSysmembar_IMPL;
 #endif
-} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s).
-
-// Vtable initialization 3/3
-static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
-    RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
-    const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
-    PORT_UNREFERENCED_VARIABLE(pThis);
-    PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
 
     // subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal -- exported (id=0x20800a71)
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
@@ -13278,13 +13358,13 @@ static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
     pThis->__subdeviceSpdmRetrieveTranscript__ = &subdeviceSpdmRetrieveTranscript_IMPL;
 #endif
-} // End __nvoc_init_funcTable_Subdevice_3 with approximately 149 basic block(s).
+} // End __nvoc_init_funcTable_Subdevice_3 with approximately 153 basic block(s).
 
 
-// Initialize vtable(s) for 656 virtual method(s).
+// Initialize vtable(s) for 660 virtual method(s).
 void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
 
-    // Initialize vtable(s) with 626 per-object function pointer(s).
+    // Initialize vtable(s) with 630 per-object function pointer(s).
     // To reduce stack pressure with some unoptimized builds, the logic is distributed among 3 functions.
     __nvoc_init_funcTable_Subdevice_1(pThis, pRmhalspecowner);
     __nvoc_init_funcTable_Subdevice_2(pThis, pRmhalspecowner);

src/nvidia/generated/g_subdevice_nvoc.h

@@ -155,7 +155,7 @@ struct Subdevice {
     struct Notifier *__nvoc_pbase_Notifier;    // notify super
     struct Subdevice *__nvoc_pbase_Subdevice;    // subdevice
 
-    // Vtable with 626 per-object function pointers
+    // Vtable with 630 per-object function pointers
     NV_STATUS (*__subdeviceCtrlCmdBiosGetInfoV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *);  // halified (2 hals) exported (id=0x20800810) body
     NV_STATUS (*__subdeviceCtrlCmdBiosGetNbsiV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS *);  // exported (id=0x2080080e)
     NV_STATUS (*__subdeviceCtrlCmdBiosGetSKUInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *);  // halified (2 hals) exported (id=0x20800808)
@@ -281,6 +281,10 @@ struct Subdevice {
     NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPLIB__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS *);  // exported (id=0x20803080)
     NV_STATUS (*__subdeviceCtrlCmdNvlinkUpdateNvleTopology__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS *);  // exported (id=0x2080308c)
     NV_STATUS (*__subdeviceCtrlCmdNvlinkGetNvleLids__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS *);  // exported (id=0x2080308d)
+    NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *);  // exported (id=0x20803093)
+    NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *);  // exported (id=0x20803094)
+    NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPPRM__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *);  // exported (id=0x20803091)
+    NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccess__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *);  // exported (id=0x20803090)
     NV_STATUS (*__subdeviceCtrlCmdNvlinkGetPlatformInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *);  // exported (id=0x20803083)
     NV_STATUS (*__subdeviceCtrlCmdNvlinkGetNvleEncryptEnInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS *);  // exported (id=0x2080308b)
     NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice * /*this*/, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *);  // exported (id=0x20800601)
@@ -1155,6 +1159,14 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
 #define subdeviceCtrlCmdNvlinkUpdateNvleTopology(arg_this, arg2) subdeviceCtrlCmdNvlinkUpdateNvleTopology_DISPATCH(arg_this, arg2)
 #define subdeviceCtrlCmdNvlinkGetNvleLids_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkGetNvleLids__
 #define subdeviceCtrlCmdNvlinkGetNvleLids(arg_this, arg2) subdeviceCtrlCmdNvlinkGetNvleLids_DISPATCH(arg_this, arg2)
+#define subdeviceCtrlCmdNvlinkPRMAccessPTASV2_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__
+#define subdeviceCtrlCmdNvlinkPRMAccessPTASV2(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPTASV2_DISPATCH(arg_this, arg2)
+#define subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__
+#define subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_DISPATCH(arg_this, arg2)
+#define subdeviceCtrlCmdNvlinkPRMAccessPPRM_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__
+#define subdeviceCtrlCmdNvlinkPRMAccessPPRM(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPPRM_DISPATCH(arg_this, arg2)
+#define subdeviceCtrlCmdNvlinkPRMAccess_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccess__
+#define subdeviceCtrlCmdNvlinkPRMAccess(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccess_DISPATCH(arg_this, arg2)
 #define subdeviceCtrlCmdNvlinkGetPlatformInfo_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkGetPlatformInfo__
 #define subdeviceCtrlCmdNvlinkGetPlatformInfo(arg_this, arg2) subdeviceCtrlCmdNvlinkGetPlatformInfo_DISPATCH(arg_this, arg2)
 #define subdeviceCtrlCmdNvlinkGetNvleEncryptEnInfo_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkGetNvleEncryptEnInfo__
@@ -2766,6 +2778,22 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkGetNvleLids_DISPATCH(struct Subdev
     return arg_this->__subdeviceCtrlCmdNvlinkGetNvleLids__(arg_this, arg2);
 }
 
+static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPTASV2_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *arg2) {
+    return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__(arg_this, arg2);
+}
+
+static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *arg2) {
+    return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__(arg_this, arg2);
+}
+
+static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPRM_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *arg2) {
+    return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__(arg_this, arg2);
+}
+
+static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccess_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *arg2) {
+    return arg_this->__subdeviceCtrlCmdNvlinkPRMAccess__(arg_this, arg2);
+}
+
 static inline NV_STATUS subdeviceCtrlCmdNvlinkGetPlatformInfo_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *arg2) {
     return arg_this->__subdeviceCtrlCmdNvlinkGetPlatformInfo__(arg_this, arg2);
 }
@@ -5188,6 +5216,14 @@ NV_STATUS subdeviceCtrlCmdNvlinkUpdateNvleTopology_IMPL(struct Subdevice *arg1,
 
 NV_STATUS subdeviceCtrlCmdNvlinkGetNvleLids_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS *arg2);
 
+NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *arg2);
+
+NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *arg2);
+
+NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *arg2);
+
+NV_STATUS subdeviceCtrlCmdNvlinkPRMAccess_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *arg2);
+
 NV_STATUS subdeviceCtrlCmdNvlinkGetPlatformInfo_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *arg2);
 
 NV_STATUS subdeviceCtrlCmdNvlinkGetNvleEncryptEnInfo_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS *arg2);

src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c

@@ -899,6 +899,11 @@ kfspGetGspUcodeArchive
                     {
                         return gspGetBinArchiveGspFmcSpdmGfwDebugSigned_HAL(pGsp);
                     }
+                    else
+                    {
+                        // When CC is enabled but SPDM is not enabled. Only for MODS.
+                        return gspGetBinArchiveGspFmcGfwDebugSigned_HAL(pGsp);
+                    }
                 }
                 else
                 {
@@ -937,6 +942,11 @@ kfspGetGspUcodeArchive
                     {
                         return gspGetBinArchiveGspCcFmcGfwProdSigned_HAL(pGsp);
                     }
+                    else
+                    {
+                        // When CC is enabled but SPDM is not enabled. Only for MODS.
+                        return gspGetBinArchiveGspFmcGfwDebugSigned_HAL(pGsp);
+                    }
                 }
                 else
                 {

src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c

@@ -309,7 +309,7 @@ fbsrBegin_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op)
         if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu))
         {
             pFbsr->pCe = NULL;
-            bVirtualMode = !IS_VIRTUAL(pGpu) ? NV_TRUE : NV_FALSE;
+            bVirtualMode = pMemoryManager->bUseVirtualCopyOnSuspend;
             NV_ASSERT_OK_OR_RETURN(memmgrInitCeUtils(pMemoryManager, NV_FALSE, bVirtualMode));
         }
 

src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c

@@ -1912,8 +1912,10 @@ dmaUpdateVASpace_GF100
                 break;
     }
 
-    isVolatile |= !!(flags & DMA_UPDATE_VASPACE_FLAGS_VOLATILE);
+    {
-    isVolatile &= !(flags & DMA_UPDATE_VASPACE_FLAGS_NONVOLATILE);
+        isVolatile |= !!(flags & DMA_UPDATE_VASPACE_FLAGS_VOLATILE);
+        isVolatile &= !(flags & DMA_UPDATE_VASPACE_FLAGS_NONVOLATILE);
+    }
 
     encrypted = (flags & DMA_UPDATE_VASPACE_FLAGS_DISABLE_ENCRYPTION) ? 0 :
         memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ENCRYPTED);

src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c

@@ -324,7 +324,8 @@ _memmgrAllocFbsrReservedRanges
                          pWprMeta->vgaWorkspaceSize;                                              // VGA Workspace
 
             // Check if CBC region needs to be saved
-            if (GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->bPreserveComptagBackingStoreOnSuspend)
+            if (GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->bPreserveComptagBackingStoreOnSuspend ||
+                pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED))
             {
                 NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS compbitStoreInfoParams;
                 RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);

src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c

@@ -456,7 +456,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL
             .inst.request.requestFlags = pParams->flags
         };
 
-        if (!hypervisorIsVgxHyper())
+        if (!gpuIsSriovEnabled(pGpu))
         {
             request.inst.request.requestFlags = FLD_SET_DRF(C637_CTRL, _DMA_EXEC_PARTITIONS_CREATE_REQUEST, _WITH_PART_ID, _FALSE, request.inst.request.requestFlags);
         }

src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c

@@ -3829,12 +3829,13 @@ subdeviceCtrlCmdThermalSystemExecuteV2_IMPL(Subdevice *pSubdevice,
 {
     OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice);
     RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
+    NvU32 instructionListSize = pSystemExecuteParams->instructionListSize;
+    (void)instructionListSize;
 
     NV_STATUS status = NV_OK;
     NvBool bForwardRmctrl;
-    NvU32 instructionListSize;
 
-    for (NvU32 i = 0; i < pSystemExecuteParams->instructionListSize; i++)
+    for (NvU32 i = 0; i < instructionListSize; i++)
     {
         pSystemExecuteParams->instructionList[i].executed = NV_FALSE;
     }
@@ -3853,7 +3854,6 @@ subdeviceCtrlCmdThermalSystemExecuteV2_IMPL(Subdevice *pSubdevice,
     bForwardRmctrl = NV_FALSE;
 
     // Service values from cache
-    instructionListSize = pSystemExecuteParams->instructionListSize;
     for (NvU32 i = 0; i < instructionListSize; i++)
     {
         // Verify that the size of the union NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS is dictated by

src/nvidia/src/kernel/vgpu/vgpu_util.c

@@ -267,7 +267,7 @@ static NV_STATUS vgpuExpandSysmemPfnBitMapList(OBJGPU *pGpu, NvU64 pfn)
         vgpuSysmemPfnInfo.guestMaxPfn  = node->nodeEndPfn;
         vgpuSysmemPfnInfo.sizeInBytes  = vgpuSysmemPfnInfo.guestMaxPfn / 8;
 
-    } while (vgpuSysmemPfnInfo.guestMaxPfn < pfn);
+    } while (vgpuSysmemPfnInfo.guestMaxPfn <= pfn);
 
     // Alloc the ref count buffer
     temp_pfn_ref_count = portMemAllocNonPaged(sizeof(NvU16) * vgpuSysmemPfnInfo.guestMaxPfn);
@@ -445,7 +445,7 @@ NV_STATUS vgpuUpdateSysmemPfnBitMap
 
         if (bAlloc)
         {
-            if (pfn > vgpuSysmemPfnInfo.guestMaxPfn)
+            if (pfn >= vgpuSysmemPfnInfo.guestMaxPfn)
             {
                 NV_PRINTF(LEVEL_INFO, "Update sysmem pfn bitmap for pfn: 0x%llx > guestMaxPfn: 0x%llx\n",
                           pfn, vgpuSysmemPfnInfo.guestMaxPfn);

version.mk

@@ -1,5 +1,5 @@
-NVIDIA_VERSION = 575.57.08
+NVIDIA_VERSION = 575.64
-NVIDIA_NVID_VERSION = 575.57.08
+NVIDIA_NVID_VERSION = 575.64
 NVIDIA_NVID_EXTRA = 
 
 # This file.