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This commit is contained in:
Andy Ritger
2022-09-20 13:54:59 -07:00
parent 9855350159
commit fe0728787f
50 changed files with 822 additions and 367 deletions
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42
src/nvidia/arch/nvalloc/unix/include/nv.h
View File

@@ -619,27 +619,33 @@ typedef enum
#define NV_GET_NV_STATE(pGpu) \
(nv_state_t *)((pGpu) ? (pGpu)->pOsGpuInfo : NULL)
#define IS_REG_OFFSET(nv, offset, length) \
(((offset) >= (nv)->regs->cpu_address) && \
(((offset) + ((length)-1)) <= \
(nv)->regs->cpu_address + ((nv)->regs->size-1)))
static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
{
return ((offset >= nv->regs->cpu_address) &&
((offset + (length - 1)) <= (nv->regs->cpu_address + (nv->regs->size - 1))));
}
#define IS_FB_OFFSET(nv, offset, length) \
(((nv)->fb) && ((offset) >= (nv)->fb->cpu_address) && \
(((offset) + ((length)-1)) <= (nv)->fb->cpu_address + ((nv)->fb->size-1)))
static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
{
return ((nv->fb) && (offset >= nv->fb->cpu_address) &&
((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1))));
}
#define IS_UD_OFFSET(nv, offset, length) \
(((nv)->ud.cpu_address != 0) && ((nv)->ud.size != 0) && \
((offset) >= (nv)->ud.cpu_address) && \
(((offset) + ((length)-1)) <= (nv)->ud.cpu_address + ((nv)->ud.size-1)))
static inline NvBool IS_UD_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
{
return ((nv->ud.cpu_address != 0) && (nv->ud.size != 0) &&
(offset >= nv->ud.cpu_address) &&
((offset + (length - 1)) <= (nv->ud.cpu_address + (nv->ud.size - 1))));
}
#define IS_IMEM_OFFSET(nv, offset, length) \
(((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && \
((nv)->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && \
((offset) >= (nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && \
(((offset) + ((length) - 1)) <= \
(nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + \
((nv)->bars[NV_GPU_BAR_INDEX_IMEM].size - 1)))
static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
{
return ((nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) &&
(nv->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) &&
(offset >= nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) &&
((offset + (length - 1)) <= (nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address +
(nv->bars[NV_GPU_BAR_INDEX_IMEM].size - 1))));
}
#define NV_RM_MAX_MSIX_LINES 8

8
src/nvidia/arch/nvalloc/unix/src/osapi.c
View File

@@ -780,10 +780,8 @@ static NV_STATUS RmAccessRegistry(
RmStatus = NV_ERR_INVALID_STRING_LENGTH;
goto done;
}
// get access to client's parmStr
RMAPI_PARAM_COPY_INIT(parmStrParamCopy, tmpParmStr, clientParmStrAddress, ParmStrLength, 1);
parmStrParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER;
RmStatus = rmapiParamsAcquire(&parmStrParamCopy, NV_TRUE);
if (RmStatus != NV_OK)
{
@@ -2026,6 +2024,7 @@ static NV_STATUS RmGetAllocPrivate(
PMEMORY_DESCRIPTOR pMemDesc;
NvU32 pageOffset;
NvU64 pageCount;
NvU64 endingOffset;
RsResourceRef *pResourceRef;
RmResource *pRmResource;
void *pMemData;
@@ -2086,8 +2085,9 @@ static NV_STATUS RmGetAllocPrivate(
if (rmStatus != NV_OK)
goto done;
pageCount = ((pageOffset + length) / os_page_size);
pageCount += (*pPageIndex + (((pageOffset + length) % os_page_size) ? 1 : 0));
endingOffset = pageOffset + length;
pageCount = (endingOffset / os_page_size);
pageCount += (*pPageIndex + ((endingOffset % os_page_size) ? 1 : 0));
if (pageCount > NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount))
{

25
src/nvidia/arch/nvalloc/unix/src/osinit.c
View File

@@ -362,10 +362,6 @@ osHandleGpuLost
pmc_boot_0 = NV_PRIV_REG_RD32(nv->regs->map_u, NV_PMC_BOOT_0);
if (pmc_boot_0 != nvp->pmc_boot_0)
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS *pBoardInfoParams;
NV_STATUS status;
//
// This doesn't support PEX Reset and Recovery yet.
// This will help to prevent accessing registers of a GPU
@@ -376,24 +372,11 @@ osHandleGpuLost
NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "GPU has fallen off the bus.\n");
pBoardInfoParams = portMemAllocNonPaged(sizeof(*pBoardInfoParams));
if (pBoardInfoParams != NULL)
if (pGpu->boardInfo != NULL && pGpu->boardInfo->serialNumber[0] != '\0')
{
portMemSet(pBoardInfoParams, 0, sizeof(*pBoardInfoParams));
status = pRmApi->Control(pRmApi, nv->rmapi.hClient,
nv->rmapi.hSubDevice,
NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO,
pBoardInfoParams,
sizeof(*pBoardInfoParams));
if (status == NV_OK)
{
NV_DEV_PRINTF(NV_DBG_ERRORS, nv,
"GPU serial number is %s.\n",
pBoardInfoParams->serialNumber);
}
portMemFree(pBoardInfoParams);
NV_DEV_PRINTF(NV_DBG_ERRORS, nv,
"GPU serial number is %s.\n",
pGpu->boardInfo->serialNumber);
}
gpuSetDisconnectedProperties(pGpu);

1
src/nvidia/generated/g_gpu_nvoc.h
View File

@@ -60,6 +60,7 @@ typedef struct GPUATTACHARG GPUATTACHARG;
* */
#include "ctrl/ctrl0080/ctrl0080gpu.h" // NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS (form hal)
#include "ctrl/ctrl2080/ctrl2080internal.h" // NV2080_CTRL_CMD_INTERNAL_MAX_BSPS/NVENCS
#include "ctrl/ctrl2080/ctrl2080ecc.h"
#include "ctrl/ctrl2080/ctrl2080nvd.h"
#include "class/cl2080.h"
#include "class/cl90cd.h"

1
src/nvidia/generated/g_kernel_gsp_nvoc.h
View File

@@ -301,6 +301,7 @@ struct KernelGsp {
LIBOS_LOG_DECODE logDecode;
RM_LIBOS_LOG_MEM rmLibosLogMem[2];
void *pLogElf;
NvBool bInInit;
MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf;
SimAccessBuffer *pSimAccessBuf;
NvP64 pSimAccessBufPriv;

3
src/nvidia/generated/g_nv_name_released.h
View File

@@ -806,6 +806,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x20B0, 0x1450, 0x10de, "NVIDIA A100-PG509-200" },
{ 0x20B2, 0x1463, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x147f, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x1622, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x1623, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B3, 0x14a7, 0x10de, "NVIDIA PG506-242" },
{ 0x20B3, 0x14a8, 0x10de, "NVIDIA PG506-243" },
{ 0x20B5, 0x1533, 0x10de, "NVIDIA A100 80GB PCIe" },
@@ -907,6 +909,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2507, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050" },
{ 0x2508, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 OEM" },
{ 0x2520, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Laptop GPU" },
{ 0x2521, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Laptop GPU" },
{ 0x2523, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Ti Laptop GPU" },
{ 0x2531, 0x151d, 0x1028, "NVIDIA RTX A2000" },
{ 0x2531, 0x151d, 0x103c, "NVIDIA RTX A2000" },

3
src/nvidia/inc/libraries/nvlog/nvlog.h
View File

@@ -86,8 +86,9 @@ NV_STATUS nvlogAllocBuffer(NvU32 size, NvU32 flags, NvU32 tag, NVLOG_BUFFER_HAND
* @brief Deallocate a buffer with the given handle
*
* @param[in] hBuffer Handle of the buffer to deallocate
* @param[in] bDeallocPreserved Deallocate preserved buffers
*/
void nvlogDeallocBuffer(NVLOG_BUFFER_HANDLE hBuffer);
void nvlogDeallocBuffer(NVLOG_BUFFER_HANDLE hBuffer, NvBool bDeallocPreserved);
/**
* @brief Write to a buffer with the given handle

10
src/nvidia/kernel/vgpu/nv/rpc.c
View File

@@ -265,8 +265,11 @@ static NV_STATUS _issueRpcLarge
// should not be called in broadcast mode
NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE);
//
// Copy the initial buffer
entryLength = NV_MIN(bufSize, pRpc->maxRpcSize);
// Temporary black magic WAR for bug 3594082: reducing the size by 1
//
entryLength = NV_MIN(bufSize, pRpc->maxRpcSize - 1);
if ((NvU8 *)vgpu_rpc_message_header_v != pBuf8)
portMemCopy(vgpu_rpc_message_header_v, entryLength, pBuf8, entryLength);
@@ -291,8 +294,11 @@ static NV_STATUS _issueRpcLarge
remainingSize -= entryLength;
pBuf8 += entryLength;
//
// Copy the remaining buffers
entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v);
// Temporary black magic WAR for bug 3594082: reducing the size by 1
//
entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v) - 1;
while (remainingSize != 0)
{
if (entryLength > remainingSize)

11
src/nvidia/src/kernel/diagnostics/nvlog.c
View File

@@ -103,7 +103,7 @@ nvlogDestroy()
tlsShutdown();
for (i = 0; i < NVLOG_MAX_BUFFERS; i++)
{
nvlogDeallocBuffer(i);
nvlogDeallocBuffer(i, NV_TRUE);
}
if (NvLogLogger.mainLock != NULL)
{
@@ -261,7 +261,8 @@ nvlogAllocBuffer
void
nvlogDeallocBuffer
(
NVLOG_BUFFER_HANDLE hBuffer
NVLOG_BUFFER_HANDLE hBuffer,
NvBool bDeallocPreserved
)
{
NVLOG_BUFFER *pBuffer;
@@ -271,6 +272,12 @@ nvlogDeallocBuffer
pBuffer = NvLogLogger.pBuffers[hBuffer];
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pBuffer->flags) &&
!bDeallocPreserved)
{
return;
}
pBuffer->flags = FLD_SET_DRF(LOG_BUFFER, _FLAGS, _DISABLED,
_YES, pBuffer->flags);

18
src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c
View File

@@ -2502,15 +2502,19 @@ kbusFlushSingle_GM107
if (IS_GSP_CLIENT(pGpu))
{
//
// on GSP client, we only support PCIE_READ to do flush
// a sysmembar flush should call kbusSendSysmembarSingle_HAL explicitly
// on GSP client, we should use PCIE_READ to do video memory flush.
// A sysmembar flush that touches registers is done through RPC and has
// lower effeciency. For cases where it needs sysmembar, the caller site
// should use kbusSendSysmembarSingle_HAL explicitly.
//
NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_PATH);
}
else
{
return kbusSendSysmembarSingle_HAL(pGpu, pKernelBus);
NV_ASSERT(0);
// This will dump a stack trace to assist debug on certain
// platforms.
osAssertFailed();
}
return kbusSendSysmembarSingle_HAL(pGpu, pKernelBus);
}
}

9
src/nvidia/src/kernel/gpu/fifo/kernel_channel.c
View File

@@ -3750,6 +3750,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL
Memory *pMemory;
ContextDma *pContextDma;
NvU32 addressSpace;
NvU64 notificationBufferSize;
NV_STATUS status;
hNotifier = pKernelChannel->hErrorContext;
@@ -3758,6 +3759,8 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL
NV_CHECK_OR_RETURN(LEVEL_INFO, index != NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR,
NV_ERR_INVALID_ARGUMENT);
notificationBufferSize = (index + 1) * sizeof(NvNotification);
status = deviceGetByInstance(pClient, gpuGetDeviceInstance(pGpu), &pDevice);
if (status != NV_OK)
return NV_ERR_INVALID_DEVICE;
@@ -3766,7 +3769,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL
{
addressSpace = memdescGetAddressSpace(pMemory->pMemDesc);
NV_CHECK_OR_RETURN(LEVEL_INFO, pMemory->Length >= ((index + 1) * sizeof(NvNotification)),
NV_CHECK_OR_RETURN(LEVEL_INFO, pMemory->Length >= notificationBufferSize,
NV_ERR_OUT_OF_RANGE);
switch (addressSpace)
{
@@ -3784,7 +3787,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL
&pDmaMappingInfo),
NV_ERR_GENERIC);
NV_CHECK_OR_RETURN(LEVEL_INFO, pDmaMappingInfo->pMemDesc->Size >= ((index + 1) * sizeof(NvNotification)),
NV_CHECK_OR_RETURN(LEVEL_INFO, pDmaMappingInfo->pMemDesc->Size >= notificationBufferSize,
NV_ERR_OUT_OF_RANGE);
break;
}
@@ -3799,7 +3802,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL
}
else if (NV_OK == ctxdmaGetByHandle(pClient, hNotifier, &pContextDma))
{
NV_CHECK_OR_RETURN(LEVEL_INFO, pContextDma->Limit >= (((index + 1) * sizeof(NvNotification)) - 1),
NV_CHECK_OR_RETURN(LEVEL_INFO, pContextDma->Limit >= (notificationBufferSize - 1),
NV_ERR_OUT_OF_RANGE);
}
else

46
src/nvidia/src/kernel/gpu/gpu.c
View File

@@ -1923,26 +1923,6 @@ gpuStatePreInit_IMPL
}
}
pGpu->boardInfo = portMemAllocNonPaged(sizeof(*pGpu->boardInfo));
if (pGpu->boardInfo)
{
// To avoid potential race of xid reporting with the control, zero it out
portMemSet(pGpu->boardInfo, '\0', sizeof(*pGpu->boardInfo));
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
if (pRmApi->Control(pRmApi,
pGpu->hInternalClient,
pGpu->hInternalSubdevice,
NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO,
pGpu->boardInfo,
sizeof(*pGpu->boardInfo)) != NV_OK)
{
portMemFree(pGpu->boardInfo);
pGpu->boardInfo = NULL;
}
}
return rmStatus;
}
@@ -2291,6 +2271,26 @@ gpuStatePostLoad
goto gpuStatePostLoad_exit;
}
pGpu->boardInfo = portMemAllocNonPaged(sizeof(*pGpu->boardInfo));
if (pGpu->boardInfo)
{
// To avoid potential race of xid reporting with the control, zero it out
portMemSet(pGpu->boardInfo, '\0', sizeof(*pGpu->boardInfo));
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
if(pRmApi->Control(pRmApi,
pGpu->hInternalClient,
pGpu->hInternalSubdevice,
NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO,
pGpu->boardInfo,
sizeof(*pGpu->boardInfo)) != NV_OK)
{
portMemFree(pGpu->boardInfo);
pGpu->boardInfo = NULL;
}
}
gpuStatePostLoad_exit:
return rmStatus;
}
@@ -2326,6 +2326,9 @@ gpuStatePreUnload
NvU32 curEngDescIdx;
NV_STATUS rmStatus = NV_OK;
portMemFree(pGpu->boardInfo);
pGpu->boardInfo = NULL;
engDescriptorList = gpuGetUnloadEngineDescriptors(pGpu);
numEngDescriptors = gpuGetNumEngDescriptors(pGpu);
@@ -2648,9 +2651,6 @@ gpuStateDestroy_IMPL
_gpuFreeInternalObjects(pGpu);
gpuDestroyGenericKernelFalconList(pGpu);
portMemFree(pGpu->boardInfo);
pGpu->boardInfo = NULL;
portMemFree(pGpu->gspSupportedEngines);
pGpu->gspSupportedEngines = NULL;

16
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
View File

@@ -1047,7 +1047,7 @@ _kgspInitLibosLoggingStructures
//
// Setup logging memory for each task.
// Use MEMDESC_FLAGS_CPU_ONLY -- to early to call memdescMapIommu.
// Use MEMDESC_FLAGS_CPU_ONLY -- too early to call memdescMapIommu.
//
NV_ASSERT_OK_OR_GOTO(nvStatus,
memdescCreate(&pLog->pTaskLogDescriptor,
@@ -1258,6 +1258,8 @@ kgspInitRm_IMPL
return NV_ERR_INVALID_ARGUMENT;
}
pKernelGsp->bInInit = NV_TRUE;
// Need to hold the GPU instance lock in order to write to the RPC queue
NV_ASSERT_OK_OR_GOTO(status,
rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE,
@@ -1278,7 +1280,7 @@ kgspInitRm_IMPL
{
KernelGspVbiosImg *pVbiosImg = NULL;
// Try and extract a VBIOS image.
// Try and extract a VBIOS image.
status = kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, &pVbiosImg);
if (status == NV_OK)
@@ -1403,6 +1405,14 @@ kgspInitRm_IMPL
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspStartLogPolling(pGpu, pKernelGsp), done);
done:
pKernelGsp->bInInit = NV_FALSE;
if (status != NV_OK)
{
// Preserve any captured gsp-rm logs
libosPreserveLogs(&pKernelGsp->logDecode);
}
if (gpusLockedMask != 0)
{
rmGpuGroupLockRelease(gpusLockedMask, GPUS_LOCK_FLAGS_NONE);
@@ -1520,7 +1530,7 @@ kgspDumpGspLogs_IMPL
NvBool bSyncNvLog
)
{
if (pKernelGsp->pLogElf || bSyncNvLog)
if (pKernelGsp->bInInit || pKernelGsp->pLogElf || bSyncNvLog)
libosExtractLogs(&pKernelGsp->logDecode, bSyncNvLog);
}

5
src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c
View File

@@ -1959,6 +1959,7 @@ memmgrFillComprInfo_IMPL
{
const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig =
kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu));
NvU32 size;
portMemSet(pComprInfo, 0, sizeof(*pComprInfo));
@@ -1969,10 +1970,12 @@ memmgrFillComprInfo_IMPL
NV_ASSERT(compTagStartOffset != ~(NvU32)0);
size = pageSize * pageCount;
pComprInfo->compPageShift = pMemorySystemConfig->comprPageShift;
pComprInfo->compTagLineMin = compTagStartOffset;
pComprInfo->compPageIndexLo = (NvU32)(surfOffset >> pComprInfo->compPageShift);
pComprInfo->compPageIndexHi = (NvU32)((surfOffset + pageSize * pageCount - 1) >> pComprInfo->compPageShift);
pComprInfo->compPageIndexHi = (NvU32)((surfOffset + size - 1) >> pComprInfo->compPageShift);
pComprInfo->compTagLineMultiplier = 1;
return NV_OK;

2
src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
View File

@@ -751,6 +751,8 @@ NvBool gpumgrIsDeviceRmFirmwareCapable
0x2236, // A10 SKU215 Pris-24
0x2237, // A10G SKU215 Pris-24
0x25B6, // A16
0x20F5, // A800-80
0x20F6, // A800-40
};
NvU32 count = NV_ARRAY_ELEMENTS(defaultGspRmGpus);
NvU32 i;