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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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92 lines
6.3 KiB
C
92 lines
6.3 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __ga100_dev_runlist_h__
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#define __ga100_dev_runlist_h__
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#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
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#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */
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#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */
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#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */
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#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */
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#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */
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#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */
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#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */
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#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */
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#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */
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#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */
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#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */
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#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */
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#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */
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#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */
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#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */
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#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */
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#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */
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#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */
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#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */
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#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */
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#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */
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#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */
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#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */
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#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */
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#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */
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#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */
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#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */
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#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */
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#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */
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#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */
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#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */
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#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */
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#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */
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#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */
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#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */
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#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */
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#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
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#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */
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#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */
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#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */
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#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */
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#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
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#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
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#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
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#define NV_RUNLIST_INTERNAL_DOORBELL 0x090 /* -W-4R */
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#define NV_RUNLIST_INTERNAL_DOORBELL_CHID 11:0 /* */
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#define NV_RUNLIST_INTERNAL_DOORBELL_CHID_HW 10:0 /* -WXUF */
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#define NV_RUNLIST_INTERNAL_DOORBELL_GFID 21:16 /* -WXUF */
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#define NV_RUNLIST_PREEMPT 0x098 /* RW-4R */
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#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
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#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */
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#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */
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#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */
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#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
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#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
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#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */
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#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
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#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
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#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */
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#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */
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#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */
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#endif // __ga100_dev_runlist_h__
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