mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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412 lines
22 KiB
C
412 lines
22 KiB
C
#ifndef _G_KERNEL_SEC2_NVOC_H_
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#define _G_KERNEL_SEC2_NVOC_H_
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#include "nvoc/runtime.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "g_kernel_sec2_nvoc.h"
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#ifndef KERNEL_SEC2_H
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#define KERNEL_SEC2_H
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#include "core/bin_data.h"
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#include "core/core.h"
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#include "gpu/eng_state.h"
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#include "gpu/falcon/kernel_falcon.h"
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#include "gpu/gpu.h"
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// forward declaration of RM_FLCN_BL_DESC from rmflcnbl.h
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struct _def_rm_flcn_bl_desc;
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typedef struct _def_rm_flcn_bl_desc RM_FLCN_BL_DESC;
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// Private field names are wrapped in PRIVATE_FIELD, which does nothing for
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// the matching C source file, but causes diagnostics to be issued if another
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// source file references the field.
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#ifdef NVOC_KERNEL_SEC2_H_PRIVATE_ACCESS_ALLOWED
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#define PRIVATE_FIELD(x) x
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#else
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#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
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#endif
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struct KernelSec2 {
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const struct NVOC_RTTI *__nvoc_rtti;
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struct OBJENGSTATE __nvoc_base_OBJENGSTATE;
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struct IntrService __nvoc_base_IntrService;
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struct KernelFalcon __nvoc_base_KernelFalcon;
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struct Object *__nvoc_pbase_Object;
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struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE;
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struct IntrService *__nvoc_pbase_IntrService;
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struct CrashCatEngine *__nvoc_pbase_CrashCatEngine;
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struct KernelCrashCatEngine *__nvoc_pbase_KernelCrashCatEngine;
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struct KernelFalcon *__nvoc_pbase_KernelFalcon;
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struct KernelSec2 *__nvoc_pbase_KernelSec2;
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NV_STATUS (*__ksec2ConstructEngine__)(struct OBJGPU *, struct KernelSec2 *, ENGDESCRIPTOR);
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void (*__ksec2RegisterIntrService__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceRecord *);
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NV_STATUS (*__ksec2ServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceServiceNotificationInterruptArguments *);
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NV_STATUS (*__ksec2ConfigureFalcon__)(struct OBJGPU *, struct KernelSec2 *);
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NV_STATUS (*__ksec2ResetHw__)(struct OBJGPU *, struct KernelSec2 *);
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NV_STATUS (*__ksec2StateLoad__)(struct OBJGPU *, struct KernelSec2 *, NvU32);
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NvU32 (*__ksec2ReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelSec2 *, NvU32);
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const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveBlUcode__)(struct OBJGPU *, struct KernelSec2 *);
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NV_STATUS (*__ksec2GetGenericBlUcode__)(struct OBJGPU *, struct KernelSec2 *, const RM_FLCN_BL_DESC **, const NvU8 **);
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const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveSecurescrubUcode__)(struct OBJGPU *, struct KernelSec2 *);
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NvBool (*__ksec2Configured__)(struct KernelSec2 *);
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NvU32 (*__ksec2PriRead__)(struct KernelSec2 *, NvU32);
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void (*__ksec2RegWrite__)(struct OBJGPU *, struct KernelSec2 *, NvU32, NvU32);
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NvU32 (*__ksec2MaskDmemAddr__)(struct OBJGPU *, struct KernelSec2 *, NvU32);
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void (*__ksec2StateDestroy__)(POBJGPU, struct KernelSec2 *);
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void (*__ksec2Vprintf__)(struct KernelSec2 *, NvBool, const char *, va_list);
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NvBool (*__ksec2ClearInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceClearInterruptArguments *);
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void (*__ksec2PriWrite__)(struct KernelSec2 *, NvU32, NvU32);
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void *(*__ksec2MapBufferDescriptor__)(struct KernelSec2 *, CrashCatBufferDescriptor *);
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void (*__ksec2SyncBufferDescriptor__)(struct KernelSec2 *, CrashCatBufferDescriptor *, NvU32, NvU32);
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NvU32 (*__ksec2RegRead__)(struct OBJGPU *, struct KernelSec2 *, NvU32);
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NvBool (*__ksec2IsPresent__)(POBJGPU, struct KernelSec2 *);
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NvU32 (*__ksec2ServiceInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceServiceInterruptArguments *);
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void (*__ksec2ReadEmem__)(struct KernelSec2 *, NvU64, NvU64, void *);
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const NvU32 *(*__ksec2GetScratchOffsets__)(struct KernelSec2 *, NV_CRASHCAT_SCRATCH_GROUP_ID);
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void (*__ksec2Unload__)(struct KernelSec2 *);
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NV_STATUS (*__ksec2StateUnload__)(POBJGPU, struct KernelSec2 *, NvU32);
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NvU32 (*__ksec2GetWFL0Offset__)(struct KernelSec2 *);
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NV_STATUS (*__ksec2StateInitLocked__)(POBJGPU, struct KernelSec2 *);
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NV_STATUS (*__ksec2StatePreLoad__)(POBJGPU, struct KernelSec2 *, NvU32);
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NV_STATUS (*__ksec2StatePostUnload__)(POBJGPU, struct KernelSec2 *, NvU32);
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NV_STATUS (*__ksec2StatePreUnload__)(POBJGPU, struct KernelSec2 *, NvU32);
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NV_STATUS (*__ksec2StateInitUnlocked__)(POBJGPU, struct KernelSec2 *);
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void (*__ksec2InitMissing__)(POBJGPU, struct KernelSec2 *);
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NV_STATUS (*__ksec2StatePreInitLocked__)(POBJGPU, struct KernelSec2 *);
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NV_STATUS (*__ksec2StatePreInitUnlocked__)(POBJGPU, struct KernelSec2 *);
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NV_STATUS (*__ksec2StatePostLoad__)(POBJGPU, struct KernelSec2 *, NvU32);
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void (*__ksec2UnmapBufferDescriptor__)(struct KernelSec2 *, CrashCatBufferDescriptor *);
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void (*__ksec2ReadDmem__)(struct KernelSec2 *, NvU32, NvU32, void *);
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const RM_FLCN_BL_DESC *pGenericBlUcodeDesc;
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const NvU8 *pGenericBlUcodeImg;
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};
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#ifndef __NVOC_CLASS_KernelSec2_TYPEDEF__
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#define __NVOC_CLASS_KernelSec2_TYPEDEF__
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typedef struct KernelSec2 KernelSec2;
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#endif /* __NVOC_CLASS_KernelSec2_TYPEDEF__ */
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#ifndef __nvoc_class_id_KernelSec2
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#define __nvoc_class_id_KernelSec2 0x2f36c9
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#endif /* __nvoc_class_id_KernelSec2 */
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelSec2;
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#define __staticCast_KernelSec2(pThis) \
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((pThis)->__nvoc_pbase_KernelSec2)
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#ifdef __nvoc_kernel_sec2_h_disabled
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#define __dynamicCast_KernelSec2(pThis) ((KernelSec2*)NULL)
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#else //__nvoc_kernel_sec2_h_disabled
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#define __dynamicCast_KernelSec2(pThis) \
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((KernelSec2*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelSec2)))
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#endif //__nvoc_kernel_sec2_h_disabled
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#define PDB_PROP_KSEC2_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE.
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#define PDB_PROP_KSEC2_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING
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NV_STATUS __nvoc_objCreateDynamic_KernelSec2(KernelSec2**, Dynamic*, NvU32, va_list);
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NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32);
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#define __objCreate_KernelSec2(ppNewObj, pParent, createFlags) \
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__nvoc_objCreate_KernelSec2((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
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#define ksec2ConstructEngine(pGpu, pKernelSec2, arg0) ksec2ConstructEngine_DISPATCH(pGpu, pKernelSec2, arg0)
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#define ksec2ConstructEngine_HAL(pGpu, pKernelSec2, arg0) ksec2ConstructEngine_DISPATCH(pGpu, pKernelSec2, arg0)
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#define ksec2RegisterIntrService(pGpu, pKernelSec2, pRecords) ksec2RegisterIntrService_DISPATCH(pGpu, pKernelSec2, pRecords)
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#define ksec2RegisterIntrService_HAL(pGpu, pKernelSec2, pRecords) ksec2RegisterIntrService_DISPATCH(pGpu, pKernelSec2, pRecords)
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#define ksec2ServiceNotificationInterrupt(arg0, arg1, arg2) ksec2ServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2)
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#define ksec2ServiceNotificationInterrupt_HAL(arg0, arg1, arg2) ksec2ServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2)
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#define ksec2ConfigureFalcon(pGpu, pKernelSec2) ksec2ConfigureFalcon_DISPATCH(pGpu, pKernelSec2)
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#define ksec2ConfigureFalcon_HAL(pGpu, pKernelSec2) ksec2ConfigureFalcon_DISPATCH(pGpu, pKernelSec2)
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#define ksec2ResetHw(pGpu, pKernelSec2) ksec2ResetHw_DISPATCH(pGpu, pKernelSec2)
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#define ksec2ResetHw_HAL(pGpu, pKernelSec2) ksec2ResetHw_DISPATCH(pGpu, pKernelSec2)
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#define ksec2StateLoad(pGpu, pKernelSec2, arg0) ksec2StateLoad_DISPATCH(pGpu, pKernelSec2, arg0)
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#define ksec2StateLoad_HAL(pGpu, pKernelSec2, arg0) ksec2StateLoad_DISPATCH(pGpu, pKernelSec2, arg0)
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#define ksec2ReadUcodeFuseVersion(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId)
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#define ksec2ReadUcodeFuseVersion_HAL(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId)
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#define ksec2GetBinArchiveBlUcode(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2)
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#define ksec2GetBinArchiveBlUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2)
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#define ksec2GetGenericBlUcode(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg)
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#define ksec2GetGenericBlUcode_HAL(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg)
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#define ksec2GetBinArchiveSecurescrubUcode(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2)
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#define ksec2GetBinArchiveSecurescrubUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2)
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#define ksec2Configured(arg0) ksec2Configured_DISPATCH(arg0)
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#define ksec2PriRead(arg0, offset) ksec2PriRead_DISPATCH(arg0, offset)
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#define ksec2RegWrite(pGpu, pKernelFlcn, offset, data) ksec2RegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data)
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#define ksec2MaskDmemAddr(pGpu, pKernelFlcn, addr) ksec2MaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr)
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#define ksec2StateDestroy(pGpu, pEngstate) ksec2StateDestroy_DISPATCH(pGpu, pEngstate)
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#define ksec2Vprintf(arg0, bReportStart, fmt, args) ksec2Vprintf_DISPATCH(arg0, bReportStart, fmt, args)
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#define ksec2ClearInterrupt(pGpu, pIntrService, pParams) ksec2ClearInterrupt_DISPATCH(pGpu, pIntrService, pParams)
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#define ksec2PriWrite(arg0, offset, data) ksec2PriWrite_DISPATCH(arg0, offset, data)
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#define ksec2MapBufferDescriptor(arg0, pBufDesc) ksec2MapBufferDescriptor_DISPATCH(arg0, pBufDesc)
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#define ksec2SyncBufferDescriptor(arg0, pBufDesc, offset, size) ksec2SyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size)
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#define ksec2RegRead(pGpu, pKernelFlcn, offset) ksec2RegRead_DISPATCH(pGpu, pKernelFlcn, offset)
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#define ksec2IsPresent(pGpu, pEngstate) ksec2IsPresent_DISPATCH(pGpu, pEngstate)
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#define ksec2ServiceInterrupt(pGpu, pIntrService, pParams) ksec2ServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams)
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#define ksec2ReadEmem(arg0, offset, size, pBuf) ksec2ReadEmem_DISPATCH(arg0, offset, size, pBuf)
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#define ksec2GetScratchOffsets(arg0, scratchGroupId) ksec2GetScratchOffsets_DISPATCH(arg0, scratchGroupId)
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#define ksec2Unload(arg0) ksec2Unload_DISPATCH(arg0)
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#define ksec2StateUnload(pGpu, pEngstate, arg0) ksec2StateUnload_DISPATCH(pGpu, pEngstate, arg0)
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#define ksec2GetWFL0Offset(arg0) ksec2GetWFL0Offset_DISPATCH(arg0)
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#define ksec2StateInitLocked(pGpu, pEngstate) ksec2StateInitLocked_DISPATCH(pGpu, pEngstate)
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#define ksec2StatePreLoad(pGpu, pEngstate, arg0) ksec2StatePreLoad_DISPATCH(pGpu, pEngstate, arg0)
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#define ksec2StatePostUnload(pGpu, pEngstate, arg0) ksec2StatePostUnload_DISPATCH(pGpu, pEngstate, arg0)
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#define ksec2StatePreUnload(pGpu, pEngstate, arg0) ksec2StatePreUnload_DISPATCH(pGpu, pEngstate, arg0)
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#define ksec2StateInitUnlocked(pGpu, pEngstate) ksec2StateInitUnlocked_DISPATCH(pGpu, pEngstate)
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#define ksec2InitMissing(pGpu, pEngstate) ksec2InitMissing_DISPATCH(pGpu, pEngstate)
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#define ksec2StatePreInitLocked(pGpu, pEngstate) ksec2StatePreInitLocked_DISPATCH(pGpu, pEngstate)
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#define ksec2StatePreInitUnlocked(pGpu, pEngstate) ksec2StatePreInitUnlocked_DISPATCH(pGpu, pEngstate)
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#define ksec2StatePostLoad(pGpu, pEngstate, arg0) ksec2StatePostLoad_DISPATCH(pGpu, pEngstate, arg0)
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#define ksec2UnmapBufferDescriptor(arg0, pBufDesc) ksec2UnmapBufferDescriptor_DISPATCH(arg0, pBufDesc)
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#define ksec2ReadDmem(arg0, offset, size, pBuf) ksec2ReadDmem_DISPATCH(arg0, offset, size, pBuf)
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NV_STATUS ksec2ConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0);
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static inline NV_STATUS ksec2ConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0) {
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return pKernelSec2->__ksec2ConstructEngine__(pGpu, pKernelSec2, arg0);
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}
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void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[171]);
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static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[171]) {
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pKernelSec2->__ksec2RegisterIntrService__(pGpu, pKernelSec2, pRecords);
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}
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NV_STATUS ksec2ServiceNotificationInterrupt_IMPL(struct OBJGPU *arg0, struct KernelSec2 *arg1, IntrServiceServiceNotificationInterruptArguments *arg2);
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static inline NV_STATUS ksec2ServiceNotificationInterrupt_DISPATCH(struct OBJGPU *arg0, struct KernelSec2 *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) {
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return arg1->__ksec2ServiceNotificationInterrupt__(arg0, arg1, arg2);
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}
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NV_STATUS ksec2ConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2);
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NV_STATUS ksec2ConfigureFalcon_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2);
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NV_STATUS ksec2ConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2);
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static inline NV_STATUS ksec2ConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
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return pKernelSec2->__ksec2ConfigureFalcon__(pGpu, pKernelSec2);
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}
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NV_STATUS ksec2ResetHw_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2);
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static inline NV_STATUS ksec2ResetHw_5baef9(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
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NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED);
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}
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static inline NV_STATUS ksec2ResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
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return pKernelSec2->__ksec2ResetHw__(pGpu, pKernelSec2);
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}
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NV_STATUS ksec2StateLoad_GH100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 arg0);
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static inline NV_STATUS ksec2StateLoad_56cd7a(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 arg0) {
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return NV_OK;
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}
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static inline NV_STATUS ksec2StateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 arg0) {
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return pKernelSec2->__ksec2StateLoad__(pGpu, pKernelSec2, arg0);
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}
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static inline NvU32 ksec2ReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) {
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return 0;
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}
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NvU32 ksec2ReadUcodeFuseVersion_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId);
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static inline NvU32 ksec2ReadUcodeFuseVersion_474d46(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) {
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NV_ASSERT_OR_RETURN_PRECOMP(0, 0);
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}
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static inline NvU32 ksec2ReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) {
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return pKernelSec2->__ksec2ReadUcodeFuseVersion__(pGpu, pKernelSec2, ucodeId);
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}
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const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2);
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static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_80f438(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
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NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0));
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}
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static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
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return pKernelSec2->__ksec2GetBinArchiveBlUcode__(pGpu, pKernelSec2);
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}
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NV_STATUS ksec2GetGenericBlUcode_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg);
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static inline NV_STATUS ksec2GetGenericBlUcode_5baef9(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg) {
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NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED);
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}
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static inline NV_STATUS ksec2GetGenericBlUcode_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg) {
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return pKernelSec2->__ksec2GetGenericBlUcode__(pGpu, pKernelSec2, ppDesc, ppImg);
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}
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const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_AD10X(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2);
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static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_80f438(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
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NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0));
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}
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static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) {
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return pKernelSec2->__ksec2GetBinArchiveSecurescrubUcode__(pGpu, pKernelSec2);
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}
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static inline NvBool ksec2Configured_DISPATCH(struct KernelSec2 *arg0) {
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return arg0->__ksec2Configured__(arg0);
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}
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static inline NvU32 ksec2PriRead_DISPATCH(struct KernelSec2 *arg0, NvU32 offset) {
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return arg0->__ksec2PriRead__(arg0, offset);
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}
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static inline void ksec2RegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 offset, NvU32 data) {
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pKernelFlcn->__ksec2RegWrite__(pGpu, pKernelFlcn, offset, data);
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}
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static inline NvU32 ksec2MaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 addr) {
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return pKernelFlcn->__ksec2MaskDmemAddr__(pGpu, pKernelFlcn, addr);
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}
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static inline void ksec2StateDestroy_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) {
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pEngstate->__ksec2StateDestroy__(pGpu, pEngstate);
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}
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static inline void ksec2Vprintf_DISPATCH(struct KernelSec2 *arg0, NvBool bReportStart, const char *fmt, va_list args) {
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arg0->__ksec2Vprintf__(arg0, bReportStart, fmt, args);
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}
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static inline NvBool ksec2ClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceClearInterruptArguments *pParams) {
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return pIntrService->__ksec2ClearInterrupt__(pGpu, pIntrService, pParams);
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}
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static inline void ksec2PriWrite_DISPATCH(struct KernelSec2 *arg0, NvU32 offset, NvU32 data) {
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arg0->__ksec2PriWrite__(arg0, offset, data);
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}
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|
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static inline void *ksec2MapBufferDescriptor_DISPATCH(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc) {
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return arg0->__ksec2MapBufferDescriptor__(arg0, pBufDesc);
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}
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static inline void ksec2SyncBufferDescriptor_DISPATCH(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) {
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arg0->__ksec2SyncBufferDescriptor__(arg0, pBufDesc, offset, size);
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}
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|
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static inline NvU32 ksec2RegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 offset) {
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return pKernelFlcn->__ksec2RegRead__(pGpu, pKernelFlcn, offset);
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}
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|
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static inline NvBool ksec2IsPresent_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) {
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|
return pEngstate->__ksec2IsPresent__(pGpu, pEngstate);
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|
}
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|
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static inline NvU32 ksec2ServiceInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceServiceInterruptArguments *pParams) {
|
|
return pIntrService->__ksec2ServiceInterrupt__(pGpu, pIntrService, pParams);
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|
}
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|
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static inline void ksec2ReadEmem_DISPATCH(struct KernelSec2 *arg0, NvU64 offset, NvU64 size, void *pBuf) {
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|
arg0->__ksec2ReadEmem__(arg0, offset, size, pBuf);
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|
}
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|
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static inline const NvU32 *ksec2GetScratchOffsets_DISPATCH(struct KernelSec2 *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) {
|
|
return arg0->__ksec2GetScratchOffsets__(arg0, scratchGroupId);
|
|
}
|
|
|
|
static inline void ksec2Unload_DISPATCH(struct KernelSec2 *arg0) {
|
|
arg0->__ksec2Unload__(arg0);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StateUnload_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) {
|
|
return pEngstate->__ksec2StateUnload__(pGpu, pEngstate, arg0);
|
|
}
|
|
|
|
static inline NvU32 ksec2GetWFL0Offset_DISPATCH(struct KernelSec2 *arg0) {
|
|
return arg0->__ksec2GetWFL0Offset__(arg0);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) {
|
|
return pEngstate->__ksec2StateInitLocked__(pGpu, pEngstate);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) {
|
|
return pEngstate->__ksec2StatePreLoad__(pGpu, pEngstate, arg0);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) {
|
|
return pEngstate->__ksec2StatePostUnload__(pGpu, pEngstate, arg0);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) {
|
|
return pEngstate->__ksec2StatePreUnload__(pGpu, pEngstate, arg0);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) {
|
|
return pEngstate->__ksec2StateInitUnlocked__(pGpu, pEngstate);
|
|
}
|
|
|
|
static inline void ksec2InitMissing_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) {
|
|
pEngstate->__ksec2InitMissing__(pGpu, pEngstate);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StatePreInitLocked_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) {
|
|
return pEngstate->__ksec2StatePreInitLocked__(pGpu, pEngstate);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) {
|
|
return pEngstate->__ksec2StatePreInitUnlocked__(pGpu, pEngstate);
|
|
}
|
|
|
|
static inline NV_STATUS ksec2StatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) {
|
|
return pEngstate->__ksec2StatePostLoad__(pGpu, pEngstate, arg0);
|
|
}
|
|
|
|
static inline void ksec2UnmapBufferDescriptor_DISPATCH(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc) {
|
|
arg0->__ksec2UnmapBufferDescriptor__(arg0, pBufDesc);
|
|
}
|
|
|
|
static inline void ksec2ReadDmem_DISPATCH(struct KernelSec2 *arg0, NvU32 offset, NvU32 size, void *pBuf) {
|
|
arg0->__ksec2ReadDmem__(arg0, offset, size, pBuf);
|
|
}
|
|
|
|
void ksec2Destruct_IMPL(struct KernelSec2 *pKernelSec2);
|
|
|
|
#define __nvoc_ksec2Destruct(pKernelSec2) ksec2Destruct_IMPL(pKernelSec2)
|
|
#undef PRIVATE_FIELD
|
|
|
|
|
|
#endif // KERNEL_SEC2_H
|
|
|
|
#ifdef __cplusplus
|
|
} // extern "C"
|
|
#endif
|
|
|
|
#endif // _G_KERNEL_SEC2_NVOC_H_
|