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48 lines
3.2 KiB
C
48 lines
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __ga100_dev_fb_h__
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#define __ga100_dev_fb_h__
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#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR 0x00100C10 /* RW-4R */
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#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
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#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08 31:0 /* RWIVF */
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#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08_INIT 0x00000000 /* RWI-V */
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#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI 0x00100C40 /* RW-4R */
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#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_MASK 0x7F /* */
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#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_ADR_63_40 23:0 /* RWIVF */
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#define NV_PFB_FBHUB_POISON_INTR_VECTOR 0x00100A24 /* R--4R */
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#define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW 7:0 /* R-IVF */
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#define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT 135 /* R-I-V */
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#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK 0x001FA7C8 /* RW-4R */
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#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFB_PRI_MMU_LOCK_ADDR_LO 0x001FA82C /* RW-4R */
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#define NV_PFB_PRI_MMU_LOCK_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7C8 /* */
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#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_VAL 31:4 /* RWEVF */
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#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_ALIGNMENT 0x0000000c /* */
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#define NV_PFB_PRI_MMU_LOCK_ADDR_HI 0x001FA830 /* RW-4R */
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#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_VAL 31:4 /* RWEVF */
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#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_ALIGNMENT 0x0000000c /* */
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#endif // __ga100_dev_fb_h__
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